TLV1549 SLAA005 TLV1549-TO-68HC05 TLV1549-TO-TMS7000 TLV1549-TO-80C51-L 68HC05 - Datasheet Archive

 

10-Bit Serial-Out ADC to Popular 3.3-V Microcontrollers SLAA005 August 1994 IMPORTANT NOTICE Texas Instruments (TI) reserves the

 

Interfacing the TLV1549 TLV1549 10-Bit Serial-Out ADC to Popular 3.3-V Microcontrollers SLAA005 SLAA005 August 1994 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright © 1994, Texas Instruments Incorporated Contents Title Page INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Use of Software Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 TLV1549-TO-68HC05 TLV1549-TO-68HC05 INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microcontroller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Status Register (SPSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Data I/O Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Listing for the TLV1549-to-MC68HC705 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 2 3 3 3 3 3 4 TLV1549-TO-TMS7000 TLV1549-TO-TMS7000 INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microcontroller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Provision of TLV1549 TLV1549 Chip Select (CS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Reformatting and Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Listing for TLV1549-to-TMS70C02 Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5 5 5 6 6 6 7 TLV1549-TO-80C51-L TLV1549-TO-80C51-L INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Microcontroller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serial I/O Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Software Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Program Listing for the TLV1549-to-80C51-L Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ANALOG CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Reference for the TLV1549 TLV1549 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Grounding and Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 11 11 APPENDIX A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 iii List of Illustrations Figure Title Page µs) . . . . . . . 1 1 2 TLV1549 TLV1549 10-Bit Serial Out ADC-to-MC68HC705C8 Microcontroller Interface . . . . . . . . . . . . . . . . . . . . 2 3 Shift Register Operation of the Serial Peripheral Interface (SPI) 4 TLV1549 TLV1549 10Bit Serial Out ADCtoTMS70C02 Microcontroller Interface 5 TLV1549 TLV1549 10Bit Serial Out ADCto80C51L Microcontroller Interface 6 iv Timing for the 11 to 16Clock Transfer Using CS (Serial Transfer Completed After 21 UserAdjustable 2.5V Reference Circuit . 3 . 5 . 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 INTRODUCTION The TLV1549 TLV1549 is a 10-bit serial out analog-to-digital converter that operates from a 3.3-V (± 0.3 V) single supply. It uses a switched-capacitor successive-approximation method to perform the conversion in a maximum of 21 µs. This application report describes how to interface the TLV1549 TLV1549 to three popular microcontrollers which operate from a single 3.3-V supply rail. These are the 68HC05 68HC05, the TMS70C02 TMS70C02, and the 80C51-L 80C51-L. Interface Timing The timing for each of the interfaces described in this application report is illustrated in Figure 1. One chip-select (CS) pulse is used for each 10-bit conversion and 16 CLOCK I/O pulses are between each CS. I/O CLOCK 1 2 3 4 5 6 7 8 9 10 11 Sample Cycle B DATA OUT A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Low Level Previous Conversion Data MSB LSB Initialize ÏÏÏ ÏÏÏ ÏÏ ÏÏ ÑÑÑ ÑÑÑ CS 16 1 Hi-Z State B9 A/D Conversion Interval ( 21 µs) Initialize Figure 1. Timing for the 11- to 16-Clock Transfer Using CS (Serial Transfer Completed After 21 µs) Use of Software Subroutines The subroutines included in this application report have been developed as much as possible as relocatable pieces of software. They include a provision for setting the number of consecutive conversions to be performed. This is either set in the main program as in the TMS7000 TMS7000 and 80C51-L 80C51-L examples or inside the subroutine as used in the 68HC05 68HC05 example, by programming the number of conversions into COUNT. It is recommended that at least two conversions are performed either after a power-up reset or after a protracted interval between the last conversion. This enables the TLV1549 TLV1549 on-board sample-and-hold to acquire the most recent signal level during the first conversion cycle before converting it into digital form during the second cycle. Data Format In whatever format the data arrives at the microcontroller, it is important to ensure that any reformatting, if required, puts the data into a convenient final format. This application report places the most significant byte of the conversion result in one byte of random access memory (RAM) and the least significant byte in an adjacent byte of RAM. The two least significant bits of the 10-bit result are placed in the least significant bit locations of their RAM location. This format gives the user the flexibility to use only 8-bit precision data, if so required, to add the MS and LS bytes together for use in 16 bit wide architectures, to view the two least significant bits of the result for fine tuning applications, or to reformat into another more convenient format. 1 TLV1549-TO-68HC05 TLV1549-TO-68HC05 INTERFACE Microcontroller Features The M68HC05 M68HC05 family of microcontrollers consists of several different product variants of the basic architecture. It is important that the correct product type is specified to ensure that it contains all the features and attributes necessary to fulfill all its eventual system requirements. In the case of its suitability for interfacing to the TLV1549 TLV1549 serial out ADC, the M68HC05 M68HC05 product type should contain a serial peripheral interface (SPI). Several types contain this feature including the MC68HC705C8 MC68HC705C8, which was chosen as the target for this ADC interface. VCC+ (3.3 V ± 0.3 V) VCC 1/2 TLV2262A TLV2262A Analog Input (0 V ­ VCC/2) + _ VCC+ VCC PD4/SCK I/O CLOCK REF + DATA OUT PD2/MISO XTAL1 ANALOG IN XTAL2 REF ­ IRQ TLV1549 TLV1549 10 k 2 MHz (max) PC7 CS 10 k SS Interrupt (optional) VCC ­ (0 V) MC68HC705C8 MC68HC705C8 VSS 0V NOTE: For 68HC05 68HC05 operating off 3.3 V dc supply: Maximum I/O clock frequency = maximum crystal clock frequency/4 = 0.5 MHz Figure 2. TLV1549 TLV1549 10-Bit Serial Out ADC-to-MC68HC705C8 Microcontroller Interface Interface Circuit Figure 2 shows the circuit interconnections for the TLV1549 TLV1549 ­ MC68HC705C8 MC68HC705C8 microcontroller interface. No glue logic is required. The positive reference to the TLV1549 TLV1549 is provided directly from the VCC+ supply. The analog signal is scaled by an appropriate factor (a gain of two in this case) and buffered by one half of a TLV2262A TLV2262A dual operational amplifier. The three digital interface terminals, I/O CLOCK, DATA OUT, and CS of the TLV1549 TLV1549 connect directly to the PD4/SCK, PD2/MISO, and PC7 terminals respectively of the microcontroller. When the SPI is enabled, PD4 becomes SCK, which is the serial clock output, and PD2 becomes the master in slave out (MISO) terminal. When programmed to be a master device, the microcontroller receives serial data at its MISO terminal. Figure 3 shows the shift register operation of the SPI when connected to a serial output peripheral component such as the TLV1549 TLV1549. The MC68HC705C8 MC68HC705C8 operates as the master device and the TLV1549 TLV1549 acts as the slave. 2 I/O CLOCK SCK DATA OUT MISO SPI Shift Register TLV1549 TLV1549 Receive Buffer MC68HC705C8 MC68HC705C8 Figure 3. Shift Register Operation of the Serial Peripheral Interface (SPI) Software Considerations The three registers which are used for SPI communications are: Serial peripheral control register (SPCR) Serial peripheral status register (SPSR) Serial peripheral data I/O register (SPDR) Serial Peripheral Control Register (SPCR) Bits 0 and 1 of the SPCR program the SPI master bit rate. With bits 0 and 1 set to 0, SCK runs at the internal processor clock/2. This means that SCK operates at one quarter of the microcontroller XTAL frequency. Bit 2 determines the phase relationship between the clock transmitted at SCK and the data appearing on the MISO terminal. If a 0 is placed in bit 3, SCK idles low. This is the correct condition for the TLV1549 TLV1549. A 1 in bit 6 of the SPCR enables the SPI. A 0 in bit 6 disables the SPI. A 1 in bit 4 (MSTR) confers the status of master to the microcontroller. Serial Peripheral Status Register (SPSR) The most important bit of the SPSR is bit 7 (SPIF). When set to 1, it indicates that a data transfer between the TLV1549 TLV1549 and the microcontroller has been completed. The SPIF bit is automatically cleared when the SPSR is read and the SPI data register is accessed. Serial Peripheral Data I/O Register (SPDR) When the SPIF bit of the SPSR is 1, the SPDR contains the received byte of information from the converter. The contents of SPDR can then be read into a suitable register or location. Program Listing The program listing for the TLV1549-to-MC68HC705 interface shown in Figure 2 is included in the following section. COUNT has been set to 2; this ensures that two conversions are performed each time the ADC subroutine is used. The first conversion flushes out potentially erroneous data from the converter output registers. For test purposes, the main program simply performs continuous repeat jumps to the ADC subroutine. The SPI expects the most significant bit of each received byte to arrive first which is compatible with the order of the TLV1549 TLV1549 output bit stream. This means that no reformatting of the most significant bit of the 10-bit conversion result is required. However, the least significant byte does need to be shifted right by 6 bits. 3 Program Listing for the TLV1549-to-MC68HC705 Interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 4 000A 000B 000C 0002 0006 0011 000E 000F 0010 0050 0051 1FFE 1FFF 0052 0160 0160 0162 0165 0167 016A 016D 016F 0171 0173 0175 0177 0179 017A 017C 017E 0180 0182 0184 0186 0189 018B 018D 018F 0191 0194 0196 0198 019A 019C 019E 01A0 01A1 01A3 01A4 01A6 01A7 A601 C71FFE C71FFE A660 C71FFF C71FFF CD016F CD016F 20FB 1E06 A602 B752 A610 1E02 4A 26FB 1F02 A650 B70A A600 B70C 0F0BFD B60C B750 A600 B70C OF00FD OF00FD B60C B751 3A52 B652 26D7 A606 98 3651 4A 26FA 81 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * TLV1549 TLV1549 ­ MC68HC705C8 MC68HC705C8 Interface Program * * * * This program contains a subroutine ADC which reads * * the serial data from two conversions of the TLV1549 TLV1549 * * and places the MSByte in address 50H and the LSByte * * in address 51H. * * The data from the first conversion(potentially * * erroneous) is overwritten by the result from the * * second conversion. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * SPCR EQU 0AH * * * * * * * * * * * * * * * * * * SPSR EQU OBH * * SPDR EQU 0CH * * PORTC EQU 02H * Names, Peripheral, and * DDRC EQU 06H * Control Registers * SCDAT EQU 11H * * SCCR1 EQU 0EH * * SCCR2 EQU 0FH * * SCSR EQU 10H * * * * * * * * * * * * * * * * * * MSBYTE EQU 50H * * * * * * * * * * * * * * * * * * LSBYTE EQU 51H * Names working RAM addresses * RESETH EQU 1FFEH * * RESETL EQU 1FFFH * * COUNT EQU 52H * * * * * * * * * * * * * * * * * * ORG 160H Start Program at 160H LDA #01H STA RESETH Load Reset Vector High Byte LDA #60H STA RESETL Load Reset Vector Low Byte START JSR ADC BRA START ADC BSET 7, DDRC LDA #02H STA COUNT CONVERT LDA #10H CSHIGH BSET 7, PORTC Set Port C bit 7 (TLV1549 TLV1549 CS) high DECA BNE CSHIGH BCLR 7, PORTC Reset TLV1549 TLV1549 CS (Low) LDA #50H Load accumulator with 50H STA SPCR Load SPI control register LDA #00H Load dummy data into accumulator STA SPDR Receive SPI data HBYTE BRCLR 7, SPSR, HBYTE LDA SPDR STA MSBYTE Put MSBYTE in Location 50 LDA #00H Load dummy data into accumulator STA SPDR Receive SPI data LBYTE BRCLR 7, 0B, LBYTE LDA SPDR STA LSBYTE Put LSBYTE in Location 51 DEC COUNT LDA COUNT BNE CONVERT If COUNT = 1, do another conversion LDA #06H * * * * * * * * * * * * * * * * * * FORMAT CLC * * ROR LSBYTE * Reformats LSBYTE * DECA * * BNE FORMAT * * * * * * * * * * * * * * * * * * RTS END TLV1549-TO-TMS7000 TLV1549-TO-TMS7000 INTERFACE Microcontroller Features The entire range of TMS7000 TMS7000 microcontrollers can be operated with a 3-V supply. However, the maximum crystal frequency they will tolerate at this supply voltage (over the full temperature range) is 3 MHz. The inherently longer instruction cycle times that this yields should be taken into account when deciding how many software delay loops are necessary to produce the required delay. Within the family of TMS7000 TMS7000 microcontrollers, three types are available that have a serial port: TMS70Cx2, TMS77C82 TMS77C82, and TMS70Cx8. This application report refers to the TMS70Cx2, but any one of these three types could be chosen to efficiently implement a serial interface to the TLV1549 TLV1549. Three modes of serial communication are available for the serial port: asynchronous mode, isosynchronous mode, and the serial I/O mode. The most suitable of these for interfacing the TMS70Cx2 to the TLV1549 TLV1549 is the serial I/O mode. Interface Circuit The TLV1549-to-TMS70C02 interface circuit is shown in Figure 4. The chip select (CS) of the TLV1549 TLV1549 is controlled by the output from A0 (bit 0 of peripheral port A). VCC + (3.3 V ± 0.3 V) VCC+ VCC VCC 1/2 TLV2262A TLV2262A Analog Input (0 V ­ VCC/2) + _ A4/SCLK I/O CLOCK REF + DATA OUT A5/RXD XTAL1 ANALOG IN XTAL2 REF ­ INT1 TLV1549 TLV1549 10 k 3 MHz (max) A0 CS 10 k SS Interrupt (optional) VCC ­ (0 V) TMS70C02 TMS70C02 VSS 0V NOTE: Maximum I/O clock frequency = microcontroller crystal frequency/8 Figure 4. TLV1549 TLV1549 10-Bit Serial Out ADC-to-TMS70C02 Microcontroller Interface Serial I/O Mode Four peripheral registers are used to set up and control the serial I/O mode of the microcontroller: Serial mode register (SMODE) Serial control register 0 (SCTL0) Serial control register 1 (SCTL1) Serial port status register (SSTAT) The contents of the SMODE register determine the data format and type of communication mode (serial I/O for example). In the serial I/O mode, the frame format of each character is five to eight data bits followed by a stop bit. Setting the number of bits to eight can simplify the software necessary to implement the interface. SCTL0 enables either transmit or receive communication. SCTL1 determines the source of SCLK and programs the frequency of SCLK. 5 SSTAT is a read-only register that is used for checking the status of the serial port. Bit 1 (RXRDY) of SSTAT is 0 when the receive buffer (RXBUF) is empty and 1 when RXBUF is full. Provision of TLV1549 TLV1549 Chip Select (CS) On power-up and/or system reset, the TLV1549 TLV1549 chip-select terminal (CS) should be initialized to a high level. To provide this, one of the bidirectional peripheral port bits can be programmed as an output and set to a 1 for a period of at least 21 µs. This period is provided by a delay loop at the beginning of the ADC subroutine. The number of times the loop is excuted in order to achieve at least 21 µs is dependent on the clock frequency of the microcontroller and the number of instruction cycles contained within the delay loop. The example program listing shown in the section program listing for TLV1549-to-TMS70C02 microcontroller interface executes the loop 16 times, but the loop can be executed less times to optimize the conversion throughput rate. On completion of this delay loop, the particular peripheral port bit is reset to 0, and the converter is now ready to send out data from the previously performed conversion. Data Reformatting and Storage After RXBUF is checked to verify it is full, its contents can be read to a suitable register for subsequent access and processing. In the case of the 10-bit conversion result from the TLV1549 TLV1549, two successive bytes of data are received and each are placed in RXBUF to be read consecutively into two convenient memory locations. The TLV1549 TLV1549 sends the digital result of each conversion with the most significant bit first and the least significant bit last. This is the reverse of the order that the TMS70C02 TMS70C02 expects. A few software instructions are therefore inserted near the end of the conversion subroutine that reformat the data into the correct order for interpretation by the microcontroller. Other Software Considerations The subroutine that services the TLV1549 TLV1549 conversion should be located in a convenient area of memory that is compatible with the rest of the system. For example, all serial port versions of the TMS7000 TMS7000 family have 8K bytes of EPROM. This EPROM is located between addresses E000H E000H (hex) and FFFFH. A converter subroutine start address at the midpoint of this EPROM memory space may be convenient in that it leaves the first half of this space for the location of the main program. The example program listing in the section Program Listing for TLV1549-to-TMS70C02 Microcontroller Interface uses a start location of F006 which is convenient for the emulation system it was developed on. On system reset, the stack pointer is at location 0001H 0001H. In programs that include nested subroutines where the number of RAM locations taken up by the stack becomes large, the stack can interfere with other useful or even critical RAM locations. It is therefore prudent to reposition the stack pointer, immediately after reset, at a higher address in RAM such as 0060H 0060H. This allows the stack plenty of room to grow and avoids interference with lower address RAM locations. Software Listing The following program listing reads in the results of two 10-bit conversions from the TLV1549 TLV1549. The software routine ADC actually reads in the results from N conversions, where N is the contents of the register COUNT. The first conversion in a sequence of conversions may be erroneous because the data received is derived from a previous (probably invalid) sample of the analog signal. It is often useful to flush out this first spurious reading before receiving a second valid conversion result. The setting of the contents of COUNT is performed within the main program and should normally be set to a minimum of two. 6 Program Listing for TLV1549-to-TMS70C02 Microcontroller Interface 0001 0002 0003 0004 0005 0006 0007 0008 0009 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 0020 0021 0022 F006 0023 F006 F007 0024 F008 0025 F009 F00A F00B 0026 F00C F00D F00E 0027 F00F F010 F011 0028 F012 F013 0029 F015 F016 0030 F017 F018 0031 F019 F01A F01B 0032 F01C 0033 F01D F01E 0034 FO1F F020 F021 0035 F022 F023 F024 0036 F025 F026 F027 0037 F028 F029 0038 F02A F02B F02C 0039 F02D F02E 0040 F02F F030 0041 F031 F032 0042 F033 F034 F035 0004 0005 0014 0015 0016 0018 0019 001A 0009 0010 0011 52 60 0D A2 11 05 A2 0C 14 72 02 09 8E F017 E0 EF 22 03 A2 01 04 B2 E6 FA A2 00 04 A2 16 15 A2 C0 18 80 16 26 02 02 E0 F9 80 19 D0 0A A2 16 15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * TLV1549 TLV1549 ­ TMS70C02 TMS70C02 Interface Program * * * * This program contains a subroutine ADC which reads in * * the serial data from two conversions of the TLV1549 TLV1549. The * * data (potentially erroneous) from the first conversion * * is overwritten by the data from the second conversion. * * The most significant byte is placed in register 16. The * * least significant byte is placed in register 17. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * APORT EQU P4 * * * * * * * * * * * * * * * * * * * * ADDR EQU P5 * * SMODE EQU P20 * * SCTL0 EQU P21 * * SSTAT EQU P22 * Name Peripheral Registers * SCTL1 EQU P24 * * RXBUF EQU P25 * * TXBUF EQU P26 * * COUNT EQU R9 * Name Count and Result Registers * MSBYTE EQU R16 * * LSBYTE EQU R17 * * * * * * * * * * * * * * * * * * * * AORG >F006 Set start address of program START MOV %> 60,B Set stack register LDSP MOVP %> 11,ADDR Set up Port A Data Direction Register MOVP %> 0C,SMODE Set up Serial Mode Register MOV %> 02,COUNT Set COUNT = 2 CALL @ADC Call Subroutine ADC JMP START On return from Subroutine ADC, jump to START ADC MOV %> 03,A Put 03 in register A CSHIGH MOVP %> 01,APORT TLV1549 TLV1549 Chip Select goes high DEC A JNZ CSHIGH Decrement the contents of Register A by 1 and jump to CSHIGH if result is not zero MOVP %> 00,APORT TLV1549 TLV1549 Chip Select goes low MOVP %> 16,SCTL0 Set up Serial Control Register 0 MOVP %> C0,SCTL1 Set up Serial Control Register 1 LABEL1 MOVP SSTAT,A Put contents of Serial Status Register in A BTJO %> 2,A,LABEL2 If bit 1 of A is 1, jump to LABEL2 JMP LABEL1 LABEL2 and if not, jump to LABEL1 MOVP RXBUF,A Put contents of RXBUF (MSByte) in A MOV A,R10 Put contents of A into Register 10 MOVP %> 16,SCTL0 Set up Serial Control Register 0 7 0043 F036 A2 F037 C0 F038 18 0044 F039 80 F03A 16 0045 F03B 26 F03C 02 F03D 02 0046 F03E E0 F03F F9 0047 F040 80 F041 19 0048 F042 D0 F043 0B 0049 F044 D2 F045 09 0050 F046 E6 F047 CF 0051 F048 B0 0052 F049 DD F04A 0B 0053 F04B E7 F04C 03 0054 F04D 74 F04E 02 F04F 0B 0055 F050 42 F051 0B F052 11 0056 F053 D5 F054 0C 0057 F055 D5 F056 0E 0058 F057 22 F058 08 0059 F059 42 F05A 0A F05B 0C 0060 F05C B0 0061 F05D DD F05E 0C 0062 F05F DF F060 0E 0063 F061 B2 0064 F062 E6 F063 F8 0065 F064 42 F065 0E F066 10 0066 F067 0A 0067 FFFE 0068 FFFE F006 0069 8 MOVP %>C0,SCTL1 Set up Serial Control Register 1 LABEL3 MOVP SSTAT,A Put contents of Serial Status Register in A BTJO %>2,A,LABEL4 If bit 1 of A is 1, jump to LABEL1 JMP LABEL3 MOVP RXBUF,A Put contents of RXBUF (LSByte) in A MOV A,R11 Put contents of A in Register 11 DEC COUNT (COUNT) ­ 1 JNZ ADC If COUNT is not zero do another conversion CLRC RRC R11 OR %>2,R11 clear carry bit * * * * * * * * * * * * * * * * * * * * * * * Reformats Least Significant Byte * * * * * * * * * * * * * * * * * * * * * * * MOV R11,LSBYTE Put reformatted LSByte in LSBYTE CLR R12 clear register 12 CLR R14 and register 14 MOV %>8,A Set contents of A to 8 MOV R10,R12 LABEL4 and if not, jump to LABEL3 Put contents of register 10 in register 12 JNC LSBIT0 LSBIT0 FORMAT CLRC RRC R12 DEC A JNZ FORMAT * * * * * * * * * * * * * * * * * * * * * * * * * Reformats Most Significant Byte * * * * * * * * * * * * * * * * * * * * * * * * * MOV R14,MSBYTE Put reformatted MSByte into MSBYTE RETS AORG >FFFE DATA START END Return from subroutine ADC Configure Reset vector to point to START RLC R14 TLV1549-TO-80C51-L TLV1549-TO-80C51-L INTERFACE Microcontroller Features The 80C51-L 80C51-L is the 3.3-V supply version of the 80C51 80C51 family of microcontrollers. Various 3.3-V supply versions of the 80C51 80C51 architecture are available from different manufacturers. Individual data sheets should be consulted to establish at which maximum crystal frequency each specific device type can operate. As indicated for the previously described interfaces, the most suitable method of receiving the serial output from the TLV1549 TLV1549 is to configure the serial port of the microcontroller to perform like an 8-bit shift register. The same is true for the 80C51-L 80C51-L. Serial I/O Mode 0 The type of serial communication to and from the 80C51-L 80C51-L is determined by the data inserted into the serial port control register (SCON). The contents of the most significant bits of SCON (bits 7 and 6) determine the operating mode (modes 0, 1, 2, and 3) of the serial port. Mode 0 is the shift register mode and is programmed by placing a 0 in each of bits 7 and 6 of the SCON. Bit 4 (REN) of the SCON is the receive enable bit. This bit is set to 1, while bit 1 (RI) of the SCON is 0, to receive serial data. In this configuration, data is received at bit 0 of port 3 (P3.0). The synchronizing signal for clocking in this data is output at TXD, which is bit 1 of port 3 (P3.1). When configured for mode 0, eight bits are received with no trailing stop bit for each enabling of serial reception. The data is received with the least significant bit expected first, the reverse of the order in which the TLV1549 TLV1549 serial data arrives. Reformatting of the received data is therefore necessary. Interface Circuit Figure 5 shows the interconnections necessary to implement the interface of the TLV1549 TLV1549 to the 80C51-L 80C51-L microcontroller. CS of the TLV1549 TLV1549 is driven by bit 4 of port 3 (P3.4) of the 80C51-L 80C51-L. VCC + (3.3 V ± 0.3 V) VCC+ VCC VCC 1/2 TLV2262A TLV2262A Analog Input (0 V ­ VCC/2) + _ P3.1/TXD I/O CLOCK REF + DATA OUT P3.0/RXD XTAL1 ANALOG IN P3.4 CS XTAL2 REF ­ 10 k P3.3/INT1 TLV1549 TLV1549 10 k Interrupt (optional) VCC ­ (0 V) 80C51-L 80C51-L VSS See Data Sheet for Maximum Frequency 0V NOTE: I/O clock frequency = microcontroller clock frequency/12 Figure 5. TLV1549 TLV1549 10-Bit Serial Out ADC-to-80C51-L Microcontroller Interface Software Listing Similar to the previously described program listings, the following listing contains the subroutine ADC that reads into the 80C51-L 80C51-L ten bits of serial data resulting from a single conversion of the TLV1549 TLV1549. The number of consecutive conversions performed for each jump to subroutine ADC is equal to the number placed in COUNT. The result of each conversion is overwritten by that of the next conversion in the sequence. 9 Program Listing for the TLV1549-to-80C51-L Interface LOC OBJ 0020 0021 REG 0022 0022 0024 0027 0029 002B 002D 002E 0030 0032 0035 0038 003A 003C 003F 0041 0043 0045 0046 0047 7B02 020029 8OF9 D2B4 7410 14 70FD C2B4 759810 3098FD 3098FD C298 A899 3098FD 3098FD C29C C298 A999 1B EB 70E0 0049 004B 004D 004E 004F 0050 0051 0052 0053 0054 0055 0056 0058 0059 005B 005C 005D 005F 0061 0063 7C08 AA00 C3 E8 13 F8 EA 33 FA 1C EC 70F5 EA F520 E9 13 F521 9209 C20F 22 10 LINE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 SOURCE ;* * * ;* ;* ;* ;* ;* ;* ;* ;* ;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * TLV1549 TLV1549 ­ 80C51-L 80C51-L Interface Program * This program contains a subroutine ADC which reads in the serial data from the TLV1549 TLV1549 10-bit ADC and places the most significant byte in address 20H and least significant byte in address 21H * * * * * * * * * * * * * * * * * * * * * * * * * * * * * MSBYTE LSBYTE COUNT START: ADC: DELAY: LABEL1: LABEL2: LOOP: EQU 20H EQU 21H EQU R3 ;* * * * * * * * * * * * * * * * ;* Name data destinations ;* and COUNT register ;* * * * * * * * * * * * * * * * ORG 22H ;Set start address MOV COUNT, #02H ;Set COUNT=2 (Do 2 conversions) JMP ADC ;Jump to subroutine ADC JMP START ;Repeat above again SETB P3.4 ;* * * * * * * * * * * * * * * * MOV A, #10H ;* Set Port3 (bit 4) high DEC A ;* (Sets CS of TLV1549 TLV1549 high) JNZ DELAY :* * * * * * * * * * * * * * * * CLR P3.4 MOV SCON, #10H JNB SCON.0, LABEL1 ;Read in CLR SCON.0 ;most significant MOV R0,SBUF ;byte, place in R0 JNB SCON.0, LABEL2 ;Read in CLR SCON.4 ;least significant CLR SCON.0 ;byte, MOV R1, SBUF ;place in R1 DEC COUNT ;COUNT-1 MOV A, COUNT ; JNZ ADC ;If COUNT not = 0, ;do another conversion MOV R4, #08H ;Put 08H in R4 MOV R2, 00H CLR C :* * * * * * * * * * * * * * * * MOV A, R0 ;* RRC A ;* MOV R0, A ;* Reformats MSByte MOV A, R2 ;* RLC A ;* MOV R2, A ;* DEC R4 ;* MOV A, R4 ;* JNZ LOOP ;* * * * * * * * * * * * * * * * MOV A, R2 ; MOV 20H, A ; MOV A, R1 ;* * * * * * * * * * * * * * * * RRC A ;* MOV 21H, A ;* Reformats LSByte MOV 21H.1, C ;* CLR 21H.7 ;* * * * * * * * * * * * * * * * RET ;Return from subroutine END * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ANALOG CONSIDERATIONS Analog Reference for the TLV1549 TLV1549 The REF + terminal of the TLV1549 TLV1549 can be directly connected to the VCC rail of the device. This produces accurate results for analog input signals right up to the supply rail. However, if the operational amplifier driving the input is supplied from the same single supply as the ADC, the output of the operational amplifier could possibly be nonlinear up to the rail voltage. If this is a concern, a lower reference voltage as shown in Figure 6 can be applied to REF + providing more headroom for the amplifier. The output of the TL2262A TL2262A 3-V single-supply operational amplifier can swing to within 10 mV of its positive supply rail. This effectively loses only two least significant bits (LSBs) off the top of the digital output range of the TLV1549 TLV1549 when both the amplifier and ADC are powered from the same 3-V supply. The circuit shown in Figure 6 provides a 2.5-V reference to the converter, which restores those bits to the digital output of the TLV1549 TLV1549 while the maximum analog input swing is reduced to 2.5 V. VCC (3 V) 20 k 1/2 TL2262A TL2262A + _ Vref (2.5 V) 1 k AD589 AD589 (1.235-V reference) 10 k 10 k GND Figure 6. User Adjustable 2.5-V Reference Circuit PCB Layout As with all precision analog components, care should be taken in laying out the printed-circuit board (PCB) on which the TLV1549 TLV1549 and chosen microcontroller are placed. The interaction between digital and analog signal paths should be minimized by keeping them as far apart as is physically possible within the constraints of the dimensions of the PCB. Grounding and Decoupling Each supply terminal to both the TLV1549 TLV1549 and the microcontroller should be decoupled by a ceramic capacitor of approximately 100 nF in value, situated close to the terminal of the device. Digital and analog ground return paths should be kept separate to prevent any digitally generated currents from corrupting the analog signal. 11 APPENDIX A References MC68HC705C8 MC68HC705C8 Technical Data Manual (1990) M68HC05 M68HC05 Applications Guide TLV1549 TLV1549 Data Sheet TMS7000 TMS7000 Family Data Manual (1991) Embedded Microcontrollers and Processors Vol. 1 12 Motorola Motorola Texas Instruments Incorporated Texas Instruments Incorporated Intel Corporation IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI's standard warranty. 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