TL750M TL751M SLVS021E TL751M05M TL751M12M TL750M05CKC TL750M05CKTE - Datasheet Archive

 

LOW-DROPOUT VOLTAGE REGULATORS SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 D D D D D D D Very Low Dropout Voltage,

 

TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 D D D D D D D Very Low Dropout Voltage, Less Than 0.6 V at 750 mA Low Quiescent Current TTL- and CMOS-Compatible Enable on TL751M TL751M Series 60-V Load-Dump Protection Overvoltage Protection Internal Thermal Overload Protection Internal Overcurrent Limiting Circuitry description The TL750M TL750M and TL751M TL751M series are low-dropout positive voltage regulators specifically designed for battery-powered systems. The TL750M TL750M and TL751M TL751M incorporate on-board overvoltage and current-limit protection circuitry to protect both themselves and the regulated system. Both series are fully protected against 60-V load-dump and reverse battery conditions. Extremely low quiescent current, even during full-load conditions, makes the TL750M TL750M and TL751M TL751M series ideal for standby power systems. The TL750M TL750M series of fixed-output voltage regulators offer 5-V, 8-V, 10-V, and 12-V options available in 3-lead KC (TO-220AB) and KTE plastic packages. The TL751M TL751M series of fixed-output voltage regulators also offer 5-V, 8-V, 10-V, and 12-V options with the addition of an enable input. The enable input gives the designer complete control over power up, allowing sequential power up or emergency shutdown. When taken high, the enable input places the regulator output in a highimpedance state. It is completely TTL- and CMOS-compatible. The TL751M TL751M series is offered in 5-lead KTG plastic packages. The TL750MxxC and TL751MxxC are characterized for operation from 0°C to 125°C virtual junction temperature, and the TL750MxxQ and TL751MxxQ series are characterized for operation from ­ 40°C to 125°C virtual junction temperature. The TL751M05M TL751M05M and TL751M12M TL751M12M are characterized for operation over the full military temperature range of ­ 55°C to 125°C. AVAILABLE OPTIONS PACKAGED DEVICES VO TYP (V) PLASTIC FLANGE MOUNT (KTE) PLASTIC FLANGE MOUNT (KTG) CHIP FORM (Y) - - TL750M05CKC TL750M05CKC TL750M05CKTE TL750M05CKTE TL751M05CKTG TL751M05CKTG TL750M05Y TL750M05Y 8 - - TL750M08CKC TL750M08CKC TL750M08CKTE TL750M08CKTE TL751M08CKTG TL751M08CKTG TL750M08Y TL750M08Y 10 - - TL750M10CKC TL750M10CKC TL750M10CKTE TL750M10CKTE TL751M10CKTG TL751M10CKTG TL750M10Y TL750M10Y - - TL750M12CKC TL750M12CKC TL750M12CKTE TL750M12CKTE TL751M12CKTG TL751M12CKTG TL750M12Y TL750M12Y - - TL750M05QKC TL750M05QKC TL750M05QKTE TL750M05QKTE TL751M05QKTG TL751M05QKTG - 8 - - TL750M08QKC TL750M08QKC TL750M08QKTE TL750M08QKTE TL751M08QKTG TL751M08QKTG - 10 - - TL750M10QKC TL750M10QKC TL750M10QKTE TL750M10QKTE TL751M10QKTG TL751M10QKTG - 12 ­ 55°C to 125°C HEAT-SINK MOUNTED (3-PIN) (KC) 5 ­ 40°C to 125°C CERAMIC DIP (JG) 12 0°C to 125°C CHIP CARRIER (FK) 5 TJ - - TL750M12QKC TL750M12QKC TL750M12QKTE TL750M12QKTE TL751M12QKTG TL751M12QKTG - 5 TL751M05MFK TL751M05MFK TL751M05MJG TL751M05MJG - - - - 12 TL751M12MFK TL751M12MFK TL751M12MJG TL751M12MJG - - - - The KTE and KTG packages are alos available taped and reeled. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 TL750M TL750M . . . 3-LEAD KC PACKAGE (TOP VIEW) TL750M TL750M . . . 3-LEAD KTE PACKAGE (TOP VIEW) OUTPUT COMMON INPUT OUTPUT COMMON INPUT NOTE A: The common terminal is in electrical contact with the mounting base. TO-200AB O C I O C I JG PACKAGE (TOP VIEW) COMMON NC ENABLE INPUT 1 7 3 6 4 NC NC NC OUTPUT NC 8 2 TL751M TL751M . . . 5-LEAD KTG PACKAGE (TOP VIEW) 5 OUTPUT COMMON INPUT ENABLE NOTE A: The common terminal is in electrical contact with the mounting base. FK PACKAGE (TOP VIEW) NC COMMON NC NC NC N 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 NC NC NC OUTPUT NC NC NC NC 4 NC INPUT NC NC NC ENABLE NC NC ­ No internal connection 2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 O C I E TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 TL751Mxx functional block diagram INPUT ACTUAL DEVICE COMPONENT COUNT Transistors ENABLE Enable 46 Diodes 14 Resistors Current Limiting 44 Capacitors 28 V _ + Bandgap OUT Overvoltage/ Thermal Shutdown 4 JFET 1 Tunnels (emitter R) 2 COMMON POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3 TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 TL750MxxY chip information This chip, when properly assembled, displays characteristics similar to the TL750MxxC. Thermal compression or ultrasonic bonding can be used on the doped aluminum bonding pads. The chip can be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS INPUT (3) (1) OUTPUT TL750Mx (2) COMMON 123 (2) (1) (3) 92 4 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 CHIP THICKNESS: 11 MILS TYPICAL BONDING PADS: 7 X 7 MILS MINIMUM TJmax = 150°C TOLERANCES ARE ± 10% ALL DIMENSIONS ARE IN MILS TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 absolute maximum ratings over virtual junction temperature range (unless otherwise noted) Continuous input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 V Transient input voltage (see Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V Continuous reverse input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­15 V Transient reverse input voltage: t = 100 ms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 50 V Continuous total power dissipation at (or below) TA = 25°C . . . . . . . . . . . . . . . See Dissipation Rating Tables Continuous total power dissipation at (or below) TC = 40°C: FK Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 W JG Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 W All Other Packages (see Note 1) . . See Dissipation Rating Tables Operating free-air, TA, case, TC, or virtual junction, TJ, temperature range . . . . . . . . . . . . . . . ­ 40°C to 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: For operation above TA = 25°C and TC = 40°C, refer to Figures 1 and 2. To avoid exceeding the design maximum virtual junction temperature, these ratings should not be exceeded. Due to variation in individual device electrical characteristics and thermal resistance, the built-in thermal overload protection may be activated at power levels slightly above or below the rated dissipation. DISSIPATION RATING TABLE - FREE-AIR TEMPERATURE PACKAGE TA 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 105°C POWER RATING TA = 125°C POWER RATING FK 1920 mW 15.4 mW/°C 1227 mW 688 mW 380 mW JG 1050 mW 8.4 mW/°C 672 mW 378 mW 210 mW KC 2000 mW 16.0 mW/°C 1280 mW 720 mW 400 mW KTE/KTG 1900 mW 15.2 mW/°C 1216 mW 684 mW 380 mW DISSIPATION RATING TABLE - CASE TEMPERATURE PACKAGE TC 90°C POWER RATING DERATING FACTOR ABOVE TC = 90°C TA = 125°C POWER RATING KC 15000 mW 250.0 mW/°C 6250 mW KTE/KTG 14300 mW 238.0 mW/°C 5970 mW POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 5 TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 CASE TEMPERATURE DISSIPATION DERATING CURVE FREE-AIR TEMPERATURE DISSIPATION DERATING CURVE 25 Maximum Continuous Dissipation ­ W 1600 1400 1200 1000 800 600 400 ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Maximum Continuous Dissipatation ­ mW 1800 Derating Factor = 16 mW/°C 200 RJA 62.5°C/W 0 25 50 75 100 125 TA ­ Free-Air Temperature ­ °C 150 20 15 10 5 ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ 2000 0 25 Derating Factor = 181.8 mW/°C Above 40°C RJC 5.5°C/W 50 150 75 100 125 TC ­ Case Temperature ­ °C Figure 1 Figure 2 recommended operating conditions over recommended virtual junction temperature range MIN TL75xM05 6 26 TL75xM08 9 26 TL75xM10 Input voltage range VI I l range, MAX 11 26 26 TL75xM12 13 High-level ENABLE input voltage, VIH TL751Mxx 2 15 Low-level ENABLE input voltage, VIL TL751Mxx 0 0.8 UNIT V V TL75xMxxC, TL75xMxxQ 750 mA TL751MxxM Output current range IO range, 480 mA TL75xMxxC 0 125 TL75xMxxQ ­ 40 125 TL75xMxxM Operating virtual j O i i l junction temperature range, TJ i ­ 55 125 °C electrical characteristics, VI = 14 V, IO = 300 mA,TJ = 25°C TL751Mxxx PARAMETER MIN 50 Response time, ENABLE to output 6 TYP POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MAX UNIT µs TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 electrical characteristics, VI = 14 V, IO = 300 mA, ENABLE at 0 V for TL751M05 TL751M05, TJ = 25°C (unless otherwise noted) (see Note 2) PARAMETER TEST CONDITIONS TL750M05C TL750M05C, TL751M05C TL751M05C TL750M05Q TL750M05Q, TL751M05Q TL751M05Q MIN Output voltage Input voltage regulation VI = 9 V to 16 V, VI = 6 V to 26 V, Ripple rejection Output voltage regulation 5 5.05 4.9 IO = 250 mA IO = 250 mA VI = 8 V to 18 V, f = 120 Hz IO = 5 mA to 750 mA Dropout voltage 10 50 25 12 50 55 20 f = 10 Hz to 100 kHz Bias current 5.1 IO = 500 mA IO = 750 mA Output noise voltage UNIT MAX 4.95 TJ = 25°C TJ = MIN to MAX TYP IO = 750 mA IO = 10 mA mV dB 50 0.5 0.6 mV V µV 500 60 V 75 5 mA Bias current (TL751M05C TL751M05C and TL751M05Q TL751M05Q only) ENABLE VIH 2 V 200 µA For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 2: Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor on the output with equivalent series resistance within the guidelines shown in Figure 3. electrical characteristics, VI = 14 V, IO = 300 mA, ENABLE at 0 V for TL751M08 TL751M08, TJ = 25°C (unless otherwise noted) (see Note 2) PARAMETER TEST CONDITIONS Output voltage VI = 10 V to 17 V, VI = 9 V to 26 V, Ripple rejection Output voltage regulation MIN TYP MAX 7.92 TJ = 25°C TJ = MIN to MAX Input voltage regulation TL750M08x, TL751M08x 8 8.08 7.84 IO = 250 mA IO = 250 mA VI = 11 V to 21 V, f = 120 Hz IO = 5 mA to 750 mA Dropout voltage f = 10 Hz to 100 kHz Bias current IO = 750 mA IO = 10 mA 12 50 40 15 68 55 24 IO = 500 mA IO = 750 mA Output noise voltage 8.16 V mV dB 80 0.5 0.6 mV V µV 500 60 UNIT 75 5 mA Bias current (TL751Mxx only) 200 µA ENABLE VIH 2 V For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 2: Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor on the output with equivalent series resistance within the guidelines shown in Figure 3. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 7 TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 electrical characteristics, VI = 14 V, IO = 300 mA, ENABLE at 0 V for TL751M10 TL751M10, TJ = 25°C (unless otherwise noted) (see Note 2) PARAMETER TEST CONDITIONS Output voltage VI = 12 V to 18 V, VI = 11 V to 26 V, Ripple rejection Output voltage regulation 10 10.1 IO = 250 mA IO = 250 mA 10.2 15 50 43 20 75 55 30 f = 10 Hz to 100 kHz Bias current MAX IO = 500 mA IO = 750 mA Output noise voltage TYP 9.8 VI = 13 V to 23 V, f = 120 Hz IO = 5 mA to 750 mA Dropout voltage MIN 9.9 TJ = 25°C TJ = MIN to MAX Input voltage regulation TL750M10x, TL751M10x IO = 750 mA IO = 10 mA V mV dB 100 0.5 0.6 mV V µV 1000 60 UNIT 75 5 mA Bias current (TL751Mxx only) 200 µA ENABLE VIH 2 V For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 2: Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor on the output with equivalent series resistance within the guidelines shown in Figure 3. electrical characteristics, VI = 14 V, IO = 300 mA, ENABLE at 0 V for TL751M12 TL751M12, TJ = 25°C (unless otherwise noted) (see Note 2) PARAMETER TEST CONDITIONS TL750M12C TL750M12C, TL751M12C TL751M12C TL750M12Q TL750M12Q, TL751M12Q TL751M12Q MIN Output voltage Input voltage regulation VI = 14 V to 19 V, VI = 13 V to 26 V, Ripple rejection Output voltage regulation IO = 250 mA IO = 250 mA f = 10 Hz to 100 kHz Bias current IO = 750 mA IO = 10 mA 12.24 15 50 43 20 78 55 30 IO = 500 mA IO = 750 mA Output noise voltage 12.12 11.76 VI = 13 V to 23 V, f = 120 Hz IO = 5 mA to 750 mA Dropout voltage 12 UNIT MAX 11.88 TJ = 25°C TJ = MIN to MAX TYP mV dB 120 0.5 0.6 mV V µV 1000 60 V 75 5 mA Bias current (TL751Mxx only) 200 µA ENABLE VIH 2 V For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 2: Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor on the output with equivalent series resistance within the guidelines shown in Figure 3. 8 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 electrical characteristics, VI = 14 V, IO = 300 mA, ENABLE at 0 V, TJ = 25°C (unless otherwise noted) (see Note 2) PARAMETER TL751M05M TL751M05M TEST CONDITIONS Output voltage VI = 6 V to 26 V V, IO = 0 mA to 480 mA Input voltage regulation VI = 9 V to 16 V, VI = 6 V to 26 V, TJ = 25°C TJ = ­ 55°C to 125°C f = 120 Hz TYP MAX 4.95 5 5.05 IO = 250 mA IO = 250 mA VI = 8 V to 18 V, IO = 5 mA to 480 mA MIN Ripple rejection Output voltage regulation Dropout voltage Output noise voltage 5.1 10 50* 25 12 50 55 IO = 480 mA IO = 10 mA V mV dB 20 IO = 480 mA f = 10 Hz to 100 kHz Bias Bi current 4.9 UNIT 50 0.5 mV V µV 500 60 75 5 mA ENABLE VIH 2 V 200 µA * This parameter is not production tested. NOTE 2: Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor on the output with equivalent series resistance within the guidelines shown in Figure 3. electrical characteristics, VI = 14 V, IO = 300 mA, ENABLE at 0 V, TJ = 25°C (unless otherwise noted) (see Note 2) PARAMETER TL751M12M TL751M12M TEST CONDITIONS Output voltage VI = 13 V to 26 V, V IO = 0 mA to 480 mA Input voltage regulation VI = 14 V to 19 V, VI = 13 V to 26 V, TJ = 25°C TJ = ­ 55°C to 125°C f = 120 Hz TYP MAX 11.88 12 12.12 IO = 250 mA IO = 250 mA VI = 13 V to 23 V, IO = 5 mA to 480 mA MIN Ripple rejection Output voltage regulation Dropout voltage Output noise voltage 12.24 15 43 20 50* 78 55 30 IO = 480 mA f = 10 Hz to 100 kHz Bias Bi current 11.76 IO = 480 mA IO = 10 mA V mV dB 120 0.5 mV V µV 1000 60 UNIT 75 5 mA ENABLE VIH 2 V 200 µA For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 2: Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor on the output with equivalent series resistance within the guidelines shown in Figure 3. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 9 TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 electrical characteristics, VI = 14 V, IO = 300 mA, ENABLE at 0 V, TJ = 25°C (unless otherwise noted) (see Note 2) PARAMETER TEST CONDITIONS TL750M05Y TL750M05Y MIN Output voltage TYP MAX 5 UNIT V VI = 9 V to 16 V, VI = 6 V to 26 V, IO = 250 mA IO = 250 mA 10 VI = 8 V to 18 V, IO = 5 mA to 750 mA f = 120 Hz 55 dB Output voltage regulation 20 mV Output noise voltage f = 10 Hz to 100 kHz 500 µV Input voltage regulation Ripple rejection mV 12 Bias current IO = 750 mA 60 mA NOTE 2: Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor on the output with equivalent series resistance within the guidelines shown in Figure 3. electrical characteristics, VI = 14 V, IO = 300 mA, ENABLE at 0 V, TJ = 25°C (unless otherwise noted) (see Note 2) PARAMETER TEST CONDITIONS TL750M08Y TL750M08Y MIN Output voltage TYP MAX 8 UNIT V VI = 10 V to 17 V, VI = 9 V to 26 V, IO = 250 mA IO = 250 mA 12 VI = 11 V to 21 V, IO = 5 mA to 750 mA f = 120 Hz 55 dB Output voltage regulation 24 mV Output noise voltage f = 10 Hz to 100 kHz 500 µV Input voltage regulation Ripple rejection mV 15 Bias current IO = 750 mA 60 mA NOTE 2: Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor on the output with equivalent series resistance within the guidelines shown in Figure 3. electrical characteristics, VI = 14 V, IO = 300 mA, ENABLE at 0 V, TJ = 25°C (unless otherwise noted) (see Note 2) PARAMETER TEST CONDITIONS Output voltage TL750M10Y TL750M10Y MIN TYP 10 MAX UNIT V VI = 12 V to 18 V, VI = 11 V to 26 V, IO = 250 mA IO = 250 mA 15 VI = 13 V to 23 V, IO = 5 mA to 750 mA f = 120 Hz 55 dB Output voltage regulation 30 mV Output noise voltage f = 10 Hz to 100 kHz 1000 µV Input voltage regulation Ripple rejection 20 mV Bias current IO = 750 mA 60 mA NOTE 2: Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor on the output with equivalent series resistance within the guidelines shown in Figure 3. 10 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 TL751M12Y TL751M12Y electrical characteristics, VI = 14 V, IO = 300 mA, ENABLE at 0 V, TJ = 25°C (unless otherwise noted) (see Note 2) PARAMETER TEST CONDITIONS Output voltage TL750M12Y TL750M12Y MIN TYP 12 MAX UNIT V VI = 14 V to 19 V, VI = 13 V to 26 V, IO = 250 mA IO = 250 mA 15 f = 120 Hz 55 dB Output voltage regulation VI = 13 V to 23 V, IO = 5 mA to 750 mA 30 mV Output noise voltage f = 10 Hz to 100 kHz 1000 µV Input voltage regulation Ripple rejection 20 mV Bias current IO = 750 mA 60 mA NOTE 2: Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor on the output with equivalent series resistance within the guidelines shown in Figure 3. PARAMETER MEASUREMENT INFORMATION The TL751Mxx is a low-dropout regulator. This means that the capacitance loading is important to the performance of the regulator because it is a vital part of the control loop. The capacitor value and the equivalent series resistance (ESR) both affect the control loop and must be defined for the load range and the temperature range. Figures 3 and 4 can establish the capacitance value and ESR range for the best regulator performance. Figure 3 shows the recommended range of ESR for a given load with a 10-µF capacitor on the output. This figure also shows a maximum ESR limit of 2 and a load-dependent minimum ESR limit. For applications with varying loads, the lightest load condition should be chosen since it is the worst case. Figure 4 shows the relationship of the reciprocal of ESR to the square root of the capacitance with a minimum capacitance limit of 10 µF and a maximum ESR limit of 2 . This figure establishes the amount that the minimum ESR limit shown in Figure 3 can be adjusted for different capacitor values. For example, where the minimum load needed is 200 mA, Figure 4 suggests an ESR range of 0.8 to 2 for 10 µF. Figure 4 shows that changing the capacitor from 10 µF to 400 µF can change the ESR minimum by greater than 3/0.5 (or 6). Therefore, the new minimum ESR value is 0.8/6 (or 0.13 ). This now allows an ESR range of 0.13 to 2 , achieving an expanded ESR range by using a larger capacitor at the output. For better stability in low-current applications, a small resistance placed in series with the capacitor (see Table 1) is recommended, so that ESRs better approximate those shown in Figures 3 and 4. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 11 TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 PARAMETER MEASUREMENT INFORMATION Table 1. Compensation for Increased Stability at Low Currents MANUFACTURER CAPACITANCE ESR TYP AVX 15 µF 0.9 TAJB156M010S TAJB156M010S KEMET 33 µF 0.6 ADDITIONAL RESISTANCE PART NUMBER T491D336M010AS T491D336M010AS 1 0.5 IL Applied Load Current Load Voltage VL = IL x ESR VL OUTPUT CAPACITOR STABILITY vs EQUIVALENT SERIES RESISTANCE (ESR) EQUIVALENT SERIES RESISTANCE (ESR) vs LOAD CURRENT RANGE 3 0.04 2.4 Not Recommended Recommended Min ESR Potential Instability 0.035 1000 µF 0.03 Max ESR Boundary 1.8 1.6 Region of Best Stability 1.4 1.2 Stability ­ 2 CL 2.2 ÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÎÎÎÎÎÎÎÎÎ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÎÎÎÎÎÎÎÎÎÎÎÎ Î ÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÎÎÎÎ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÎÎÎÎÎÎÎÎ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑ Equivalent Series Resistance (ESR) ­ 2.6 This Region Not Recommended for Operation Region of Best Stability 0.025 400 µF 0.02 200 µF 0.015 1 0.8 Min ESR Boundary 0.6 0.4 Potential Instability Region 0.2 0 0 0.1 0.2 0.3 0.4 IL ­ Load Current Range ­ A ÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎ ÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏ Ï ÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎ Î ÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎ Î ÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏ ÎÏÏÏÏÏÏÏÏÏÏ ÎÎ Ï ÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎ ÏÏÏ Ï CL = 10 µF CI = 0.1 µF f = 120 Hz 2.8 0.5 100 µF 0.01 0.005 0 0 22 µF 10 µF 0.5 1.5 2 2.5 1/ESR Figure 3 12 1 Figure 4 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3 3.5 4 4.5 5 TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 TYPICAL CHARACTERISTICS Table of Graphs FIGURE Transient input voltage vs Time vs Input voltage Output voltage IO = 10 mA IO = 100 mA Input current 5 6 vs Input voltage 7 vs Input voltage 8 Dropout voltage vs Output current 9 Quiescent current vs Output current 10 Load transient response 11 Line transient response 12 TRANSIENT INPUT VOLTAGE vs TIME OUTPUT VOLTAGE vs INPUT VOLTAGE 14 TJ = 25°C VI = 14 V + 46e( ­ t/0.230) for t 5 ms 50 IO = 10 mA TJ = 25°C 12 VO ­ Output Voltage ­ V V i ­ Transient Input Voltage ­ V 60 40 30 tr = 1 ms 20 10 TL75xM12 10 TL75xM10 8 TL75xM08 6 TL75xM05 4 2 0 0 100 200 300 400 500 600 0 0 2 t ­ Time ­ ms 4 6 8 10 12 14 VI ­ Input Voltage ­ V Figure 5 Figure 6 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 13 TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 TYPICAL CHARACTERISTICS INPUT CURRENT vs INPUT VOLTAGE INPUT CURRENT vs INPUT VOLTAGE 200 350 IO = 10 mA TJ = 25°C 180 IO = 100 mA TJ = 25°C 300 TL75_M12 40 TL75_M10 60 TL75_M08 150 TL75_M12 80 200 TL75_M10 100 TL75_M08 120 250 TL75_M05 I I ­ Input Current ­ mA 140 TL75_M05 I I ­ Input Current ­ mA 160 100 50 20 0 0 0 2 4 6 8 10 12 14 0 2 VI ­ Input Voltage ­ V 4 6 8 10 VI ­ Input Voltage ­ V Figure 7 12 14 Figure 8 DROPOUT VOLTAGE vs OUTPUT CURRENT QUIESCENT CURRENT vs OUTPUT CURRENT 12 250 TJ = 25°C VI = 14 V TJ = 25°C 225 I Q ­ Quiescent Current ­ mA Dropout Voltage ­ mV 10 200 175 150 125 100 8 6 4 2 75 50 0 0 50 100 150 200 IO ­ Output Current ­ mA 250 300 0 20 Figure 9 14 40 60 80 100 150 IO ­ Output Current ­ mA Figure 10 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 250 350 TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 100 0 ­ 100 ­ 200 150 VI(NOM) = VO + 1 V ESR = 2 CL = 10 µF TJ = 25°C 100 50 0 0 50 100 150 200 t ­ Time ­ µs LINE TRANSIENT RESPONSE VO ­ Output Voltage ­ mV 20 mV/DIV LOAD TRANSIENT RESPONSE 200 VI(NOM) = VO + 1 V ESR = 2 IL = 20 mA CL = 10 µF TJ = 25°C VIN ­ Input Voltage ­ V 1 V/DIV I O ­ Output Current ­ mA VO ­ Output Voltage ­ mV TYPICAL CHARACTERISTICS 250 300 350 0 20 Figure 11 40 60 80 100 t ­ Time ­ µs 150 250 350 Figure 12 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 15 TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 MECHANICAL INFORMATION FK (S-CQCC-N*) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS * 12 B A 11 20 MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 19 MIN 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 10 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.740 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 25 5 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / C 11/95 NOTES: A. B. C. D. E. 16 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 MS-004 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 MECHANICAL INFORMATION JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE PACKAGE 0.400 (10,20) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.063 (1,60) 0.015 (0,38) 0°­15° 0.023 (0,58) 0.015 (0,38) 0.015 (0,38) 0.008 (0,20) 0.100 (2,54) 4040107 / B 04/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only Falls within MIL-STD-1835 MIL-STD-1835 GDIP1-T8 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 17 TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 MECHANICAL INFORMATION KC (R-PSFM-T3) PLASTIC FLANGE-MOUNT PACKAGE 0.120 (3,05) 0.100 (2,54) 0.420 (10,67) 0.380 (9,65) 0.156 (3,96) DIA 0.146 (3,71) 0.185 (4,70) 0.175 (4,46) (see Note H) 0.052 (1,32) 0.048 (1,22) 0.270 (6,86) 0.230 (5,84) (see Note H) 0.625 (15,88) 0.560 (14,22) 0.125 (3,18) (see Note C) (see Note F) 0.250 (6,35) MAX 0.562 (14,27) 0.500 (12,70) 1 0.035 (0,89) 0.029 (0,74) 0.010 (0,25) M 3 0.070 (1,78) 0.045 (1,14) 0.122 (3,10) 0.102 (2,59) 0.025 (0,64) 0.012 (0,30) 0.100 (2,54) 0.200 (5,08) 4040207 / B 01/95 NOTES: A. B. C. D. E. F. G. H. 18 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Lead dimensions are not controlled within this area. All lead dimensions apply before solder dip. The center lead is in electrical contact with the mounting tab. The chamfer is optional. Falls within JEDEC TO-220AB Tab contour optional within these dimensions POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 MECHANICAL INFORMATION KTE (R-PSFM-T3) PLASTIC FLANGE-MOUNT PACKAGE 0.080 (2,03) 0.070 (1,78) 0.366 (9,31) 0.050 (1,27) 0.040 (1,02) 0.356 (9,05) 0.220 (5,59) NOM 0.010 (0,25) NOM 0.360 (9,14) 0.350 (8,89) 0.295 (7,49) NOM 0.320 (8,13) 0.310 (7,87) 0.420 (10,67) 0.410 (10,41) 1 3 0.025 (0,63) 0.031 (0,79) 0.100 (2,54) Thermal Tab (see Note C) Seating Plane 0.004 (0,10) 0.010 (0,25) M 0.005 (0,13) 0.001 (0,03) 0.200 (5,08) 0.041 (1,04) 0.031 (0,79) 0.010 (0,25) NOM Gage Plane 3°­ 6° 0.010 (0,25) 4073375/B 4073375/B 01/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. The center lead is in electrical contact with the thermal tab. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 19 TL750M TL750M, TL751M TL751M LOW-DROPOUT VOLTAGE REGULATORS SLVS021E SLVS021E ­ JANUARY 1988 ­ REVISED OCTOBER 1996 MECHANICAL INFORMATION KTG (R-PSFM-G5) PLASTIC FLANGE-MOUNT PACKAGE 0.080 (2,03) 0.070 (1,78) 0.050 (1,27) 0.366 (9,31) 0.356 (9,05) 0.040 (1,02) 0.220 (5,59) NOM 0.010 (0,25) NOM Thermal Tab (see Note C) 0.360 (9,14) 0.350 (8,89) 0.295 (7,49) NOM 0.320 (8,13) 0.310 (7,87) 0.420 (10,67) 0.410 (10,41) 1 0.067 (1,72) 5 Seating Plane 0.031 (0,79) 0.004 (0,10) 0.025 (0,63) 0.268 (6,81) 0.010 (0,25) M 0.005 (0,13) 0.001 (0,03) 0.041 (1,04) 0.010(0,25) NOM 0.031 (0,79) Gage Plane 3°­ 6° 0.010(0,25) 4073377/B 4073377/B 01/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. The center lead is in electrical contact with the thermal tab. 20 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. 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