NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
THS4061 THS4062 SLOS234E THS4061/2 MILPRF38535 THS4011/2 THS4031/2 THS4061CD - Datasheet Archive
180MHz HIGHSPEED AMPLIFIERS SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 7 3 6 4 5 1OUT 1IN - 1IN + -VCC 8 2 7 3 6 4 5 VCC+
THS4061 THS4061, THS4062 THS4062 180MHz HIGHSPEED AMPLIFIERS SLOS234E SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 7 3 6 4 5 1OUT 1IN - 1IN + -VCC 8 2 7 3 6 4 5 VCC+ 2OUT 2IN- 2IN+ Cross-Section View Showing PowerPAD Option (DGN) THS4061 THS4061 FK PACKAGE (TOP VIEW) 2 1 20 19 NC 3 description NC 4 18 NC IN- 5 17 VCC+ NC 6 16 NC IN+ 7 15 OUT NC 8 14 NC VI 10 11 12 13 + NC 9 NC The THS4061 THS4061 and THS4062 THS4062 are generalpurpose, single/dual, high-speed voltage feedback amplifiers ideal for a wide range of applications including video, communication, and imaging. The devices offer very good ac performance with 180-MHz bandwidth, 400-V/µs slew rate, and 40-ns settling time (0.1% ). The THS4061/2 THS4061/2 are stable at all gains for both inverting and noninverting configurations. These amplifiers have a high output drive capability of 115 mA and draw only 7.8 mA supply current per channel. Excellent professional video results can be obtained with the low differential gain/phase errors of 0.02%/0.02° and wide 0.1 db flatness to 75 MHz. For applications requiring low distortion, the THS4061/2 THS4061/2 is ideally suited with total harmonic distortion of -72 dBc at f = 1 MHz. 1 NC - No internal connection NULL D 2 NULL VCC+ OUT NC NC D 8 NC D 1 VCC- NC D NULL IN - IN + VCC- THS4062 THS4062 D AND DGN PACKAGE (TOP VIEW) NC D D - 180 MHz Bandwidth (G = 1, -3 dB) - 400 V/µs Slew Rate - 40-ns Settling Time (0.1%) High Output Drive, IO = 115 mA (typ) Excellent Video Performance - 75 MHz 0.1 dB Bandwidth (G = 1) - 0.02% Differential Gain - 0.02° Differential Phase Very Low Distortion - THD = -72 dBc at f = 1 MHz Wide Range of Power Supplies - VCC = ±5 V to ±15 V Available in Standard SOIC, MSOP PowerPAD, JG, or FK Package Evaluation Module Available THS4061 THS4061 JG, D AND DGN PACKAGE (TOP VIEW) NULL D High Speed 75 THS4061 THS4061 VO 75 _ 2 k 75 2 k LINE DRIVER (G = 2) CAUTION: The THS4061 THS4061 and THS4062 THS4062 provide ESD protection circuitry. However, permanent damage can still occur if this device is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance degradation or loss of functionality Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments Incorporated. Copyright 1998 - 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MILPRF38535 MILPRF38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 THS4061 THS4061, THS4062 THS4062 180MHz HIGHSPEED AMPLIFIERS SLOS234E SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 RELATED DEVICES DEVICE DESCRIPTION THS4011/2 THS4011/2 THS4031/2 THS4031/2 THS4061/2 THS4061/2 290-MHz Low Distortion High-Speed Amplifiers 100-MHz Low Noise High Speed-Amplifiers 180-MHz High-Speed Amplifiers AVAILABLE OPTIONS PACKAGED DEVICES NUMBER OF CHANNELS PLASTIC SMALL OUTLINE (D) PLASTIC MSOP (DGN) CERAMIC DIP (JG) CHIP CARRIER (FK) 0°C to 0C 70°C 1 THS4061CD THS4061CD THS4061CDGN THS4061CDGN - 2 THS4062CD THS4062CD THS4062CDGN THS4062CDGN - -40 C -40°C to 85°C 1 THS4061ID THS4061ID THS4061IDGN THS4061IDGN 2 THS4062ID THS4062ID 1 - TA -55°C to 125°C MSOP SYMBOL EVALUATION MODULES - TIABS THS4061EVM THS4061EVM - TIABM THS4062EVM THS4062EVM - - TIABT - THS4062IDGN THS4062IDGN - - TIABN - - THS4061MJG THS4061MJG THS4061MFK THS4061MFK - - The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4061CDGNR THS4061CDGNR). functional block diagram Null 2 IN- 3 IN+ 1 8 - 6 OUT + Figure 1. THS4061 THS4061 - Single Channel VCC 1IN- 2 8 - 1 1IN+ 2IN- 3 6 - 7 2IN+ 5 1OUT + 2OUT + 4 -VCC Figure 2. THS4062 THS4062 - Dual Channel 2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 THS4061 THS4061, THS4062 THS4062 180MHz HIGHSPEED AMPLIFIERS SLOS234E SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage, VCC+ to VCC- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VCC Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA Differential input voltage, VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±4 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Operating free-air temperature, TA: C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C M-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 125°C Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds, D and DGN package . . . . . . . . . . . . 300°C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds, JG package . . . . . . . . . . . . . . . . . . . . 300°C Case temperature for 60 seconds, FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE TA 25°C 25 C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C 70 C POWER RATING TA = 85°C 85 C POWER RATING TA = 125°C 125 C POWER RATING D 475 mW 385 mW - 740 mW 6 mW/°C DGN 2.14 W 17.1 mW/°C 1.37 W 1.11 W - JG 1057 mW 8.4 mW/°C 627 mW 546 mW 210 mW FK 1375 mW 11 mW/°C 880 mW 715 mW 275 mW The DGN package incorporates a PowerPAD on the underside of the device. This acts as a heatsink and must be connected to a thermal dissipation plane for proper power dissipation. Failure to do so can result in exceeding the maximum specified junction temperature, which could permanently damage the device. recommended operating conditions MIN Supply voltage, VCC+ and VCC- MAX ±16 9 Single supply C-suffix Operating free-air temperature, TA NOM ±4.5 Dual supply 32 0 -40 85 M-suffix -55 V 70 I-suffix UNIT 125 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 °C C 3 THS4061 THS4061, THS4062 THS4062 180MHz HIGHSPEED AMPLIFIERS SLOS234E SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 (unless otherwise noted) dynamic performance THS4061C/I THS4061C/I, THS4062C/I THS4062C/I TEST CONDITIONS PARAMETER MIN Dynamic performance small-signal bandwidth (-3 dB) BW Bandwidth for 0.1 dB flatness SR Slew rate Settling time to 0.1% ts Settling time to 0.01% VCC = ±5 V VCC = ±15 V Gain = 1 TYP UNIT MAX 180 MHz 50 Gain = -1 VCC = ±5 V VCC = ±15 V MHz 50 75 Gain = 1 VCC = ±5 V VCC = ±15 V MHz 20 400 Gain = -1 VCC = ±5 V VCC = ±15 V, 5-V step (0 V to 5 V) VCC = ±5 V, VCC = ±15 V, VO = -2.5 V to 2.5 V, 5-V step (0 V to 5 V) VCC = ±5 V, VO = -2.5 V to 2.5 V, Full range = 0°C to 70°C for C suffix and - 40°C to 85°C for I suffix V/µs V/ s 350 40 Gain = -1 ns 40 140 Gain = -1 ns 150 noise/distortion performance THS4061C/I THS4061C/I, THS4062C/I THS4062C/I TEST CONDITIONS PARAMETER MIN THD Total harmonic distortion f = 1 MHz Vn In Input voltage noise f = 10 kHz, Input current noise f = 10 kHz, TYP -72 dBc 14.5 nV/Hz 1.6 VCC = ±5 V or ±15 V VCC = ±5 V or ±15 V pA/Hz VCC = ±15 V Gain = 2, 0.02 % VCC = ±5 V Differential gain error UNIT MAX 0.02 % VCC = ±15 V VCC = ±5 V 0.02° NTSC, 40 IRE modulation Differential phase error Gain = 2, NTSC, 40 IRE modulation Channel-to-channel crosstalk (THS4062 THS4062 only) VCC = ±5 V or ±15 V, 0.06° f = 1 MHz 65 dB Full range = 0°C to 70°C for C suffix and - 40°C to 85°C for I suffix dc performance THS4061C/I THS4061C/I, THS4062C/I THS4062C/I TEST CONDITIONS PARAMETER MIN TYP 15 VCC = ±15 V, VO = ±10 V, TA = 25°C TA = full range 5 RL = 1 k VCC = ±5 V, VO = ±2.5 V, RL = 1 k TA = 25°C TA = full range 2.5 Open loop gain Input offset voltage VOS IIB IOS Offset drift Input bias current Input offset current VCC = ±5 V or ±15 V VCC = ±5 V or ±15 V TA = full range VCC = ±5 V or ±15 V VCC = ±5 V or ±15 V TA = full range TA = full range TA = full range Full range = 0°C to 70°C for C suffix and - 40°C to 85°C for I suffix 4 POST OFFICE BOX 655303 V/mV 4 8 V/mV 2 2.5 Offset current drift 8 mV µV/°C 15 3 6 75 250 0.3 · DALLAS, TEXAS 75265 UNIT MAX µA nA nA/°C THS4061 THS4061, THS4062 THS4062 180MHz HIGHSPEED AMPLIFIERS SLOS234E SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 (unless otherwise noted) (continued) input characteristics THS4061C/I THS4061C/I, THS4062C/I THS4062C/I TEST CONDITIONS PARAMETER MIN VICR Common-mode input voltage range CMRR Common mode rejection ratio ± 4.3 70 110 70 95 Input resistance VICR = ±12 V VICR = ±2.5 V TA = full range UNIT ±14.1 ± 3.8 VCC = ±15 V, VCC = ±5 V, RI ±13.8 VCC = ±15 V VCC = ±5 V TYP MAX V dB 1 2 Ci Input capacitance Full range = 0°C to 70°C for C suffix and - 40°C to 85°C for I suffix M pF output characteristics THS4061C/I THS4061C/I, THS4062C/I THS4062C/I TEST CONDITIONS PARAMETER MIN VO IO Output voltage swing Output current RL = 250 ±3.5 ±13 ±13.5 ±3.5 ±3.7 80 115 50 75 RL = 20 VCC = ±5 V VCC = ±15 V UNIT ±12.5 ±3.2 RL = 1 k VCC = ±15 V VCC = ±5 V VCC = ±15 V ±11.5 RL = 150 VCC = ±15 V VCC = ±5 V TYP ISC Short-circuit current RO Output resistance Open loop Full range = 0°C to 70°C for C suffix and - 40°C to 85°C for I suffix MAX V V mA 150 mA 12 power supply THS4061C/I THS4061C/I, THS4062C/I THS4062C/I TEST CONDITIONS PARAMETER MIN TYP UNIT MAX ±4.5 Supply voltage operating range ICC Quiescent current (per amplifier) VCC = ±15 V VCC = ±5 V Power supply rejection ratio VCC = ±5 V or ±15 V TA = 25°C TA = full range 33 TA = full range PSRR ±16.5 9 Dual supply VCC Single supply 7.8 70 68 10.5 7.3 10 V mA 78 dB Full range = 0°C to 70°C for C suffix and - 40°C to 85°C for I suffix POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 5 THS4061 THS4061, THS4062 THS4062 180MHz HIGHSPEED AMPLIFIERS SLOS234E SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 (unless otherwise noted) dynamic performance Unity-gain bandwidth BW SR Closed loop, Slew rate Settling time to 0.1% ts Settling time to 0.01% RL = 1 k MIN VCC = ±15 V VCC = ±15 V VCC = ±5 V VCC = ±15 V VCC = ±5 V TYP *140 180 Gain = 1 Gain = -1 VCC = ±15 V VCC = ±5 V Dynamic performance small-signal bandwidth (-3 dB) Bandwidth for 0.1 dB flatness THS4061M THS4061M TEST CONDITIONS PARAMETER Gain = 1 MAX UNIT MHz 180 MHz 180 50 MHz 50 75 VCC = ±15 V VCC = ±15 V, RL = 1 k VCC = ±5 V, VCC = ±15 V, VO = -2.5 V to 2.5 V, 5-V step (0 V to 5 V) VCC = ±5 V, VO = -2.5 V to 2.5 V, MHz 20 *400 5-V step (0 V to 5 V) 500 V/µs 40 Gain = -1 ns 40 140 Gain = -1 ns 150 Full range = -55°C to 125°C for M suffix *This parameter is not tested. noise/distortion performance THS4061M THS4061M TEST CONDITIONS PARAMETER MIN TYP THD Total harmonic distortion f = 1 MHz Vn In Input voltage noise f = 10 kHz, Input current noise f = 10 kHz, VCC = ±5 V or ±15 V VCC = ±5 V or ±15 V Gain = 2, NTSC, 40 IRE Modulation VCC = ±15 V VCC = ±5 V Differential phase error Gain = 2, NTSC, 40 IRE Modulation VCC = ±15 V VCC = ±5 V UNIT 0.02 Differential gain error MAX -72 dBc 14.5 nV/Hz 1.6 pA/Hz 0.02° % 0.02 0.06° Full range = -55°C to 125°C for M suffix dc performance Open loop gain IIB IIO VCC = ±15 V, VCC = ±5 V, Input offset voltage VCC = ±5 V or ±15 V RL = 1 k Offset drift VIO VCC = ±5 V or ±15 V VCC = ±5 V or ±15 V RL = 1 k VCC = ±5 V or ±15 V VCC = ±5 V or ±15 V RL = 1 k Input bias current Input offset current Offset current drift Full range = -55°C to 125°C for M suffix 6 THS4061M THS4061M TEST CONDITIONS PARAMETER VO = ±10 V, RL = 1 k VO = ±2.5 V, RL = 1 k POST OFFICE BOX 655303 RL = 1 k RL = 1 k · DALLAS, TEXAS 75265 MIN 5 TA = full range TYP 6 UNIT 9 2.5 MAX V/mV TA = 25°C TA = full range 2.5 mV 9 TA = full range TA = full range 15 3 6 µA TA = full range TA = full range 75 250 nA 0.3 8 mV µV/°C nA/°C THS4061 THS4061, THS4062 THS4062 180MHz HIGHSPEED AMPLIFIERS SLOS234E SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 electrical characteristics at TA = full range, VCC = ±15 V, RL = 1 k (unless otherwise noted) (continued) input characteristics THS4061M THS4061M TEST CONDITIONS PARAMETER VICR Common-mode input voltage range Common mode rejection ratio RI ±14.1 ± 3.8 VCC = ±15 V, VCC = ±5 V, TYP ±13.8 ± 4.3 70 90 Input resistance VICR = ±12 V VICR = ±2.5 V MAX UNIT 86 80 VCC = ±15 V VCC = ±5 V CMRR MIN V dB 1 2 Ci Input capacitance Full range = -55°C to 125°C for M suffix M pF output characteristics VO IO Output voltage swing Output current ISC Short-circuit current RO Output resistance Full range = -55°C to 125°C for M suffix THS4061M THS4061M TEST CONDITIONS PARAMETER TYP RL = 250 ±12 ±13.1 RL = 150 VCC = ±15 V VCC = ±5 V MIN ±3.2 ±3.5 ±13 ±13.5 ±3.5 ±3.7 70 75 RL = 1 k VCC = ±15 V VCC = ±5 V RL = 20 VCC = ±15 V Open loop UNIT 115 50 VCC = ±15 V VCC = ±5 V TA = 25°C MAX V V mA 150 mA 12 power supply THS4061M THS4061M TEST CONDITIONS PARAMETER MIN ICC PSRR Supply voltage operating range Quiescent current Power supply rejection ratio MAX ±4.5 Single supply VCC = ±15 V VCC = ±5 V TA = full range VCC = ±5 V or ±15 V TA = 25°C TA = full range 33 TA = 25°C VCC = ±15 V VCC = ±5 V ±16.5 9 Dual supply VCC TYP 7.8 V 9 7.3 UNIT 8.5 11 mA 10.5 76 80 74 78 dB Full range = -55°C to 125°C for M suffix POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 7 THS4061 THS4061, THS4062 THS4062 180MHz HIGHSPEED AMPLIFIERS SLOS234E SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS FIGURE IIB VIO Input bias current vs Free-air temperature 3 Input offset voltage vs Free-air temperature 4 Open-loop gain vs Frequency 5 Phase vs Frequency 5 Differential gain vs Number of loads Differential phase vs Number of loads Closed-loop gain vs Frequency 10, 11 6, 8 7, 9 Output amplitude 12, 13 Common-mode rejection ratio vs Frequency 14 vs Frequency 15 PSRR Power supply rejection ratio vs Free-air temperature 16 VO(PP) ICC Output voltage swing vs Supply voltage 17 Supply current vs Free-air temperature 18 Env THD Noise spectral density vs Frequency 19 Total harmonic distortion vs Frequency 20, 21 Crosstalk 8 vs Frequency CMRR vs Frequency 22, 23 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 THS4061 THS4061, THS4062 THS4062 180MHz HIGHSPEED AMPLIFIERS SLOS234E SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE INPUT OFFSET VOLTAGE vs FREE-AIR TEMPERATURE 4 0 VIO - Input Offset Voltage - mV -0.5 3.5 3 2.5 VCC = ±5 V -1 -1.5 VCC = ±15 V -2 -2.5 -3 -20 0 20 40 60 80 -3.5 -40 100 -20 TA - Free-Air Temperature - °C 0 20 40 60 80 100 TA - Free-Air Temperature - °C Figure 3 Figure 4 OPEN-LOOP GAIN AND PHASE vs FREQUENCY 90 VCC = ±15 V 80 0° VCC = ±5 V 70 60 -45° Phase 50 40 -90° Phase 2 -40 Open-Loop Gain - dB I IB - Input Bias Current - µ A VCC = ±15 V, ±5 V 30 -135° 20 10 0 1k 10k 100k 1M 10M 100M -180° 1G f - Frequency - Hz Figure 5 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 9 THS4061 THS4061, THS4062 THS4062 180MHz HIGHSPEED AMPLIFIERS SLOS234E SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS DIFFERENTIAL GAIN vs NUMBER OF LOADS DIFFERENTIAL PHASE vs NUMBER OF LOADS 0.14% 0.7° Gain = 2 RF = 680 40 IRE - NTSC Worst Case ±100 IRE Ramp 0.12% 0.6 Differential Phase Differential Gain 0.1% 0.08% VCC = ±15 Gain 0.06% VCC = ±5 Gain 0.04% 0.5° VCC = ± 5 Phase 0.4° VCC = ± 15 Phase 0.3° 0.2° 0.02% 0% Gain = 2 RF = 680 40 IRE - NTSC Worst Case ±100 IRE Ramp 0.1° 2 1 3 0° 4 1 2 Number of 150 Loads Figure 6 DIFFERENTIAL PHASE vs NUMBER OF LOADS 0.2% 1° Gain = 2 RF = 680 40 IRE - PAL Worst Case ±100 IRE Ramp 0.18% 0.16% 0.14% 0.8° VCC = ±15 Gain 0.12% 0.1% VCC = ±5 Gain 0.08% Gain = 2 RF = 680 40 IRE - PAL Worst Case ±100 IRE Ramp 0.9° Differential Phase Differential Gain 4 Figure 7 DIFFERENTIAL GAIN vs NUMBER OF LOADS 0.7° 0.6° 0.5° 0.4° 0.06% 0.2° 0.02% VCC = ±5 Phase VCC = ±15 Phase 0.3° 0.04% 0.1° 0% 1 2 3 4 0° 1 Number of 150 Loads 2 Figure 9 POST OFFICE BOX 655303 3 Number of 150 Loads Figure 8 10 3 Number of 150 Loads · DALLAS, TEXAS 75265 4 THS4061 THS4061, THS4062 THS4062 180MHz HIGHSPEED AMPLIFIERS SLOS234E SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS CLOSED-LOOP GAIN vs FREQUENCY 2 CLOSED-LOOP GAIN vs FREQUENCY 5 VCC = ±15 V 0 -2 VCC = ±5 V Closed-Loop Gain - dB Closed-Loop Gain - dB 0 -4 -6 -8 -5 -10 -10 -12 -15 Gain = 1 RF = 270 RL = 150 -14 100k 1M 10M 100M VCC = ±15 V, ±5 V Gain = -1 RF = 510 RL = 150 -20 100k 1G 1M 10M f - Frequency - Hz Figure 10 OUTPUT AMPLITUDE vs FREQUENCY 4 RF = 510 RF = 1 k 0 Output Amplitude - dB Output Amplitude - dB 2 0 RF = 270 RF = 200 -2 -4 -6 -8 100k 1G Figure 11 OUTPUT AMPLITUDE vs FREQUENCY 2 100M f - Frequency - Hz RF = 3 k -2 -4 -6 -8 Gain = 1 RL = 150 1M 10M 100M 1G -10 100k Gain = -1 RL = 150 f - Frequency - Hz 1M 10M 100M 1G f - Frequency - Hz Figure 12 Figure 13 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 11 THS4061 THS4061, THS4062 THS4062 180MHz HIGHSPEED AMPLIFIERS SLOS234E SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS COMMON-MODE REJECTION RATIO vs FREQUENCY POWER SUPPLY REJECTION RATIO vs FREQUENCY -80 VCC = ±15 V, ±5 V PSRR - Power Supply Rejection Ratio - dB CMRR - Common-Mode Rejection Ratio - dB 120 100 80 60 40 20 0 10k 100k 1M 10M -70 -60 -50 -40 -30 -20 -10 VCC = ±15 V, ±5 V 0 1k 100M 10k f - Frequency - Hz Figure 14 10M 100M OUTPUT VOLTAGE SWING vs SUPPLY VOLTAGE 90 30 88 VO(PP) - Output Voltage Swing - V PSRR - Power Supply Rejection Ratio - dB 1M Figure 15 POWER SUPPLY REJECTION RATIO vs FREE-AIR TEMPERATURE 86 VCC = -15 V 84 82 80 VCC = 15 V 78 76 25 RL = 1 k 20 RL = 150 15 10 5 74 72 -40 -20 0 20 40 60 80 100 0 ±4 TA - Free-Air Temperature - °C ±6 ±8 ±10 Figure 17 POST OFFICE BOX 655303 ±12 VCC - Supply Voltage - V Figure 16 12 100k f - Frequency - Hz · DALLAS, TEXAS 75265 ±14 ±16 THS4061 THS4061, THS4062 THS4062 180MHz HIGHSPEED AMPLIFIERS SLOS234E SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE NOISE SPECTRAL DENSITY vs FREQUENCY 10 180 E nv - Noise Spectral Density - nV/ Hz TA = 25°C I CC - Supply Current - mA 9 VCC = ±15 V 8 VCC = ±5 V 7 6 5 4 -40 -20 0 20 40 60 80 160 140 120 100 80 60 40 20 0 10 100 100 TA - Free-Air Temperature - °C Figure 18 100k TOTAL HARMONIC DISTORTION vs FREQUENCY -40 -40 Gain = 2 VCC = ±15 V RL = 150 THD - Total Harmonic Distortion - dB THD - Total Harmonic Distortion - dB 10k Figure 19 TOTAL HARMONIC DISTORTION vs FREQUENCY -50 1k f - Frequency - Hz -60 -70 2nd Harmonic -80 3rd Harmonic -90 -100 -110 100k 1M 10M -50 Gain = 2 VCC = ±5 V RL = 150 -60 -70 2nd Harmonic -80 3rd Harmonic -90 -100 -110 100k f - Frequency - Hz 1M 10M f - Frequency - Hz Figure 20 Figure 21 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 13 THS4061 THS4061, THS4062 THS4062 180MHz HIGHSPEED AMPLIFIERS SLOS234E SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS CROSSTALK vs FREQUENCY CROSSTALK vs FREQUENCY 0 0 -20 Crosstalk - dBc -30 -10 -20 Crosstalk - dBc -10 G = 2, RF = 300 W, RL = 100 W, VO = 200 mVPP, VS = +15 V See Figure 24 -40 -50 CH B to A -60 -70 -30 G = 2, RF = 300 W, RL = 100 W, VO = 200 mVPP, VS = +5 V See Figure 24 -40 CH B to A -50 -60 CH A to B -70 CH A to B -80 -80 -90 -90 -100 100 k 1M 10 M 100 M 1G -100 100 k 1M 10 M f - Frequency - Hz f - Frequency - Hz Figure 22 Figure 23 300 W 300 W - THS4062 THS4062 A + VIN 100 W 49.9 W 300 W 300 W - THS4062 THS4062 B + 50 W Load Measured 49.9 W 49.9 W Figure 24. Test Circuits 14 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 100 M 1G THS4061 THS4061, THS4062 THS4062 180MHz HIGHSPEED AMPLIFIERS SLOS234E SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 APPLICATION INFORMATION theory of operation The THS406x is a high speed, operational amplifier configured in a voltage feedback architecture. It is built using a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing fTs of several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high slew rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 25. (7) VCC + (6) OUT IN - (2) IN + (3) (4) VCC - NULL (1) NULL (8) Figure 25. THS4061 THS4061 Simplified Schematic POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 15 THS4061 THS4061, THS4062 THS4062 180MHz HIGHSPEED AMPLIFIERS SLOS234E SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 APPLICATION INFORMATION offset nulling The THS4061 THS4061 has very low input offset voltage for a high-speed amplifier. However, if additional correction is required, an offset nulling function has been provided. By placing a potentiometer between terminals 1 and 8 and tying the wiper to the negative supply, the input offset can be adjusted. This is shown in Figure 26. VCC+ 0.1 µF + THS4061 THS4061 _ 10 k 0.1 µF VCC - Figure 26. Offset Nulling Schematic optimizing unity gain response Internal frequency compensation of the THS406x was selected to provide very wideband performance yet still maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated in this manner there is usually peaking in the closed loop response and some ringing in the step response for very fast input edges, depending upon the application. This is because a minimum phase margin is maintained for the G=+1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 270 should be used as shown in Figure 27. Additional capacitance can also be used in parallel with the feedback resistance if even finer optimization is required. Input + Output THS406x _ 270 Figure 27. Noninverting, Unity Gain Schematic 16 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 THS4061 THS4061, THS4062 THS4062 180MHz HIGHSPEED AMPLIFIERS SLOS234E SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 APPLICATION INFORMATION driving a capacitive load Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS406x has been internally compensated to maximize its bandwidth and slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the output will decrease the device's phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 28. A minimum value of 20 should work well for most applications. For example, in 75- transmission systems, setting the series resistor value to 75 both isolates any capacitance loading and provides the proper line impedance matching at the source end. 510 510 Input _ 20 Output THS406x + CLOAD Figure 28. Driving a Capacitive Load circuit layout considerations In order to achieve the levels of high frequency performance of the THS406x, it is essential that proper printed-circuit board high frequency design techniques be followed. A general set of guidelines is given below. In addition, a THS406x evaluation board is available to use as a guide for layout or for evaluating the device performance. D Ground planes - It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. D Proper power supply decoupling - Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distances increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. D Sockets - Sockets are not recommended for high-speed operational amplifiers. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. D Short trace runs/compact part placements - Optimum high frequency performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance at the input of the amplifier. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 17 THS4061 THS4061, THS4062 THS4062 180MHz HIGHSPEED AMPLIFIERS SLOS234E SLOS234E - DECEMBER 1998 - REVISED DECEMBER 2003 APPLICATION INFORMATION circuit layout considerations (continued) D Surface-mount passive components - Using surface-mount passive components is recommended for high-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. evaluation board An evaluation board is available for the THS4061 THS4061 (literature number SLOP226 SLOP226) and THS4062 THS4062 (literaure number SLOP235 SLOP235). This board has been configured for very low parasitic capacitance in order to realize the full performance of the amplifier. A schematic of the evaluation board is shown in Figure 29. The circuitry has been designed so that the amplifier may be used in either an inverting or noninverting configuration. To order the evaluation board contact your local TI sales office or distributor. For more detailed information, refer to the THS4061 THS4061 EVM User's Manual (literature number SLOU038 SLOU038) or the THS4062 THS4062 EVM User's Manual (literature number SLOU040 SLOU040) VCC+ + C3 0.1 µF R4 1 k IN + C2 6.8 µF NULL R5 49.9 + R3 49.9 OUT THS4061 THS4061 _ NULL R2 1 k + C4 0.1 µF C1 6.8 µF IN - R1 49.9 VCC - Figure 29. THS4061 THS4061 Evaluation Board Schematic 18 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-9960101Q2A 5962-9960101Q2A ACTIVE LCCC FK 20 1 TBD 5962-9960101QPA 5962-9960101QPA ACTIVE CDIP JG 8 1 TBD POST-PLATE N / A for Pkg Type A42 SNPB THS4061CD THS4061CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4061CDG4 THS4061CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4061CDGN THS4061CDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4061CDGNR THS4061CDGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4061CDGNRG4 THS4061CDGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4061CDR THS4061CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4061CDRG4 THS4061CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4061ID THS4061ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4061IDGN THS4061IDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4061IDGNG4 THS4061IDGNG4 ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4061IDGNR THS4061IDGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4061IDGNRG4 THS4061IDGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4061IDR THS4061IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4061IDRG4 THS4061IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4061MFKB THS4061MFKB ACTIVE LCCC FK 20 1 TBD N / A for Pkg Type POST-PLATE N / A for Pkg Type THS4061MJG THS4061MJG ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type THS4061MJGB THS4061MJGB ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type THS4062CD THS4062CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4062CDGN THS4062CDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4062CDGNG4 THS4062CDGNG4 ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4062CDGNR THS4062CDGNR ACTIVE MSOPPower DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2006 Orderable Device Status (1) Package Type THS4062CDGNRG4 THS4062CDGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4062CDR THS4062CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4062CDRG4 THS4062CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4062ID THS4062ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4062IDGN THS4062IDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4062IDGNR THS4062IDGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4062IDGNRG4 THS4062IDGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4062IDR THS4062IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4062IDRG4 THS4062IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) PAD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MCER001A MCER001A JANUARY 1995 REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°15° 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MECHANICAL DATA MLCC006B MLCC006B OCTOBER 1996 FK (S-CQCC-N*) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS * 12 A B 11 20 MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 19 MIN 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 10 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 MS-004 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/video Wireless Mailing Address: www.ti.com/telephony Video & Imaging www.ti.com/wireless Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2006, Texas Instruments Incorporated