THC63LVD104C THC63LVD104A TCLKTHC63LVD104C 00TYP - Datasheet Archive
THC63LVD104C 112MHz 30Bits COLOR LVDS Receiver General Description Features The THC63LVD104C receiver is designed to support
THC63LVD104C THC63LVD104C_Rev.1.10_E THC63LVD104C THC63LVD104C 112MHz 30Bits COLOR LVDS Receiver General Description Features The THC63LVD104C THC63LVD104C receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The THC63LVD104C THC63LVD104C converts the LVDS data streams back into 35bits of CMOS/TTL data with the choice of the rising edge or falling edge clock for the convenience with a variety of LCD panel controllers.At a transmit clock frequency of 112MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC, VSYNC,DE,CNTL1,CNTL2) are transmitted at an effective rate of 784Mbps per LVDS channel.Using a 112MHz clock, the data throughput is 490Mbytes per second. · Wide dot clock range: 8-112MHz suited for NTSC, VGA, SVGA, XGA, and SXGA · · · · · · · PLL requires no external components 50% output clock duty cycle TTL clock edge programmable Power down mode Low power single 3.3V CMOS design 64pin TQFP Backward compatible with THC63LVDF64x (18bits) / F84x(24bits) · Pin compatible with THC63LVD104A THC63LVD104A · Fail-safe for Open LVDS Input Block Diagram LVDS INPUT CMOS/TTL OUTPUT 7 RC+/RD+/- RCLK+/- RD6-RD0 7 PLL RC6-RC0 7 RE+/- RB6-RB0 7 SERIAL TO PARALLEL RB+/- RA6-RA0 7 RA+/- RE6-RE0 CLKOUT (8 to 112MHz) CMOS/TTL INPUT TEST PD OE R/F Copyright©2010 THine Electronics, Inc. 1/13 THine Electronics, Inc. THine THC63LVD104C THC63LVD104C_Rev.1.10_E 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC RA0 RA1 RA2 GND RA3 RA4 RA5 RA6 RB0 RB1 VCC RB2 RB3 RB4 RB5 Pin Out 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 RB6 CLKOUT GND RC0 RC1 RC2 RC3 RC4 RC5 VCC RC6 RD0 RD1 RD2 RD3 RD4 GND TEST PD OE R/F RE6 RE5 RE4 VCC RE3 RE2 RE1 RE0 RD6 RD5 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RARA+ RBRB+ LVCC RCRC+ RCLKRCLK+ LGND RDRD+ RERE+ PGND PVCC Copyright©2010 THine Electronics, Inc. 2/13 THine Electronics, Inc. THine THC63LVD104C THC63LVD104C_Rev.1.10_E Pin Description Pin Name Pin # Type RA+, RA- 50, 49 LVDS IN RB+, RB- 52, 51 LVDS IN RC+, RC- 55, 54 LVDS IN RD+, RD- 60, 59 Description LVDS IN RE+,RE- 62, 61 LVDS IN RCLK+, RCLK- 57, 56 LVDS IN RA6 ~ RA0 40,41,42,43,45,46,47 OUT RB6 ~ RB0 32,33,34,35,36,38,39 LVDS Data In. OUT LVDS Clock In. RC6 ~ RC0 22,24,25,26,27,28,29 OUT RD6 ~ RD0 14,15,17,18,19,20,21 OUT CMOS/TTL Data Outputs. RE6 ~ RE0 6,7,8,10,11,12,13 OUT TEST 2 IN PD 3 IN OE 4 IN R/F 5 IN VCC 9,23,37,48 Power Power Supply Pins for TTL outputs and digital circuitry. CLKOUT 31 OUT Clock out. GND 1,16,30,44 Ground Ground Pins for TTL outputs and digital circuitry. LVCC 53 Power Power Supply Pin for LVDS inputs. LGND 58 Ground Ground Pin for LVDS inputs. PVCC 64 Power Power Supply Pin for PLL circuitry. PGND 63 Ground Ground Pin for PLL circuitry. Test pin, must be "L" for normal operation. H: Normal operation, L: Power down (all outputs are "L") H: Output enable (Normal operation). L: Output disable(all outputs are Hi-Z) Output Clock Triggering Edge Select. H: Rising edge, L: Falling edge Data Outputs PD R/F OE CLKOUT 0 0 0 Hi-Z Hi-Z 0 0 1 All 0 Fixed Low 0 1 0 Hi-Z Hi-Z 0 1 1 All 0 Fixed Low 1 0 0 Hi-Z Hi-Z 1 0 1 Data Out The falling edge closer to the center of the data eye. 1 1 0 Hi-Z Hi-Z 1 1 1 Data Out The rising edge closer to the center of the data eye. (Rxn) * Rxn x = A,B,C,D,E n = 0,1,2,3,4,5,6 Copyright©2010 THine Electronics, Inc. 3/13 THine Electronics, Inc. THine THC63LVD104C THC63LVD104C_Rev.1.10_E Absolute Maximum Ratings 1 Supply Voltage (VCC=VCC=LVCC=PVCC) -0.3V ~ +4.0V CMOS/TTL Input Voltage -0.3V ~ (VCC + 0.3V) CMOS/TTL Output Voltage -0.3V ~ (VCC + 0.3V) LVDS Receiver Input Voltage -0.3V ~ (VCC + 0.3V) Output Current -30mA ~ 30mA Junction Temperature +125 °C Storage Temperature Range -55 °C ~ +150 °C Resistance to soldering heat +260 °C /10sec Maximum Power Dissipation @+25 °C 2.2W Electrical Characteristics CMOS/TTL DC Specifications VCC =LVCC=PVCC= 3.0V ~ 3.6V, Ta = -20 °C ~ +85 °C Symbol Parameter Conditions Min. Typ. Max. Units VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage GND 0.8 V VOH High Level Output Voltage VOL Low Level Output Voltage IINC Input Current IOH= -4mA (data) IOH= -8mA (clock) 2.4 V IOL= 4mA (data) 0.4 0V V IN V CC V ± 10 IOL= 8mA (clock) A LVDS Receiver DC Specifications VCC =LVCC=PVCC= 3.0V ~ 3.6V, Ta = -20 °C ~ +85 °C Symbol Parameter Conditions VTH Differential Input High Threshold VIC= 1.2V VTL Differential Input Low Threshold VIC= 1.2V IINL Input Current Min. VIN= 2.4V / 0V VCC= 3.6V Typ. Max. 100 -100 Units mV mV 30 A 1. "Absolute Maximum Ratings" are those values beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation. Copyright©2010 THine Electronics, Inc. 4/13 THine Electronics, Inc. THine THC63LVD104C THC63LVD104C_Rev.1.10_E Supply Current VCC =LVCC=PVCC= 3.0V ~ 3.6V, Ta = -20 °C ~ +85 °C Symbol Parameter Conditions fCLKOUT = 75MHz fCLKOUT = 90MHz (LVDS Full Toggle) IRCCW IRCCS Max. Units fCLKOUT = 112MHz CL=8pF,Vcc=3.6V, Ta= -20 °C ~70 °C * Receiver Power Down Supply Current PD = L 205 mA 236 mA 280 mA 25 Current CL=8pF,Vcc=3.6V, Ta= -20 °C ~ 85 °C Receiver Supply Typ. A *The trade-off between the output load and the ambient temperature exists so that the junction temperature does not exceed 125 °C . LVDS Full Toggle Pattern CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 x=A,B,C,D,E Copyright©2010 THine Electronics, Inc. 5/13 THine Electronics, Inc. THine THC63LVD104C THC63LVD104C_Rev.1.10_E Output load limitation The output load is limited so that the junction temperature does not exceed 125 °C . 25.0 Output Load[pF] 20.0 15.0 10.0 5.0 Ta=70 Ta=85 0.0 8 28 48 68 88 108 Frequency[MHz] Copyright©2010 THine Electronics, Inc. 6/13 THine Electronics, Inc. THine THC63LVD104C THC63LVD104C_Rev.1.10_E Switching Characteristics VCC =LVCC=PVCC= 3.0V ~ 3.6V, Ta = -20 °C ~+85 °C Symbol Parameter Min. Typ. Max. Units tRCP CLKOUT Period tRCH CLKOUT High Time T -2 ns tRCL CLKOUT Low Time T -2 ns tRS TTL Data Setup to CLKOUT 4 - t RCP 1 7 ns tRH TTL Data Hold from CLKOUT 3 - t RCP 1 7 ns tTLH TTL Low to High Transition Time 1.0 3.0 ns tTHL TTL High to Low Transition Time 1.0 3.0 ns 8.92 T 125.0 ns CLKOUT=50MHz 0 1000 ps Receiver Skew CLKOUT=75MHz -550 0 550 ps Margin CLKOUT=90MHz -400 0 400 ps CLKOUT=112MHz tSK -1000 -250 0 250 ps - tSK 0 + tSK ns tRIP1 Input Data Position0 tRIP0 Input Data Position1 t RCIP - t S K 7 t RCIP -7 t RCIP - + t S K 7 ns tRIP6 Input Data Position2 t RCIP 2 - t S K 7 t RCIP 2 -7 t RCIP 2 - + t S K 7 ns tRIP5 Input Data Position3 t RCIP 3 - t S K 7 t RCIP 3 -7 t RCIP 3 - + t S K 7 ns tRIP4 Input Data Position4 t RCIP 4 - t S K 7 t RCIP 4 -7 t RCIP 4 - + t S K 7 ns tRIP3 Input Data Position5 t RCIP 5 - t S K 7 t RCIP 5 -7 t RCIP 5 - + t S K 7 ns tRIP2 Input Data Position6 t RCIP 6 - t S K 7 t RCIP 6 -7 t RCIP 6 - + t S K 7 ns tRPLL Phase Lock Loop Set tRCD RCLK +/- to CLKOUT Delay tRCIP CLKIN Period 10.0 46.5 Copyright©2010 THine Electronics, Inc. 7/13 52.5 ns 8.92 CLKOUT=75MHz ms 125.0 ns THine Electronics, Inc. THine THC63LVD104C THC63LVD104C_Rev.1.10_E AC Timing Diagrams TTL Outputs TTL Output 80% 80% CL=8pF 20% 20% TTL Output Load tTHL tTLH tRCP tRCH tRCL R/F = L VCC/2 VCC/2 VCC/2 tRS CLKOUT tRH R/F = H Rxn VCC/2 VCC/2 x = A,B,C,D,E n = 0,1,2,3,4,5,6 Copyright©2010 THine Electronics, Inc. 8/13 THine Electronics, Inc. THC63LVD104C THC63LVD104C_Rev.1.10_E AC Timing Diagrams Phase Lock Loop Set Time VCC 3.0V RCLK+/- 2.0V PD tRPLL 2.0V CLKOUT RCLK +/- to CLKOUT Delay RCLK+ Note: 1)Vdiff = (RCLK+) - (RCLK-) Vdiff=0V Ry+/y = A,B,C,D,E Current Data tRCD CLKOUT R/F = L VCC/2 Rxn Current Data x = A,B,C,D,E n = 0,1,2,3,4,5,6 Copyright©2010 THine Electronics, Inc. 9/13 THine Electronics, Inc. THC63LVD104C THC63LVD104C_Rev.1.10_E AC Timing Diagrams LVDS Inputs tRCIP Vdiff = 0V Vdiff = 0V RCLK+ (Differential) RA+/- RA3' RA2' RA1' RA0' RA6 RA5 RA4 RA3 RA2 RA1 RA0 RA6'' RB+/- RB3' RB2' RB1' RB0' RB6 RB5 RB4 RB3 RB2 RB1 RB0 RB6'' RC+/- RC3' RC2' RC1' RC0' RC6 RC5 RC4 RC3 RC2 RC1 RC0 RC6'' RD+/- RD3' RD2' RD1' RD0' RD6 RD5 RD4 RD3 RD2 RD1 RD0 RD6'' RE+/- RE3' RE6 RE5 RE4 RE3 RE2 RE1 RE0 RE2' RE1' RE0' Previous Cycle Current Cycle RE6'' Next Cycle tRIP1 tRIP0 tRIP6 tRIP5 tRIP4 tRIP3 tRIP2 Copyright©2010 THine Electronics, Inc. 10/13 THine Electronics, Inc. THine THC63LVD104C THC63LVD104C_Rev.1.10_E Note 1)Power On Sequence Power on LVDS-Tx after THC63LVD104C THC63LVD104C. If it is not avoidable, please contact to firstname.lastname@example.org (for FAE mailing list) 2)Cable Connection and Disconnection Don't connect and disconnect the LVDS cable, when the power is supplied to the system. 3)GND Connection Connect the each GND of the PCB which LVDS-Tx and THC63LVD104C THC63LVD104C on it. It is better for EMI reduction to place GND cable as close to LVDS cable as possible. 4)Multi Drop Connection Multi drop connection is not recommended. TCLK+ LVDS-Tx THC63LVD104C THC63LVD104C TCLKTHC63LVD104C TCLKTHC63LVD104C 5)Asynchronous use Asynchronous use such as following systems are not recommended. If it is not avoidable, please contact to email@example.com (for FAE mailing list) CLKOUT TCLK+ LVDS-Tx DATA IC CLKOUT TCLK- CLKOUT THC63LVD104C THC63LVD104C IC TCLK+ LVDS-Tx DATA TCLK- THC63LVD104C THC63LVD104C TCLK+ TCLKIC Copyright©2010 THine Electronics, Inc. DATA CLKOUT THC63LVD104C THC63LVD104C DATA IC TCLK+ TCLK- DATA THC63LVD104C THC63LVD104C 11/13 DATA THine Electronics, Inc. THC63LVD104C THC63LVD104C_Rev.1.10_E Package INDEX 64 49 PIN No.1 33 16 32 1.2MAX 17 1.00TYP 00TYP 12.0TYP 0.2 10.0TYP 0.5TYP 48 UNITS: mm Copyright©2010 THine Electronics, Inc. 12/13 THine Electronics, Inc. THC63LVD104C THC63LVD104C_Rev.1.10_E Notices and Requests 1. The product specifications described in this material are subject to change without prior notice. 2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. We are not responsible for possible errors and omissions in this material. Please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. This material contains our copy right, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. This product is presumed to be used for general electric equipment, not for the applications which require very high reliability (including medical equipment directly concerning people's life, aerospace equipment, or nuclear control equipment). Also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various Types of safety equipment, please do it after applying appropriate measures to the product. 6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. Please note that this product is not designed to be radiation-proof. 8. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Control Law. THine Electronics, Inc. E-mail: firstname.lastname@example.org Copyright©2010 THine Electronics, Inc. 13/13 THine Electronics, Inc.