TDA933XH AN98073 TDA9330/31/32 TDA933X-N1 TDA933X QFP-44 QFP44 TDA61XX TDA8350 - Datasheet Archive

 

Application information for I2C-bus controlled TV-processor TDA933XH AN98073 Philips Semiconductors E W Philips Semiconductors

 

APPLICATION NOTE Application information for I2C-bus controlled TV-processor TDA933XH TDA933XH AN98073 AN98073 Philips Semiconductors E W Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 Abstract This report gives a description of the TDA933X-N1 TDA933X-N1 version, together with application aspects. 2 Purchase of Philips I C components conveys 2 a license under the I C patent to use the 2 components in the I C system, provided the 2 system conforms to the I C specifications defined by Philips. © Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. 2 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 APPLICATION NOTE Application information for I2Cbus controlled TV-processor TDA933XH TDA933XH AN98073 AN98073 Author(s): P.C.T.J. Laro R.P. Vermeulen Design & Application Department, Consumer ICs Nijmegen, The Netherlands Keywords Synchronisation H/V Single / Double scan, VGA Geometry on vertical and E-W Continuous cathod calibration 2 I C controlled Date: October 1998 3 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 Summary This report gives a description of the TDA933X TDA933X together with application aspects. The TDA933X TDA933X is the combination of a RGB output processor an a deflection processor, suitable for single scan, double scan and VGA. 4 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 CONTENTS 1. INTRODUCTION.9 2. DEVICE INFORMATION.11 2.1 Pinning configuration for QFP-44 QFP-44 .13 2.2 Device description per functional block.14 2.2.1 Horizontal synchronisation .16 2.2.2 Vertical synchronisation/deflection and geometry (horizontal & vertical) .22 2.2.3 RGB processing and control .32 2.2.4 I²C bus description .44 3. APPLICATION INFORMATION.61 3.1 General.61 3.2 Application remarks per functional block and per pin.61 3.2.1 Horizontal synchronisation .61 3.2.2 Geometry (drive of vertical deflection) and Vertical & Horizontal.69 3.2.3 RGB processing and control. .74 3.2.4 Supply, decoupling and grounding .82 3.3 Application of non-used pins .85 4. ALIGNMENTS.87 4.1 Colour temperature alignment .87 4.2 Geometry alignment .87 5. REMARKS FOR THE TDA 933X N1 VERSION.89 6. REFERENCES .91 5 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 LIST OF FIGURES FIG 1 : PINNING DIAGRAM OF QFP44 QFP44 FIG 2 : SANDCASTLE WAVEFORM. FIG 3 : SLOW START / SLOW STOP HORIZONTAL OUTPUT. FIG 4 : FIELD DETECTION MECHANISM FOR VSR=0(A) AND VSR=1(B) FIG 5 : 1FH TIMING DIAGRAM FIG 6 : 2FH TIMING DIAGRAM FIG 7 : MATRIX OPTIONS FIG 8 : BLUE STRETCHER FIG 9 : DC-LEVEL AT RGB OUTPUTS FIG 10 : CCC-LOOP CORRECTION MECHANISMS FIG 11 : BASIC APPLICATION OF THE CCC-LOOP WITH THE TDA61XX TDA61XX FIG 12 : MAIN BLOCKS OF THE CCC-LOOP FIG 13 : INTERFACE VERTICAL GUARD PULSE FIG 14 : FLYBACK INPUT CIRCUIT FIG 15 : PHI-2 TIMING SIGNAL FIG 16 : HORIZONTAL SHIFT. FIG 17 : SIMPLIFIED DIAGRAM X-TAL OSCILLATOR FIG 18 : LOW POWER START-UP CIRCUIT FIG 19 : VERTICAL DRIVE SIGNALS WITH TDA8350 TDA8350 FIG 20 : EW OUTPUT CONFIGURATION FIG 21 : EXPAND AND COMPRESS MODE BEHAVIOUR FIG 22 : BLENDER OUTPUT FIG 23 : BEAM CURRENT LIMITING INPUT - STANDARD APPLICATION FIG 24 : MAXIMUM RGB OUTPUT FIG 25 : RANGE RGB MEASURING PULSES. FIG 26 : EMITTER FOLLOWER TO IMPROVE BANDWIDTH FIG 27 : CONNECTING RGB STAGE FIG 28 : CURRENT DIVIDER IN CCC LOOP FIG 29 : SCAN SUPPLY SENSE CIRCUIT FIG 30 : PIN 43 APPLICATION FOR FBSCO 6 13 18 20 23 25 26 33 34 37 38 39 40 62 63 64 65 66 67 69 70 73 75 76 77 77 78 78 79 81 81 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 SYSTEM DIAGRAMS A 1: BLOCK DIAGRAM: HORIZONTAL AND VERTICAL SYNCHRONISATION A 2: BLOCK DIAGRAM: GEOMETRY ON VERTICAL AND E-W DRIVE A 3: BLOCK DIAGRAM: YUV/RGB PROCESSING. A 4: BLOCK DIAGRAM: RGB-PROCESSING AND CONTROL. 21 31 35 43 B 1 : INTERNAL PINNING DIAGRAM (1-11) B 2 : INTERNAL PINNING DIAGRAM (12-19) B 3 : INTERNAL PINNING DIAGRAM (20-34) B 4 : INTERNAL PINNING DIAGRAM (35-44) 93 95 97 99 C 1 : APPLICATION DIAGRAM OF TDA933X TDA933X 101 LIST OF TABLES TABLE 1 : SURVEY FEATURES / TYPE TABLE 2 : APPLICATION INFO PER PIN NUMBER TABLE 3 : APPLICATION INFO PER PIN NAME TABLE 4 : CONDITION PHI-1 LOOP TABLE 5 : H/V SETTINGS FOR ASPECT RATIO'S AS 16:9 AND 4:3 7 12 14 15 44 73 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 8 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 1. INTRODUCTION This report gives a description of the TDA933X TDA933X together with application aspects. The TDA933X TDA933X is the successor of the TDA 478X RGB processor and TDA 9150 deflection processor. It has a higher degree of integration and additional features. The TDA933X TDA933X is a combination of a RGB output processor and deflection processor with I2C control. The TDA933X TDA933X matches ideal with the versatile TDA9321 TDA9321 (see ref. 2, 4) input processor (IF + video switches + full multistandard colour decoder) for set architectures using extra YUV processing like PAL plus and scan conversion (progressive scan or "100 Hz"). All chips contain the RGB control processing with YUV input, 2 linear RGB inputs one of which has a blending option, deflection processing with H and V input, stable clock generation using an external X-tal/resonator, drive signal generation for horizontal & vertical deflection and East West (diode modulator). Versions are available with VGA option, having a multi-sync mode for horizontal synchronisation between 30 - 50 kHz (or 15 - 25 kHz) and stabilised vertical amplitude independent of the vertical frequency. The number of external components required for application is considerably less than equivalent two or three chip concepts. All necessary alignments can be done via I²C control. The device is available in QFP 44 (Quad Flat Pack, 44 pins) package. The complete integration of all functions on a single chip has been realised using the BIMOS technology (combined BIpolar and MOS). The high frequent bipolar process is used for video processing. The MOS process is used for all digital parts. Due to MOS components, it is possible to integrate very large time constants. 9 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 10 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 2. DEVICE INFORMATION The TDA933X TDA933X TV display processor is the combination of a RGB output processor and deflection processor The device matches ideal with the versatile input processor TDA9321 TDA9321 (see ref. 2, 4, IF + video switches + full multi-system colour decoder including Pal plus helper demodulation) in set architectures with additional YUV processing like PAL plus or scan conversion (progressive scan or "100 Hz"). Below the features available in all versions will be discussed. The additional features are described separately. Available in all versions RGB - RGB control (brightness, contrast, saturation) - Improved black current stabilisation (continuous cathode calibration) - White point adjustment - Blue stretch which offsets colours near white to blue - Option to insert "blue back" when no video signal is available - Black stretching of non standard luminance signals - Switchable matrices for colour difference signals Input - YUV input - Linear RGB input 1 with fast blanking for SCART RGB or VGA signals with full control (brightness, contrast, saturation) - Linear RGB input 2 for TEXT / OSD with blending option for mixing YUV or RGB 1 input with TEXT / OSD. RGB input 2 has only brightness control Synchronisation and Deflection - Stable clock generation using an external 12 MHz ceramic resonator or X-tal - Suitable for single scan (1 Fh, 1 Fv), progressive scan (2 Fh, 1 Fv) and double scan (2 Fh, 2 Fv) applications - Horizontal synchronisation with two control loops and alignment free horizontal oscillator - Slow start and slow stop of the horizontal drive output to enable low stress start-up and switch-off from the line circuit at nominal line supply voltage. - Low power start-up option to generate horizontal drive pulses from only 5V/3mA supply - Vertical count-down circuit for stable behaviour, including absence of HD / VD synchronisation pulses - Horizontal and vertical geometry control - Vertical drive optimised for DC coupled vertical output stages - Independent horizontal and vertical linear zoom for 16:9 expand or 4:3 compress - Horizontal range: 65% to 100% - Vertical range: 75% to 138% - Vertical blanking for overscan - Extended horizontal blanking to display a 4:3 picture on a 16:9 tube while blanking the standard 6% overscan which is not visible on a 4:3 tube. - Vertical scroll for optimal display in combination with vertical zoom - Option to switch-off in the vertical overscan to minimise visability of the discharge of the picture tube. Control - Full I²C bus control, as well for customer controls as for factory alignment Power consumption Low power consumption 11 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 Packaging - QFP-44 QFP-44 (Quad Flat Pack, 44 pins SOT 307-2) Additional features The additional features, varying per type, are described below. In table 1 the featuring per type is given. Synchronisation and Deflection - VGA multi-sync mode with a horizontal frequency range of 30 - 50 kHz (2 Fh mode) or 15 - 25 kHz (1 Fh mode) and stabilised vertical amplitude independent of the vertical frequency - Linear DC output proportional to the horizontal frequency for power supply adaptation Survey of additional features / type IC version TDA9330H TDA9330H DAC output voltage (pin 25) I2C controlled TDA9332H TDA9332H X VGA mode TDA9331H TDA9331H X X DAC output voltage (pin 25) proportional to VGA frequency Table 1 : Survey features / type 12 X X Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 2.1 Pinning configuration for QFP-44 QFP-44 34 PWL 35 RI2 36 GI2 37 BI2 38 BL2 39 VP2 40 RO 41 GO 42 BO 43 BCL 44 BLKIN The TDA933X TDA933X is available in Quad Flat Package QFP-44 QFP-44 SOT 307-2. VDOA 1 33 BL1 VDOB 2 32 BI1 EWO 3 31 GI1 EHTIN 4 30 RI1 FLASH 5 29 FBCSO GND1 6 28 YIN TDA933xH DECVD 7 27 UIN HOUT 8 26 VIN Fig 1 : Pinning diagram of QFP44 QFP44 13 LPSU 22 XTALO 21 XTALI 20 GND2 19 DECBG 18 VP1 17 23 VD Iref 16 SDA 11 VSC 15 24 HD DPC 14 SCL 10 HFB 13 25 DACOUT HSEL 12 SCO 9 MGR446 MGR446 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 2.2 Device description per functional block The TDA933X TDA933X is organised in functional blocks. These different blocks are: Horizontal and vertical synchronisation Horizontal and vertical geometry RGB processing & control Supply decoupling Control I²C bus A description of each functional block has been made together with the corresponding block diagrams. The internal circuits, connected to the pins, are shown on page 93 to 99. In the table below, all pin numbers are given with the page number where application information can be found. Pin Page Pin Page Pin Page Pin Page 1 69 12 63 23 71 34 76 2 69 13 63 24 67 35 74 3 70 14 64 25 68 36 74 4 71 15 71 26 74 37 74 5 61 16 71 27 74 38 75 6 82 17 82 28 74 39 82 7 82 18 82 29 81 40 76 8 61 19 82 30 74 41 76 9 62 20 66 31 74 42 76 10 - 21 66 32 74 43 76 11 - 22 67 33 74 44 78 Table 2 : Application info per pin number 14 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor PIN NAME BCL BI1 BI2 BL1 BL2 BLCIN BO DACOUT DECBG DIGSUP DPC EHTIN EWOUT FBCSO FLASH GI1 GI2 GND1 GND2 GO HD HFB HOUT HSEL IREF LPSU NDOA NDOB PWL RI1 RI2 RO SANDC SCL SDA UIN VD VIN VP1 VP2 VSC XTALI XTALO YIN Application Note AN98073 AN98073 PIN # 43 32 37 33 38 44 42 25 18 7 14 4 3 29 5 31 36 6 19 41 24 13 8 12 16 22 1 2 34 30 35 40 9 10 11 27 23 26 17 39 15 20 21 28 PIN DESCRIPTION Beam current limiting input Blue input 1 Blue input 2 RGB 1 insertion switch input RGB 2 insertion switch input Black current input Blue out DAC output Bandgap Decoupling Digital supply decoupling PHI-2 dynamic phase compensation input EHT tracking / overvoltage protection EW drive Fixed beam current switch-off input Flash detection input Green input 1 Green input 2 Grounding Grounding Green output Horizontal synchronisation input Flyback input Horizontal drive Horizontal frequency selection Reference current Low power start-up Vertical drive Vertical drive Peak white limiting capacitor Red input 1 Red input 2 RGB output Sandcastle output/Vertical guard input I2C Clock line I2C Data line U input Vertical synchronisation input V input Supply Supply Vertical sawtooth Reference oscillator input Reference oscillator input Y input Table 3 : Application info per pin name 15 PAGE # 76 74 74 74 75 78 76 68 82 82 64 71 70 81 61 74 74 82 82 76 67 63 61 63 71 67 69 69 76 74 74 76 62 74 71 74 82 82 71 66 66 74 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 2.2.1 Horizontal synchronisation See also the related block diagram (A 1 on page 21). The main functions are: * Horizontal oscillator, reference oscillator and acquisition loop ("PHI-1") * PHI-2 detector and sandcastle generation * Horizontal output with slow start/stop facility * Flash protection * Main function description Next, the main functions for sync will be described. See also the related paragraphs in the chapter I2C bus description. * Horizontal oscillator, reference oscillator and acquisition loop ("PHI-1") The horizontal oscillator requires no external components and is fully integrated. The oscillator consists of a VCO, running at a frequency of 880 * Fh = 880 * 15.625 kHz = 13.75 MHz. The horizontal VCO is controlled by: - The loop filter voltage - The calibration voltage VCAL from the reference oscillator (for free running mode) - The voltage from the auto synchronisation loop (only for types with VGA mode) The calibration voltage VCAL which stabilises the free running frequency is generated by the 12 MHz reference oscillator block which needs an external resonator. It is also possible to use a 12 MHz X-tal as reference or to feed an external 12 MHz reference signal to pin 20. The correct calibration of the horizontal VCO by the reference oscillator can be checked reading bit NRF. This bit should be checked under the following conditions, because when the horizontal VCO is not locked to the reference oscillator, the frequency of the horizontal drive can be incorrect: - At power-on / initialisation before switching-on the horizontal drive - After power dip (shutdown detection, POR = 1), re-initialisation is required The horizontal frequency for H-drive and reference signal for the acquisition loop ("PHI-1") and PHI-2 is derived from the horizontal VCO frequency using a divider chain. In this chain, various timing signals are derived for signal processing in all blocks. An acquisition loop, consisting of a PLL with built-in loop filter, locks the horizontal VCO to the incoming synchronisation signal HD using a phase detector with as input HD and the divided VCO signal. The signal HD is generated by the input processor (e.g TDA9321 TDA9321) or by scan conversion circuitry. The loop filter is integrated. The loop speed can be increased by 30 % by decreasing the internal time constant by 30% setting I2C bit FAST to 1, Though this function is analogue to the PHI-1 loop of synchronisation circuits, this phase detector loop has only the task to synchronise the horizontal VCO with the HD input and lacks therefore the sync separator, gating functions and different loopfilter time constants for synchronising under bad and noisy signal conditions. Selection between 1 Fh and 2 Fh mode The horizontal frequency can be set to 1 Fh or 2 Fh using a switchable divide-by-2 or divide-by-1 prescaler. The selection of the prescaler is hard wired for robustness. By connecting pin 12 to ground the prescaler is set to divide-by-2, giving 1 Fh horizontal frequency. By leaving pin 12 open, the prescaler is set to divide-by-1, giving 2 Fh horizontal frequency. Though this selection is meant for hard-wiring, it is possible to switch between 1 Fh and 2 Fh mode by pulling pin 12 low or not using a transistor. Because the status of pin 12 is only checked when switching on from stand-by, changing the level on pin 12 will first take effect when both stand-by bits STB1,0 are toggled from 0 0 to 1 1. In this way, switching the level on pin 12 while the horizontal output is running will not change the horizontal output frequency, preventing damage to the horizontal deflection stage. However, for safe behaviour under various conditions (e.g. power supply dips) we advice to switch only pin 12 while the TDA933X TDA933X is in stand-by mode. 16 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 TV-mode When no HD pulse is present, the free running horizontal frequency is set to 16.05 kHz (1 Fh mode) or 32.1 kHz (2 Fh mode) In TV-mode, the horizontal oscillator range is limited to - 5 % to + 10 % to prevent damage to the deflection stage. Also the maximum correction speed of the acquisition loop is limited to 2 µs per line in 1 Fh mode and 1 µs per line in 2 Fh mode. VGA mode For VGA mode, the horizontal oscillator can lock to incoming frequencies from 15 - 25 kHz in 1 Fh mode and from 30 - 50 kHz in 2 Fh mode. When not locked to an incoming HD pulse, the horizontal oscillator will run at its lowest frequency. When a HD pulse is offered, a frequency difference detector will adjust the centre frequency of the horizontal VCO with a maximum speed of 100 kHz/s to the incoming frequency, after which the phase detector of the acquisition loop takes over and keeps the VCO synchronised. Both horizontal and vertical synchronisation pulses have to be positive, so if synchronisation to different VGA standards with positive and negative sync pulses is needed, these sync signals have to be converted to positive polarity before feeding to the HD input pin 24 and VD input pin 23. Coincidence detector, Synchronisation Lock bit SL The coincidence detector detects whether the horizontal oscillator is synchronised with the incoming HD pulse, thus whether the acquisition loop is in-lock. The output is available by I²C bus, SL, and can be used to check whether the loop is working correct. Note that when the acquisition loop is disabled (see below, POC=1) SL is always 0. Free running mode By setting POC to 1, the acquisition loop is disabled and the horizontal oscillator will run at its free run frequency. The frequency is pending on the chosen mode (1 Fh or 2 Fh, see above). This frequency is stable because it is derived from the 12 MHz reference oscillator and is not disturbed by spurious signals on the HD input. This mode can be used for installation menus and also for stable blue mute when no valid signal is present. Because SL of the TDA 933X cannot be used to detect a valid input signal on the HD input, an external coincidence detector (e.g. IFI or SL from the TDA 9321 input processor) should be used to detect the presence of a valid signal. * PHI-2 detector and sandcastle As described, the acquisition PLL ("PHI-1 loop") synchronises the horizontal oscillator with the incoming HD pulses. The PHI-2 loop synchronises the deflection drive to obtain a stable horizontal position of the picture on the screen. This is necessary because due to beam current variations, the storage time of the line transistor varies. These storage time variations have to be compensated by adapting the phase of the horizontal drive, pin 8, to prevent horizontal shift of the picture on screen. The horizontal flyback pulse is used as reference for the horizontal screen position. The PHI-2 detector compares the horizontal flyback input pulse, pin 13, with the horizontal oscillator signal and keeps the phase relation fixed. This fixes the horizontal position on the screen. Using HSH (Horizontal SHift), a fixed phase offset can be programmed for PHI-2. In this way the horizontal position of the picture can be centred on the screen. Using HP (Horizontal Parallelogram), a phase offset change per line can be set. In this way, the phase offset changes from top to bottom of the screen. With this adjustment it is possible to set the vertical lines orthogonal to the horizontal lines (parallelogram correction) when the horizontal and vertical deflection yokes are not orthogonal. The time constant of the PHI-2 loop is integrated. The correction factor K is 0.5. The correction factor is defined as the amount of correction of a phase error between flyback pulse and horizontal oscillator. With K = 0.5, the phase error is halved each line period. 17 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 For horizontal geometry correction related to varying EHT voltage, a dynamic phase correction input (pin 14) is provided. This input can be driven by the standard used circuits to measure the EHT voltage decrease for the beam current limiting function. The EHT info voltage should drop when the EHT drops. The level for no correction is 4.0 Volts. Flyback input The horizontal flyback input (pin 13) has two functions. The flyback pulse on this pin is used as input signal for the PHI-2 loop but also determines the horizontal blanking. For optimal performance, the voltage level at which the blanking starts is chosen low (0.3 Volt, maximum blanking time due to wider base of the flyback pulse) while for loop stability the slicing level for the PHI-2 reference is chosen higher (4.0 Volts). The presence of a horizontal flyback pulse can be monitored by reading bit NHF (No Horizontal Flyback pulse). In this way, the µprocessor can monitor the correct working of the horizontal deflection stage. Sandcastle output/vertical guard input The sandcastle output pin 9 is combined with the vertical guard input. The sandcastle signal timing is related to the HD and VD input signals and the flyback pulse. Each horizontal line, a clamp pulse is generated. The delay from rising edge of the HD to the clamp pulse start is 5.4 µs for 1 Fh and 2.7 µs for 2 Fh. The level is 4.5 volt typical. The clamp pulse width is 3.5 µs for 1 Fh and 1.8 µs for 2 Fh. The clamp pulse timing and generation is comparable to the burstkey pulse of the PHI-1 loop of the input processor. The clamp pulse has the same timing as the internal used clamp pulse for the YUV and RGB inputs. When the flyback pulse on the flyback input pin rises above 0.3 Volt and starts the horizontal blanking, the level on the sandcastle pin rises to 2.5 volt. During vertical retrace, the output voltage is kept at 2.5 Volts for 12 - 25 lines, pending on the horizontal and vertical frequency mode. During scan, the output voltage is low. The sandcastle pulse can be used as clamp and blanking reference for display generating devices like TXT decoders and PIP processors. 4.5V 2.5V 0V Scan Vertical retrace Fig 2 : Sandcastle waveform. To prevent picture tube damage when the vertical deflection fails, a vertical guard function is added to this pin. During the vertical blanking, a current from 1 to 3 mA should be inserted to the pin during at least one line period. If such a pulse is not detected, failure of the vertical deflection circuit is assumed and the RGB outputs are blanked. The vertical deflection family TDA8350 TDA8350 - TDA8358 TDA8358 has a special guard output pin for this function. The vertical guard status can be read out via the bit NDF (No vertical DeFlection). The automatic blanking of RGB during vertical guard failure can be disabled by setting bit EVG (Enable Vertical Guard) to 0. EVG also has to be set to 0 when the vertical guard function is not used to prevent unwanted blanking of the RGB outputs. * H-output and slow start/stop The horizontal output is the driver pin for the line deflection. It is an open collector output. Under normal operating condition the duty cycle of the output pulse is 48.2 % off (Hout=high) / 51.8 % on (Hout=low). Note that all percentages used in this chapter are related to the final cycle time of the horizontal output which can be 1 Fh, 2 Fh or varying from 15 to 50 kHz in VGA mode pending on the chosen mode. When a horizontal flyback pulse is present at pin 13, Hout is always set high (Hout = off) irrespective the status of the output. In this way, switch-on of the line transistor during flyback time is prevented. The detection level is 0.3 Volt, so care must be taken to ensure that the level on this pin during scan is below 0.3 Volt under normal operating conditions. 18 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 Several provisions have been built-in to ease design and improve robustness of the deflection stage during switch-on and switch-off. A build in slow start/stop circuit ensures a smooth start/stop behaviour of the line deflection and protects the line output transistor. Switching on from stand-by via the stand-by bits STB1,0 During switch-on the horizontal output starts with a fixed off time (Hout=high) of 48.2 % while the on time (Hout=low) increases from 0% to 51.8 %. The on time increase from 0 % to 6.2 % lasts 50 ms, while the on time increase from 6.2 % to 51.8 % lasts 100 ms. These values lead in practice to a linear build-up of the EHT voltage in 150 ms while the horizontal frequency decreases from about double the final frequency to the final frequency. Some picture tubes e.g. versions with DAF gun, are sensitive for flash-over when the EHT voltage rises too fast from 75% to 100% of the nominal EHT value. For these picture tubes, the EHT increase from 75 % to 100 % can be slowed down by setting bit ESS (Extended Soft Start) to 1. The on-time increase from 39 % to 51.2 % is then extended to 1000 ms. (See Fig 3). Low power start-up To ease the design of the stand-by power supply, a special low power start-up facility is built-in. This low power start-up mode can be activated by supplying 5 Volts to pin 22 when no 8 Volt is present on supply pins 17 and 39. When 5 Volts is supplied, the horizontal output will start via a slow start procedure. The off time is fixed to 48.2 % and the on time is increased from 0 % to 12.5 % and remains running on this frequency. This horizontal drive should provide enough load for the power supply to wake it from stand-by mode and to build-up an 8 Volt supply using scan rectification of an auxiliary winding of the FBT for supplying pin 17 and 39 of the TDA 933X. When the 8 Volt supply is present and the POR has been cleared by reading the status bytes and successful calibration of the horizontal VCO is confirmed by checking NRF = 0, all I2C registers must be written including STB1,0 = 1 1. Then the on time of Hout is increased further from 12.5 % to 51.8 % according the slow start procedure as described above. When the H-out is not switched on from stand-by within 2 fields after POR is cleared, the on time is reduced from 12.5 % to 0% to switch-off safe the deflection when the 8 Volt is malfunctioning. When the 8 Volt is present and STB1,0 is set to 1 1, the 5 volt supply on pin 22 should be removed to ensure that H-out can be switched off completely. As long as the +5 Volt is present, H-out will remain running at 12.5 % on/ 48.2 % off when set to stand-by or when the +8 Volt is removed. This low power pin 22 only needs 3 mA supply current typical. In this way, the stand-by power supply design can be simplified because one voltage can be used for µprocessor and low power start-up while the power needed for the TDA 933X is only 15 mW (23 mW max.) compared to 400 mW (510 mW max.) and an 8 Volt supply when the TDA 933X is started up in normal mode. Switching off to stand-by using STB1,0 When switching-off via the stand by bits (STB1,0) the off time remains fixed on 48.2 % while the on time decreases from 51.2 % to 0 % in 43 ms. The on time decrease starts first after the vertical scan and vertical flyback is completed. During the first 37 ms of the switch-off time, the RGB outputs can be driven to obtain a fixed beam current for discharging the picture tube when bit FBC (Fixed Beam Current switch-off) is set to 1. The monitoring of the beam current is done via the Continuous Cathode Calibration loop which stabilises the cut-off and drive for the picture tube. (see chapter RGB processing and control for details). The visability of the picture tube discharge can be minimised by setting bit OSO (Overscan Switch Off) to 1. When switching to stand-by, after completion of the vertical scan and vertical flyback, the vertical deflection is kept fixed in overscan so the discharge takes place in the overscan. Switching off using mains switch Also provisions are available when the set is switched-off via the mains switch. An external circuit should monitor the supply voltage of the deflection. When this voltage decreases, pin 29 (Fixed Beam Current Switch Off) should be pulled high. From that moment, first the vertical scan and vertical flyback is completed. When FBC is set to 1, the RGB outputs are then driven to obtain a fixed beam current for discharge of the picture tube. When OSO is set to 1, the vertical deflection is kept fixed in overscan to minimise visability of the discharge. 19 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 H-out will keep running on nominal frequency, but because the deflection supply voltage decreases, the EHT will decrease proportionally. H-out will continue running till the supply voltage of the TDA 933X drops below the POR (Power On Reset) level. Both H-out and RGB drive will then be stopped. See also chapter RGB control, paragraph Fixed beam current discharge. 51.8 ESS=1 (% of nominal duty cycle) Ton 39 43 ms 6.2 50 1150 150 Time (msec) Fig 3 : Slow start / slow stop horizontal output. * Flash protection To protect the horizontal deflection stage during flash-over, the flash input pin 5 can be used. By pulling this pin above 2 Volts, the Hout is disabled immediately. When the voltage drops below 1.8 Volts, the horizontal output is started up again via the slow start procedure. This protection is hard wired and does not need intervention of the µprocessor. The status of the flash input can be read via status bit FLS, so the µprocessor can take additional action when needed. An external flash detection circuit has to be applied to use this function. The hysteresis of the input prevents unstable behaviour. For another protection facility, see paragraph "EHT compensation and overvoltage protection" in chapter "Vertical synchronisation/deflection and geometry (horizontal and vertical)". 20 HD 24 3* NRF 25 Sync control Auto VGA VGA DAC DAC5.0 F/V 25 21 1* 2* 3* X A 1: Block diagram: Horizontal and vertical synchronisation X X X X TDA 9332 TDA 9331 POC 14 Dynamic Phase compensation + Horizontal VCO VVGA 13.75 MHz NHF Horizontal VCO control + calibration HSH PHI-2 detector + filter VCAL 13 Hflyback Horizontal frequency select 12 Prescaler :1 1Fh :2 2Fh Blanking generation 1Fh or 2Fh LBM HBL HB3.0 RGB blank 1 STB0, STB1 XPR, PRD ESS,POR Slow start / stop Low power start-up 22 Low Power Start-up Supply :440 Horizontal timing signals Timing Burstkey Sandcastle Generator FLS 2V Direct stop H out 9 Flash 5 Protection 8 H out TDA9330/31/32 TDA9330/31/32 H TV Display processor Options TDA 9330 FAST Acquisition loop detector SL Loop filter + Limiter 12 MHz 21 Coincedence detector Frequency detector VCAL Reference oscillator 20 DAC out Philips Semiconductors Application Note AN98073 AN98073 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 2.2.2 Vertical synchronisation/deflection and geometry (horizontal & vertical) See also the related block diagram as well as the diagrams at the end of the report. We can distinguish the following main blocks, which will be described in more detail below: * Vertical divider system * Vertical sawtooth generator * Vertical geometry processor * Horizontal (E-W) geometry processor * EHT tracking + overvoltage protection * Vertical divider system The divider system uses a counter that delivers the timing for the vertical ramp generator in the geometry processor. The clock is derived from the horizontal line oscillator. The divider system synchronises on the VD pulse on pin 23 of the TDA933x. For optimum noise margin and reliable field detection, the edges of the VD pulse should be positioned on ¼ and ¾ of the line period referring to the rising edge of the HD pulse as reference. (see Fig 4) The timing of the vertical retrace for various modes will be discussed below and is also given in Fig 5 and Fig 6 at the end of this paragraph. Internally, a clock signal is generated running at the double frequency of the horizontal output. This signal is indicated in the figures as "CK2H" (ClocK 2 H-out) and is not related to the 2Fh frequency for double scan frequency. TV mode 1 Fh mode: When VD becomes high, the following actions are taken the first following clock pulse of the CK2H clock signal: - The vertical line counter is reset - Detection odd/even field by checking whether the CK2H clock pulse coincides with the horizontal blanking or not - Vertical blanking starts and lasts 22 / 22.5 lines for 50 Hz and 17 / 17.5 lines for 60 Hz signals for odd / even fields - A vertical saw reset is generated which discharges the vertical sawtooth capacitor to the reset level (2.3 Volt). The reset time is 14 lines for 50 Hz and 10 lines for 60 Hz. See Fig 5 and Fig 4. 2 Fh mode In this mode, two extra parameters can be set using VSR (Vertical Scan Reference) and VWT (Vertical WaiT). The bit VSR determines whether the rising edge or the falling edge of the VD pulse is used as reference for the field detection and VWT. The five bits register VWT sets the number of lines which the vertical sawtooth capacitor is kept to its reset level of 2.3 Volts and so determines at which line the vertical scan will start. The minimal number of lines is 8, putting a lower number in the VWT register will still generate 8 lines reset before the vertical scan is started. This function can be used to position the picture vertical correct for various modes of scan conversion boxes. When VD becomes high, the following actions are taken the first following clock pulse of the CK2H clock signal: - The vertical line counter is reset - Vertical blanking starts. The duration is related to the VWT setting. - The vertical saw reset is started. The actions below are executed on the timing, set by VSR: VSR = 0: The first clock pulse of the CK2H clock signal, following the falling edge of the VD pulse VSR = 1: The first clock pulse of the CK2H clock signal, following the rising edge of the VD pulse - Detection odd/even field by checking whether the CK2H clock pulse coincides with the horizontal blanking or not - Start counting the number of lines set by VWT before releasing the vertical saw reset and starting the vertical scan. The total reset time is pending on the reference used for VWT: For VSR = 0, the total reset time is the number of lines VD lasts plus the number of lines, set by VWT. For VSR = 1, the total reset time is equal to the number of lines, set by VWT. See Fig 6 and Fig 4. 22 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 VGA mode In this mode, always the rising edge of the VD pulse is used as reference for field detection and VWT irrespective of the setting of VSR. It is possible to use VWT to determine the start of vertical scan. When VD becomes high, the following actions are taken the first following clock pulse of the CK2H clock: - The vertical line counter is reset - Vertical blanking starts. The duration is related to the VWT setting. - The vertical amplitude is stabilised - Start counting the number of lines set by VWT before releasing the vertical saw reset and starting the vertical scan - After 2 additional clock pulses of the CK2H clock (one line) the vertical saw reset is started. The total reset time is therefore VWT minus one line. Also here, the minimal number of lines for VWT is 8. A lower number will still generate 8 lines reset before vertical scan is started. VD VD HD HD CK2H CK2H HBLNK HBLNK FIELD1 DETECTION FIELD1 DETECTION VD VD HD HD CK2H CK2H HBLNK HBLNK FIELD2 DETECTION FIELD2 DETECTION A) FALLING EDGE OF VD PULSE IS REFERENCE (VSR=0) B) RISING EDGE OF VD PULSE IS REFERENCE (VSR=1) Fig 4 : Field detection mechanism for VSR=0(A) and VSR=1(B) 23 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 24 25 Fig 5 : 1FH Timing diagram Vert. Blank AKB pulses Hd Vd 312 625 RESET LINE COUNTER 60Hz 50Hz L L R R G G B B L L R R G G B B 23 336 2ND FIELD 1ST FIELD 2ND FIELD 1ST FIELD TDA9330/31/32 TDA9330/31/32 H TV Display processor Reset Vert. Saw Vert. Blank AKB pulses CK2H Hd Vd Vert. Blank AKB pulses Hd = Ha Vd = Va Video from TDA9321H TDA9321H Reset Vert. Saw Vert. Blank AKB pulses CK2H Hd = Ha Vd = Va Video from TDA9321H TDA9321H Philips Semiconductors Application Note AN98073 AN98073 Fig 6 : 2FH Timing diagram 26 Vert Saw Measure pulse Reset Vert. Saw RESET LINE COUNTER = REFERENCE VWAIT REFERENCE VWAIT VWAIT=18 2FH VGA mode VWAIT=12 L L R 2FH TV mode (VSR=0) L R G R G B G B B 2ND FIELD 1ST FIELD TDA9330/31/32 TDA9330/31/32 H TV Display processor Vert. Blank AKB pulses CK2H Hd Vd Vert. Blank AKB pulses Hd Vd Reset Vert. Saw Vert. Blank AKB pulses CK2H Hd Vd RESET LINE COUNTER Philips Semiconductors Application Note AN98073 AN98073 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 Vertical frequency TV mode In TV mode, the vertical divider can be set to four different modes by the SVF (Set Vertical Frequency) and VFF (Vertical Free running Frequency) bit. These modes determine the setting for 1 Fv or 2 Fv mode and the free running frequency in these modes when no valid VD pulse is present SVF X X 0 0 1 1 VFF 0 1 0 1 0 1 1Fh / 2Fh 1Fh 1Fh 2Fh 2Fh 2Fh 2Fh Lines / field 312.5 262.5 625 525 312.5 262.5 Vertical frequency 50 Hz 60 Hz 50 Hz 60 Hz 100 Hz 120 Hz VGA mode In VGA mode, in free running mode the number of lines / field is fixed: 1 Fh VGA mode: 288 lines (55.7 Hz when also no HD is present and Hout runs at 16.05 kHz) 2 Fh VGA mode: 576 lines (55.7 Hz when also no HD is present and Hout runs at 32.1 kHz) The 1 Fh mode or 2 Fh mode is set by connecting pin 12 to ground (1 Fh) or leave pin 12 open (2 Fh). Catching ranges TV mode In TV-mode, the catching range is: 1 Fh, 1 Fv: 511.5 to 244 lines / field 2 Fh, 1 Fv: 1023 to 488 lines / field 2 Fh, 2 Fv: 511.5 to 244 lines / field (30.5 to 64 Hz) (30.5 to 64 Hz) (61 to 128 Hz) VGA mode For VGA, only the lines / field can be given. The vertical frequency is pending on the used horizontal frequency: 1 Fh VGA mode: 450 to 175 lines / field 2 Fh VGA mode: 900 to 350 lines / field The vertical frequency range is determined by the automatic amplitude stabilisation circuit and ranges from 50 to 90 Hz. Interlace Interlace can be switched on and off by I²C bus DL (De-interLace). To accommodate various TXT processors, also the choice can be made to delay the first or the second field with 0.5 line (reference is the VD pulse) using bit DIP (De-Interlace Phase). * Vertical sawtooth generator The vertical sawtooth generator delivers the reference signals for vertical and horizontal geometry processor. An accurate reference current (Iref) of 100µA is realised by means of an internal bandgap reference voltage (3.9V) and an external resistor (39k). This 100µA reference current is used to derive a 16 µA current to charge the external capacitor during vertical scan (1 Fh, 50 Hz). This circuitry ensures a very linear sawtooth (Usaw) that is used for further processing on vertical and horizontal (E-W). 27 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 * TV-mode The charge current for the sawtooth is automatically adapted pending on the input control bits SVF and VFF and the output control bit FSI (Field Synchronisation Information). FSI indicates whether the vertical frequency is 50/100 or 60/120 Hz and is only valid when a valid VD pulse is present and SL (Sync Lock) = 1, indicating lock of the acquisition loop to a valid HD input. See the table below: SVF X X 0 0 1 1 X X 0 0 1 1 VFF 0 1 0 1 0 1 X X X X X X FSI X X X X X X 0 1 0 1 0 1 1Fh / 2Fh 1Fh 1Fh 2Fh 2Fh 2Fh 2Fh 1Fh 1Fh 2Fh 2Fh 2Fh 2Fh SL 0 0 0 0 0 0 1 1 1 1 1 1 Charge current (µA) 16 19 16 19 32 38 16 19 16 19 32 38 Frequency (Hz) 50 60 50 60 100 120 50 60 50 60 100 120 Furthermore the charge current can be adjusted with the I²C bus control, VS (vertical slope). The range is +/- 20% should be used to compensate for tolerance of the external capacitor. When vertical zoom is applied, VS can be used to vary the position of the bottom part of the picture independent from the upper part (subtitle shift) The external capacitor is discharged during vertical retrace by the vertical divider system, see above. VGA mode To prevent adjustment of the vertical amplitude for various VGA frequencies, the peak to peak amplitude of the vertical sawtooth at the sawtooth capacitor is measured and the charge current is adjusted to keep the amplitude constant independent of the vertical frequency. The frequency range from this circuit is ranging from 50 to 90 Hz. * Vertical geometry processor The sawtooth signal that is derived from the sawtooth generator can be controlled by I²C bus. Control functions are: VA (Vertical Amplitude), VSH (Vertical SHift), SC (S-Correction), VX (Vertical eXpand (zoom), VSC(Vertical SCroll). To prevent picture damage, a built-in blanking functions blanks the RGB outputs for vertical overscan, larger than 105%. This function is active for both VX and VSC. The vertical geometry processor has a differential current output for a DC coupled vertical output stage (drive). It is important to notice that the TDA933X TDA933X is designed for use with a DC coupled output stage. This is the reason why a vertical linearity alignment is not necessary (and therefore not available). A half picture blanking function (service blanking, SBL) is available for vertical alignment (See chapter alignment) * Horizontal geometry processor (E-W drive) The horizontal geometry signal for E-W drive can control via the I²C bus the following functions: EW (EW-Width), PW (Parabola/Width), CP (Corner/Parabola) and TC (Trapezium Correction). The EW-width adjust range is such that linear zoom is possible on the picture size when used together with vertical expand (zoom). The horizontal geometry processor has a single-ended current output for E-W drive. 28 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 Corrections for different scan frequencies and zoom TV mode Once all vertical and horizontal parameters are aligned, the geometry settings do not have to be adapted when changing to other vertical or horizontal scan frequencies. Also when using zoom (horizontal and/or vertical) and vertical scroll (EW, VX, VSC) the geometry will remain correct without adapting the other geometry registers. Note: this geometry adaptation only works when the correct geometry alignment procedure (see chapter "Geometry alignment") has been followed. VGA mode Also in VGA mode the geometry settings will remain correct for different horizontal and vertical frequencies. The horizontal geometry currents are proportionally adapted to the horizontal VCO frequency for this purpose. * EHT tracking + overvoltage protection Both the vertical and the E-W drive can be modulated for EHT compensation. This tracking makes the picture size independent of EHT variations due to the beam current. The compensation range is -5 to +5 % and is fixed for the vertical deflection. Therefore the circuit should be designed for correct tracking of the vertical amplitude. The horizontal compensation can be matched to the vertical compensation by setting HCS. The horizontal compensation range can be set from 0 to +/-7%. A second function of this pin is for overvoltage protection, XPR (X-ray PRotection). XPR is set to "one" when the voltage on the pin exceeds 3.9 Volts and can be read by I²C bus. The bit is internally latched and will only be cleared when XPR is read after the voltage at pin 4 has dropped below 3.9 Volts. This ensures that the µprocessor can monitor a short exceeding of the 3.9 Volt level. It is possible to switch the horizontal output automatically off via slow stop for XPR = 1 when PRD (PRotection Detection mode) is set to 1. When XPR becomes 1, the vertical scan is completed and after the vertical retrace the H-out is switched off via the slow stop procedure and the IC is set in stand-by mode. The µprocessor can check XPR and decide whether to start-up the set again or to generate an error message (e.g. blinking led). 29 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 30 VD Vertical sawtooth Reference current 31 23 15 16 FSI Horizontal timing signal VGA DL, DIP FSI SVF, VFF VSR, VWT Vertical divider VS,VSC VSD,OSO Vertical sawtooth generator Vertical Amplitude stabilistion 1* HCS +/-5% +/-0 - +/-7% EW geometry processor EW,EP CP,TC EW tracking + sensitivity Vertical tracking VA,VX VSH,SC SBL Vertical geometry processor & XPR RGB blank 3 Hout Slowstart & Stop 3 4 1 EW drive EHT/Overvoltage Vert. drive pos. Vert. drive neg. TDA9330/31/32 TDA9330/31/32 H TV Display processor A 2: Block diagram: Geometry on vertical and E-W drive pin numbers according QFP44 QFP44 1* Only for versions with VGA option (TDA9331/TDA9332 TDA9331/TDA9332) PRD Overvoltage detector RGB blank 2 2 Philips Semiconductors Application Note AN98073 AN98073 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 2.2.3 RGB processing and control See also the related block diagram as well as the diagrams at the end of the report. This paragraph can be divided into: -YUV/RGB selection -RGB-control 2.2.3.1 YUV/RGB selection The main blocks are: - YUV/RGB 1 insertion and selection - Y, U and V signal processing. - RGB-adder +clamps - Contrast control - Black stretcher - Blue stretcher - RGB2 signal selection · Y, R-Y, B-Y/RGB 1 insertion and selection The luminance and colour difference input signals should be AC coupled to the input pins. These input signals are internally clamped and supplied to the YUV selection circuit. By means of the I²C bus bit GAI an additional 10 dB amplification can be selected. For RGB 1 insertion, the RGB signals should be AC coupled to the input pins where they are internally clamped. These RGB inputs are meant as external (SCART) inputs in 1Fh-mode and as VGA inputs in 2Fh mode. The RGB1 insertion signals are converted to YUV signals by means of a RGB/YUV converter. The converter uses the inverse PAL matrix, so for correct colour reproduction the PAL matrix must be selected in the Y, B-Y and R-Y processing block (see also related paragraph). The YUV signal after conversion is supplied to the YUV source selector. The YUV Source selector is controlled by hardware by means of the RGB1 insertion input signal BL1, (by applying an external voltage at this pin) and is designed for fast switching. The switching using BL1 can be enabled via the I²C bus by bit Insertion Enabled 1 (IE1). By means of the IN1 bit the RGB1 insertion pin status can be sensed. The status is only sensed during vertical retrace, so OSD insertion of descramblers will not set the IN1 bit. The RGB 1 insertion inputs are linear (video) inputs. 32 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 *Y, B-Y and R-Y signal processing/matrixing The luminance signal is supplied to a black stretcher circuit. This circuit, which is only operational during line scan, extends the grey signal level towards the actual black level (i.e. actual black level is measured during burstkey). The amount of extension is dependent upon the difference between actual black level and the darkest part of the incoming video signal; it is thus dependent upon the IRE value of the video signal. The darkest part of the video signal is registered on an internal-capacitor. For the black stretcher input/output characteristic, see the device specification. The black stretcher can be switched on/off via the I2C bus (BKS). The black stretcher is fully integrated so the black stretcher time constant is fixed. The saturation of the R-Y and B-Y signals is controlled via the I²C bus (SAT) The control range is minimal 52dB with a 6dB (minimum) reserve above nominal saturation level , refer also to the device specification. The colour matrix can be controlled via the I²C bus bits (MAT) and (MUS). With the MAT -bit the PAL/SECAM matrix or NTSC matrix can be selected. With the MUS -bit selection of the Japanese NTSC matrix or USA NTSC matrix can be made. In Fig 7 the three matrices are given (see device specification). R - Y: 1.14 90 O R - Y: 1.59 95 O B - Y: 2.03 G - Y: 0.70 236 O R - Y: 1.53 B - Y: 2.03 0O 99 O B - Y: 2.20 0O -1 O G - Y: 0.70 223O G - Y: 0.61 240O Fig 7 : Matrix options After the R-Y and B-Y processing the signals are added with the luminance signal in order to generate the internal RGB signals. At the same time a clamping action on the internal RGB-signals takes place. Note: When using the RGB1 input, the PAL matrix must be selected to get correct colour reproduction. The matrix, used to convert the RGB signals at RGB1 to YUV for internal processing is inverse to the PAL matrix. *Contrast control Contrast can be controlled for - The internal video signal coming from the YUV-outputs of the TDA9321 TDA9321 (HIP) or from the YUV outputs of a scan conversion box (100Hz converter, progressive scan converter) or PAL plus decoder. - RGB signals inserted via the RGB1 insertion inputs. Contrast control has no influence on the second RGB insertion inputs which will be discussed later on in this chapter. More about contrast will be given in the paragraph "RGB-controls", in this paragraph an overview of all the controls are given The blue back, which can be activated by the I2C bit EBB, is inserted at the contrast control function. When EBB is set to 1, a blue screen is inserted. This function can be used for example when no valid input signal is available, which usually is indicated by the coincidence detector of the input processor part. * Blue stretcher The standard blue stretcher of the TDA993X TDA993X can be activated by the I2C bit BLS. The blue stretcher reduces the R- and Gsignals by 14% whenever the video signal exceeds a threshold level of 80%. 33 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 B-slope 100% R/G slope 86% Threshold level of 80% Fig 8 : blue stretcher When adjusting the white point be sure that the blue stretcher is inactive. In principal all features should be switched off during white point adjustments. *The second RGB input This second RGB inputs are specially meant to insert teletext (TXT) or OSD signals. Before the RGB signal selection the RGB signals are clamped to a similar DC level during burstkey period. Selection is controlled by the RGB insertion input switch. Fast insertion on the second RGB inputs is made active/inactive via the I²C bus (IE2). With the I2C bit IN2 the status of the insertion switch input can be sensed. Two operating modes can be selected for the fast blanking pin 38 via I2C bit OBL: - Normal fast RGB insertion 2 ( R2IN G2IN B2IN ) (OBL = 0) - A mixture of both signal sources (the blender function), i.e. R2IN, G2IN, B2IN with YUV or RGB1 (OBL = 1). The normal fast insertion via the second RGB inputs is similar as described with the first RGB insertion inputs. If the blender function is selected then the voltage at the second RGB insertion input determines the amount of fading between the internal signal and the second RGB signals. In chapter "Application remarks per functional block and per pin" paragraph "RGB output and input circuit", pin 38 the blender characteristic is given (Fig 22). The Blender input has been optimised on the blender output characteristic of the SAA5800 SAA5800 (µprocessor/OSD/teletext processor). 34 2.2.3.2 RGB-control 35 A 3: Block diagram: YUV/RGB processing. BI1 GI1 RI1 BL1 LUMIN UIN VIN 32 31 30 33 28 27 26 U V RGB YUV Clamps Y Input GAI V1 U1 Y1 select1 YUV IN1 IE1 U V Y Saturation control matrix MUS MAT BKS black stretch U V SAT(6bit) B-Y Y' G-Y R-Y RGB adder + clamps B G R BCL Contrast control B G R EBB CON(6bit) OBL IE2 Input clamps B R RGB G select blender IN2 Blue stretcher BLS Bint Gint Rint FBK 37 36 35 38 BI2 GI2 RI2 BL2 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 On page 43 the block diagram of the RGB-control is given.(see Fig A 4) *RGB processing/ output stage * Peak White Limiting / softclipper *Beam current limiting *RGB-outputs stages *Continuous Cathode Calibration (CCC). *Vg2 adjust window *Fixed beam current discharge. * RGB processing The selected RGB signals are via the I²C bus controlled on -contrast -brightness -RGB white-point adjust (one individual control per channel) Contrast can be adapted over a 20dB gain range (-14 dB to +6 dB) by means of the I²C function: CONTRAST: 00 -> 63. Nominal contrast setting (0 dB) is realised with I²C bus setting CONTRAST = 44. For brightness, a change of DC-level of ± 1 V at RGBOUTPUT (w r t nominal) is possible for a change in I²C bus command (BRIGHTNESS: 00 -> 63). For nominal brightness (Brightness=32), the RGBOUTPUT is at black level which is equivalent to a ICATHODE of the CRT of 0mA. At the brightness function control signals used for the continuous cathode calibration circuit are inserted. For white-point adjustment, a ±3dB change in channel gain is possible for a change in I²C bus commands (WHITE POINT ADJUSTMENT RGB (WPA R,G,B): 00 -> 63). Nominal white-point adjustment settings are realised with I²C bus settings WPA R,G,B = 32. *Peak white limiting /softclipper The Peak White Limiting (PWL) of the TDA993X TDA993X is controlled by is the I2C control register PWL , which is a 4 bits register. This PWL function reacts on relative small white areas of the video signal. (for instance on inserted OSD-box). In front of the PWL function a low pass filter is added. The filter capacitor must be externally added, and allows adaptation of the filter characteristic. In order to have the same low pass filter characteristic of the peak white limiting for 1 Fh and a 2 Fh TV-sets the low pass filter is internally adapted to the selected 1 Fh or 2 Fh standard. This prevents that there is a difference between the PWL level 1Fh or 2Fh set. Under the condition of maximum contrast and a video inputs signal with a small white box , (small such that the average beam current function is not active) the minimum and maximum PWL attack level can be defined as: -Minimum PWL action (PWL setting 15) 85% of the Y-input signal applied at the input(s) of the TDA933X TDA933X -Maximum PWL action (PWL setting 00) 55% of the Y-input signal applied at the input(s) of the TDA933X TDA933X Besides a PWL function also a soft clipper is implemented. This soft clipper is only intended to clip high frequency peaks of the video signal. By I2C bits SC1,0 the soft clipper level can be adjusted to four levels with respect to the with respect to the peak white limiter level, set by PWL. Take notice that there is a small PWL-level change due to the soft clipper action. The soft clipper will reduce high frequency peaks with about 15 dB. *Beam current limiting The beam current limiting circuit or average beam current limiting (ABL) needs external circuitry to function. The voltage applied at the beam current pin must be a reflection of the amount of beam current through the picture tube. This function is a relative slow function and reduces the contrast and brightness of RGB signals. For the average beam current limiting: - contrast reduction begins when VBCL < 3.0V; - brightness reduction begins when VBCL < 2.0V. VBCL is normally 3.3V when average beam current limiting (and peak white limiting) are not active. The contrast and/or brightness reduction of the RGBOUT is proportional to the voltage decrease on the BCL pin. 36 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 * RGB output stages. Before discussing the 2-point black current loop stabilisation or continuous cathode calibration loop (CCC-loop) it is perhaps better to discuss the RGB-output stages first. Because besides that at this function the H- and V-blanking are inserted, the DC-levels of the blanking are 0.5V below nominal black level of the video signal, also several DC-levels are inserted at the RGB-outputs. These levels are used as measuring lines for the CCC-loop. (see Fig 9). At the end of the vertical blanking ( line 18,19,20,21 for 1 Fh, 50 Hz) the measuring lines for (CCC)loop can be observed The exact position of the measuring lines for various modes can be found in Fig 5 and Fig 6 in chapter "Vertical synchronisation/deflection and geometry (horizontal & vertical)". These measuring pulses have three DC-levels: -A DC-level of -0.1V with respect to nominal black level during the leakage measurement (LO). This level is chosen so that it lies close to the black level in order to have an accurate measurement close to cut off voltage of the picture tube. -A pulse of +0,25V with respect to nominal black level, which corresponds with a cathode current of 8æA -A pulse of +0,38V above nominal black level which corresponds with a cathode current of 20æA The pulse-levels of +0.25V and +0.38V can only be seen measured on alternating fields In the next paragraph CCC-loop will be described LO LR LG LB +0.25V 0V Nominal Black level -0.1V Blanking -0.5V DC-levels of R-output during the black current measurement pulse Field n +0.38V 0V Nominal Black level -0.1V Blanking -0.5V DC-levels of R-output during the cathode drive current measurement pulse Field n +1 Fig 9 : DC-level at RGB outputs Important to tell is that the RGB blanking level tracks with the DC level of the black current measurement pulses. The total video signal (except the measuring pulses for the CCC-loop) can be blanked by activating the I2C function RBL (RGB blanking). The RGB output stages supply the buffered RGB signals to pins 40, 41and 42 respectively. 37 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 * Continuous Cathode Calibration (CCC) The Continuous Cathode Calibration (CCC) loop (or two point stabilisation loop) is an auto-tuning loop which stabilises the black level (offset) as well as the cathode drive level (gain) of each gun of the CRT sequentially and independently on alternating fields. The benefit of the CCC-loop can be best explained by the figure below. no stabilisation Ik gain spread offset one point stabilisation R V Ro V Ro black current measurement pulse -no offset compensation -gain spread R Ik gain spread Ik two point stabilisation R V Ro black current measurement pulse -gain spread cathode drive current measurement pulse A B C Fig 10 : CCC-loop correction mechanisms The graphs show the cathode current (IK) as function of one of the three video output signals (in this case the red output) of the TDA933x. In case of no stabilisation, the transfer characteristic changes as function of temperature and ageing of the tube. This results in an offset and gain error , see graph A. An one point stabilisation corrects for offset variations (graph B) however with the CCC-loop both offset and gain spread are compensated as given in graph C. The CCC-loop can be divided into two loops: -a black level stabilisation loop (cut -off compensation) -a cathode drive stabilisation loop. (gain compensation) Besides these two loops a leakage current compensation loop is present. This loop compensates the total offset current of the three cathodes of the picture tube and the offset of the three RGBamplifiers. The leakage current compensation range is about ñ100µA. Leakage measurement and compensation occurs every field. 38 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 Rfeedback TDA933x 40/41/42 RGB RGB-outputs Dr,Dg,Db Rdrive Rcutoff Br,Bg,Bb Vref REF 20 uA Drive current measure ment Black current measure ment REF 8uA TDA61XX TDA61XX + Dr,Dg,Db= drive correction signals Br,Bg,Bb= black offset correction signals Field switch 10Kohm 44 Black current input Fig 11 : Basic application of the CCC-loop with the TDA61XX TDA61XX In Fig 11 basic application of the CCC-loop with RGB amplifiers is given. In this figure the main two loops of black level stabilisation and cathode drive stabilisation are shown. The two loops are being stabilised on alternating fields by means of a field switch. The main difference of the two loops is: During black level stabilisation internal black level clamps ensure that the DC-levels at RGB-outputs are independently and sequentially changed so that always 8µA flows to the black current input (pin 44). during the 3 measurement lines (LR,LG,LB) for the black current offset levels. The black current offset correction signals are stored internally. During the cathode drive current stabilisation, internal multipliers ensure that the cathode drive level for the three guns of the CRT are independently and sequentially stabilised so that 20µA feedback current flows to the black current input (pin 44) during the 3 measurement lines (LR,LG,LB) for the drive levels. The correction for the drive signals are stored internally. The drive levels at the three cathodes of the tube are always adjusted by the CCC-loop such that the feedback current is 20æA This means that the gain of the RGB-amplifier, e.g. TDA61XX TDA61XX family, is NOT determining the drive level to the CRT anymore. In order to change the cathode levels at the picture tube four I2C bits are added CL3.0 Changing the cathode level at the picture tube is achieved in the following way: The CL3.0 bits vary the amplitude of the RGB channels together of the internal measurement lines generated in a programmable pulse generator. During the 3 measurement lines (LR,LG,LB) these levels are inserted on the RGB video signals. 39 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 TDA933X TDA933X RGB 40,41,42 WPA RGB CL3,2,1,0 programmable RGB-ouputs measuring pulse level Br,Bg,Bb Dr,Dg,Db generator LR LG LB Field switch REF 20 uA Drive current measure ment Black current measure ment REF 8uA Field switch 44 Black current Dr,Dg,Db= drive correction signals Br,Bg,Bb= black offset correction signals input Fig 12 : Main blocks of the CCC-loop The drive correction signals (Dr, Dg, Db) will change the gain of the multipliers such that internal generated measurement pulse give a drive current measurement line at the cathode of the CRT corresponding with a current of 20æA. This 20æA current will be fed back to the black current input pin 44. The drive correction signals(Dr,Dg,Db) will be stored internally so that, after the 3 measurement-lines(LR,LG,LB), the actual RGB-video signals will have the same multiplication factor as determined during the drive current measurement pulses. The same procedure takes place during black current measurement except now the measurement lines are adapted such that a 8æA cathode current is measured by adding the offset correction signals (Br, Bg , Bb) to the RGB-signals By means of the field switch the programmable measurement line level generator switches the internal measurement line level corresponding with a 20æA cathode to a internal level corresponding with a 8æA cathode current. The field switch is not synchronised with odd / even fields. Changing the WPA RGB registers works on the same way as changing the CL3.0 bits except this three registers react on each individual RGB signal where the CL3.0 bits react on all three RGB-signals together. So when changing the WPA RGB registers the internal generated measurement lines are adapted at the input of the CCCmultiplier the CCC-loop adjust itself so that the black current measurement lines at the black current input (pin 44) are constant (8æA and 20æA). 40 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 Start up behaviour of the CCC-loop. After H-out is released the RGB-outputs are blanked and the CCC-loop is direct active, so from the start the 250mV and 380mV measuring pulses are present at the RGB-outputs. The cathodes of the picture tube are driven by the 250mV and 380mV measuring lines but due to the fact that the tube is cold (heater voltage is just applied, emission is very low) the corresponding 8µA and 20æA are not measured at the black current input so the gain as well as the offset is set to maximum by the CCC-loop what results in the fact that the CCC-loop gets out of range. This means that the amplitude of the 3 measuring lines is maximum at the RGB outputs. (actual scan remains at blanking level). After 7 to 15 seconds, the heater has warmed up the cathodes to generate enough emission. At that moment the CCC-loop starts to measure 8µA and 20æA at the black current input pin and at the same time the I2C Black current loop failure sense bit BCF becomes zero, at which moment the RGB-outputs will be released. For applications without a picture tube the CCC-loop can be switched off by means of the I2C control bit AKB (Auto Kine Biasing). In case AKB is switched off the RGB blanking and WPA R,G,B registers are disabled. In principal there is no difference in working for the CCC-loop in 1 Fh or 2 Fh mode. In both modes, the three measuring lines R, G and B are generated, each lasting one line period. (See Fig 9, page 37) Each alternate field the cut-off level (8 µA) or the drive level (20 µA) is measured and adjusted. The only difference is the timing of the internal measurement window of loop. For 1 Fh applications the measurement window starts at 50% of the measuring line and stops at 75% of the line. The measurement windows duration is 16µs For 2 Fh applications the measurement window starts 25% of the measuring line and stops at 75% of the line So the measurement window duration is also 16µs. Since the measuring window duration in 1 Fh and 2 Fh is equal all internal time constants of the CCC-loop are not dependent on 1 Fh or 2 Fh mode. *VG2 window Via the I2C bus VG2 can be aligned in production. The TDA933X TDA933X measures automatically the DC-level of the measuring lines of the cut-off loop of the CCC-loop. Internal, a window is defined of 2.5 Volt ± 100 mV. By turning the VG2 potentiometer the DC-level at the RGB-output will change. Whenever the lowest DC-level of the three RGB-outputs is within this window the VG2 is correctly aligned. Note that the lowest RGB output corresponds with the highest cut-off level at the cathode of the picture tube. "Within window" can be read back with the I2C output bit WBC. With the HBC-bit can be monitored whether the DC-level is above or below this window. The only restriction on this alignment method is that the VG2 window is fixed at a DC-level of 2.5V ±100mV. This implies that the RGB amplifiers should be designed to have the required highest (raster) cut-off level at their outputs at 2.5 Volt DC input level. The raster cut-off level is 10 - 12 Volt lower than the usual specified spot cut-off level. *Fixed beam current discharge This function " fixed beam current switch off" is used to discharge EHT voltage of picture tubes without bleeder when switching to standby or switching off the power supply. By means of the IIC function "Fixed Beam Current switch off" FBC=1 this function can be enabled. In combination with the IIC function Switch Off in vertical Overscan (bit OSO) can be determined whether the set is discharged in vertical overscan or during normal scan. There is in difference in behaviour of this function between switching to standby and switching off the power supply using the mains switch. So has pin 29 no function when the set is switched to standby (STB1,0). Therefore the function will be explained below for both switching off the power supply using the mains switch and for switching to stand-by using STB1,0. 41 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 Switching the power supply off using the mains switch: The power supply (the deflection supply) is "sensed" with an external circuit. The status of the power supply is fed to pin 29. A voltage below the 1.5V at this pin 29 means the supply works normally. When the supply voltage drops, pin 29 should be pulled above 1.5 Volt. This activates the fixed beam current function (provided bit FBC=1) and the following procedure is started: - The vertical scan is completed and vertical flyback is made - Inside pin 44 "the black current input" a current measurement of 1mA is activated. This current is adjusted and kept at 1 mA by adapting the brightness level of the RGB outputs. In other words: the brightness control discharges the tube, the discharge current of 1mA is measured via the black current input pin 44. - The discharge takes place during the overscan when OSO bit =1 which minimises the visability of the discharge on the screen of the picture tube. - The discharge begins when the voltage at pin 29 becomes high and ends when the supply voltage of the TDA933X TDA933X drops below the power on reset level (about 6.2V). When a power on reset is detected both H-out and the discharge current are disabled. Switching to stand-by using STB1,0: When switching the IC to Standby mode also discharge of the EHT voltage can take place when FBC=1. The procedure is the same as above (including the use of OSO) except: - Pin 29 has no function - A slow stop is made by the horizontal output. This means that the T-on of H-out decreases linear from nominal to zero in 43msec During the first 38ms of the slow stop time the fixed beam current switch off is activated in order to discharge the EHT voltage. See also chapter "Horizontal synchronisation", paragraph "H-output and slow start/stop" 42 Beam cur. lim./ Vert. guard 43 BCL 43 BCL & PWL field switch LR,LG,LB BINT GINT RINT WPR(6bit) WPG(6bit) WPB(6bit) CL3.00 CCC measurement pulse generator BCdis BRI(6bit) A 4: Block diagram: RGB-processing and control. LO pwl PWL & soft clipper 8µA AKB BCF CRT warm detector BCdis WBC HBC RGB blank? RGB blanking RBL Fixed beamcurrent discharge FBC VG2 window RGB output stages FBK 29 42 41 40 FBCSO Bout Gout Rout TDA9330/31/32 TDA9330/31/32 H TV Display processor Black current inp. 44 field switch 20µA offset correction CRT offset measurement LR,LG,LB CRT drive measurement drive correction Leakage compensator PWL(4bit) SC0,SC1 34 PWL Philips Semiconductors Application Note AN98073 AN98073 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 2.2.4 I²C bus description 2.2.4.1 Overview I²C bits For easy control, most functions of the TDA933X TDA933X are controlled via the I 2C bus: Sub Data bits Input functions1) addr. (write) (hex) D7 D6 D5 D4 RGB processing-1 00 MAT EBB SBL RBL RGB processing-2 01 MUS FBC OBL AKB Wide horizontal blanking 02 HBL 0 GAI STB0 Horizontal deflection 03 0 VSR FAST STB1 Vertical deflection 04 0 VFF LBM DIP Brightness BRI 05 0 0 A5 A4 Saturation SAT 06 0 0 A5 A4 Contrast CON 07 0 0 A5 A4 White point Red WPR 08 0 0 A5 A4 White point Green WPG 09 0 0 A5 A4 White point Blue WPB 0A 0 0 A5 A4 Peak White Limiting PWL 0B 0 0 SC1 SC0 Horizontal Shift HSH 0C 0 0 A5 A4 Horizontal Parallelogram HP 0D 0 0 A5 A4 E-W amplitude EW 0E 0 0 A5 A4 E-W parabola/width PW 0F 0 0 A5 A4 E-W corner parabola CP 10 0 0 A5 A4 E-W trapezium TC 11 0 0 A5 A4 E-W EHT hor.comp.sens. HCS 12 0 0 A5 A4 Vertical slope VS 13 0 0 A5 A4 Vertical amplitude VA 14 0 0 A5 A4 S-correction SC 15 0 0 A5 A4 Vertical shift VSH 16 0 0 A5 A4 Vertical Zoom VX 17 0 0 A5 A4 Vertical Scroll VSC 18 0 0 A5 A4 Vertical Wait VWT 19 0 0 0 A4 DAC output 3) DAC 1A 0 0 A5 A4 Data bits Output (read) Status byte 0 00 POR FSI SL XPR Status byte 1 01 ID3 ID2 ID1 ID0 Status byte 2 02 X X X X D3 BLS CL3 HB3 POC OSO A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 D2 BKS CL2 HB2 PRD SVF A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 D1 IE1 CL1 HB1 VGA2) EVG A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 D0 IE2 CL0 HB0 ESS DL A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 NDF NHF X IN1 BCF X IN2 FLS X WBC NRF HBC Table 4 : Condition PHI-1 loop 1) 2) 3) Note: All not-used bits should be set to zero, for compatibility with future devices. Only available for TDA 9331 and 9332 Only available for TDA 9330 and 9332, for TDA9331 TDA9331 the DAC output is proportional to the horizontal frequency in VGA mode and set to minimal in TV mode. 44 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 For quick reference are all bits listed in alphabetical order in the two tables below. The bits are split up for control functions and analogue control.: The meaning of the different columns in the table are: Control bits table: CONTROL BIT FUNCTION REG BIT I/O MACRO FU The short name for the control bit A short functional description The register subadress in HEX. The bit number (D7.D0) in the register Input or Output, Input = control bit, Output = status bit The device macro, where the bit is related to: Sync: Horizontal and Vertical synchronisation Geo: Geometry (vertical & horizontal) and drive of vertical deflection RGB: RGB output, input and control Pow/Prot: Power and Protection control Idselect Type number identification Function class, the bits are divided in 5 classes: SU Start-Up, bit has to be set correct before switching on from stand-by. AL Alignment, bit(s) have to be aligned during production, the found values are set each time before switching on from stand-by SC Setmaker Control, bits which have to be controlled by the setmaker during operation for correct performance like PHI-l loop time constant, positive modulation, etc. UC User Control, bits which are normally accessible for the customer like contrast, brightness, etc. Analogue control: Most columns are identical. The deviating columns: STEPS RANGE The number of steps, available for this analogue function The control range of the analogue control. Alphabetic list of I2C control bits. CONTROL BIT AKB BCF BKS BLS DIP DL EBB ESS EVG FAST FBC FUNCTION Auto Kine Biasing, 0=enable black current stabilisation loop, 1=disable Black Current loop Failure, 1=loop is not stabilised BlacK Stretch mode, 1=on Blue Stretch mode, 1=on De-Interlace Phase, 0=delay 1st field 0.5 line (reference=VD) 1=delay 2nd field 0.5 line De-interLace, 1=de-interlace Enable Blue Back, 1=enable Extended Soft Start, 0=normal, 1=extended from 75-100% Enable Vertical Guard, 1=protection enabled FAST acquisition loop ("PHI-1"), 0=normal, 1=increased with 30% Fixed Beam Current switch-off, 0=switch-off with blanked RGB outputs, 1=switch-off with fixed beam current 45 REG BIT 02 4 I/O MACRO I RGB FU SU 01 00 00 04 2 2 3 4 O I I I RGB RGB RGB Sync SU UC SC SC 04 00 03 04 03 0 6 0 1 5 I I I I I Sync RGB Sync Pow/Prot Sync SC SC SU SU SC 01 6 I RGB SC Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor CONTROL BIT FLS FSI GAI HBC HBL ID3.0 IE1 / IE2 IN1 IN2 LBM MAT MUS NDF NHF NRF OBL OSO POC POR PRD RBL SBL SC1.0 SL STB1,0 SVF VFF VSR VGA WBC XPR Application Note AN98073 AN98073 FUNCTION FLaSh-over indication, 1=flash-over detected Field Synchronisation Indication, 0=50/100Hz, 1=60/120Hz GAIn Y-input pin 28, 0 = normal (1 V bl-wh), 1 = high (0.32 V bl-wh) Help above/below Black Current loop window (see WBC), 0=below window, 1=above window Horizontal Blanking, 1=extended blanking on for display 4:3 on 16:9 tube Device Identification code Insertion Enable fast blanking, input 1, 2, 1=enabled Reflects the level on the fast blanking INput pin 33 of RGB1 0=low, 1=pin active (RGB insertion) Reflects the level on the fast blanking INput pin 38 of RGB2 0=low, 1=pin active (RGB insertion) Long Blanking Mode, 0=auto, 1=50 Hz blanking PAL/NTSC MATrix, 0=PAL, 1=NTSC matrix NTSC Matrix USA, 0=Japanese NTSC matrix, 1=USA NTSC matrix No vertical DeFlection guard output, 1=failure No Horizontal Flyback pulse present, 1=failure No ReFerence, 1=reference oscill. not locked to X-tal oscill OSD BLending function of BL2 pin 38 from RGB2, 0=normal fast blanking for OSD, 1=blending for OSD Overscan Switch Off, 1=switch off in vertical overscan Phi-One Control synchronisation mode, 1=loop switched off Power On Reset, 1=failure detected Over-voltage Protection Detection mode, 0=detection, 1=detection & slow stop H-out RGB BLanking, 1=outputs blanked Service BLanking, 1=active Soft Clipping level > peak white limiting level, 00=0%, 01=5%, 10=10%, 11=soft clipping off Sync in Lock, 1=acquisition-loop ("PHI-1") locked STand-By control, 00=stand-by, 11=on, 01,10=no action Set Vertical Frequency, 0=50/60 Hz, 1=100/120 Hz Vertical Free running Frequency, 0=50/100Hz, 1=60/120Hz Vertical Scan Reference, 0=falling edge VD pulse, 1=rising edge VD pulse VGA mode, 0=Fh fixed by internal reference, 1=multi-sync function switched on Window Black Current loop, 1=within window X-ray PRotection, 1=failure detected 46 REG 01 00 02 BIT 1 6 5 I/O O O I MACRO Pow/Prot Geo RGB FU SC SC SU 02 0 O RGB AL 02 7 I Sync SC 01 00 00 7.4 1,0 2 O I O DevSel RGB RGB SC SC SC 00 1 O RGB SC 04 00 01 5 7 7 I I I Sync RGB RGB SU SC SC 00 01 01 01 3 3 0 5 O O O I Pow/Prot Pow/Prot Pow/Prot RGB SC SC SC SU 04 00 00 03 3 3 7 2 I I O I Geo Sync Pow/Prot Pow/Prot SU SC SC SU 00 00 0B 4 5 5,4 I I I RGB Geo RGB SC AL SC 00 02 03 04 04 03 5 4 4 2 6 6 O I Sync Pow/Prot SC SC I I I Geo Geo Geo SC SC SU 03 1 I Sync SC 00 00 0 3 O O RGB Pow/Prot AL SC Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 Alphabetic listing of analogue I2C controls. The parameters in the table below are just rough indications and may change without notice. Please consult the TDA933X TDA933X data sheet (ref.[1]) for the most up-to-date values. CONTROL BITS BRI CL3.0 REG 05 01 BIT STEPS 5.0 63 3,2,1,0 16 RANGE - 1 . + 1 V1) 50 . 95 VBl-Wh MACRO RGB RGB FU UC AL 07 10 1A OE 02 5.0 5.0 5.0 5.0 3.0 63 63 63 63 16 RGB Geo Sync Geo Sync UC AL SC AL 12 5.0 63 10 .100 % (20dB) -43 . 0 % 0.3 . 4.0 V 100 . 65 % -2.03.+2.03 µs (1Fh) -1.01.+1.01 µs (2Fh) 0 . 9 %/V Geo SU HP FUNCTION BRIghtness Cathode drive Level, adjustment cathode drive amplitude CONtrast E_W Corner/Parabola Dig/Anal. Conv. Output E-W Width Horizontal Blanking position Horizont.Compensation Sensitivity Horiz. Parallelogram 0D 5.0 63 Sync AL HSH Horizontal Shift 0C 5.0 63 Sync AL PW PWL SAT SC TC VA VS VSC VSH VWT VX WPR,G,B E-W Parabola/Width Peak White Limiting SATuration S-Correction E-W Trapezium Corr. Vertical Amplitude Vertical Slope Vertical Scroll Vertical Shift Vertical WaiT Vertical zoom/eXpand White Point R,G and B 0F 0B 06 15 11 14 13 18 16 19 17 08,09,0A 5.0 3.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 4.0 5.0 5.0 63 16 63 63 63 63 63 63 63 233) 634) 63 -0.54.+0.54 µs (1Fh) -0.27.+0.27 µs (2Fh) -4.5 . +4.5 µs (1Fh) -2.25.+2.25 µs (2Fh) 0 . 22 % 0.55 . 0.85 VBl-Wh Y 0 . 300 % 0 . 30 % -5 . +5 % 80 . 120 %2) -20 . +20 % -18 . +19 % -5 . +5 % 8 . 31 lines 75 . 138 % -50 . +50 %5) Geo RGB RGB Geo Geo Geo Geo Geo Geo Geo Geo RGB AL SC UC AL AL AL AL UC AL SU UC AL CON CP DAC EW HB3.0 HCS Note: 1) 2) 3) 4) 5) Relative variation with respect to the measuring pulses at RGBOUT. Valid when SC=00HEX 00HEX, for SC=3FHEX the range is 86 . 112%. 00 - 08 HEX have default 8 lines delay, 09 - 1F HEX from 9 - 31 lines delay Neutral position for VX is 19HEX 19HEX = 25DEC 25DEC. Nominal setting=1FHEX. 47 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 The TDA933X TDA933X needs only two I²C-bus pins (10=SCL and 11=SDA) to read and write all its functions: · Write slave address: 8CHEX : A6 A5 A4 A3 A2 A1 A0 R/W : 10001100 · Read slave address: 8DHEX : A6 A5 A4 A3 A2 A1 A0 R/W : 10001101 For I²C-bus write-transmissions the TDA933X TDA933X has automatic sub-address increment, so multiple data bytes can be sent in one transmission. acknowledge acknowledge acknowledge from slave from slave from slave Start Slave address 0 Ack R/W = write Sub address Ack Data Byte first sub-address = destination of first data byte Ack Stop multiple data bytes, each acknowledged by slave Reading the three status bytes is done without sub-addressing. After receiving the I²C-bus read address, the TDA933X TDA933X always starts with status byte 0. acknowledge from slave Start Slave address 1 Ack R/W=read acknowledge from master Status byte 0 Ack No acknowledge from master (just clock pulse) Status byte 2 Nack Stop Read 1, 2 or 3 status bytes 2.2.4.2 I²C-bus start-up procedure. The TDA933X TDA933X has many alignment-free internal circuits that are calibrated with the frequency of the reference Xtal oscillator. To ensure correct register content at start-up, the following start-up procedure should be implemented in the software: ·1 ·2 ·3 ·4 ·5 Keep reading the I²C-bus status bytes, until POR = 0 Set STB1,0 = 0 0 Write all subadresses up till including 1AHEX Keep reading I2C-bus status bytes till NRF = 0 Set STB1,0 = 1 1 Before the horizontal drive output can become active, all sub-address bytes 00HEX 00HEX to 1AHEX must be loaded. Registers or register bits, not available or defined in certain versions, must be loaded with zero's for (future) compatibility. After the last sub-address is loaded, the oscillator is calibrated. After successful calibration, NRF is set 0. Each time before the sub-address bytes are refreshed, the status bytes must be read. If POR=1 then the start-up procedure must be carried out to restart the IC. Not following this procedure may result in undesired conditions after power-up or a power dip (e.g. incorrect horizontal line frequency). 48 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 The following paragraphs describes the function of the I2C control bits. Mentioned pin numbers refer to the QFP package. 2.2.4.3 Synchronisation part. Input control bits DIP : De-Interlace Phase Reg: 04 Bit: 4 Fu: SC When using de-interlacing (see DL below) with DIP the field can be selected which is delayed for 0.5 line. The vertical input pulse VD serves as reference. In this way, a wide variety of TXT processors can be interfaced. 0 = delay first field with 0.5 line 1 = delay second field with 0.5 line DL : De-interLace Reg: 04 Bit: 0 This can switch off the interlace, e.g. for TEXT applications. 0 = Interlace 1 = De-interlace ESS : Extended Soft Start Reg: 03 Bit: 0 Fu: SU The soft start gradually increases the "on"- time of the horizontal drive from 0 % to 52 % while the "off" time is kept fixed on 48 % (percentages related to the dutycycle in final situation). The EHT will be proportional to the horizontal drive frequency. To prevent flash-over in certain picture tubes, it is best to have a low speed EHT build-up from 75% to 100%. This can be achieved by slowing down the "on" - time increase during the last part. 0 = normal "on"-time increase (156 ms) 1 = normal "on"-time increase to 39% (120 ms), slow increase to 52% (1030 ms) FAST : FAST acquisition loop time constant Reg: 03 Bit: 5 Fu: SC The acquisition loop ("PHI-1") time constant is integrated. For flexibility, the speed can be increased by 30% for quick settling of HD disturbances (pending on applied scan converter, applied input processor and/or input source e.g. VCR). 0 = Normal time constant 1 = Loop speed increased with 30 % HBL : Wider Horizontal Blanking Reg: 02 Bit: 7 Fu: SC Widens the horizontal blanking for well defined edges with underscan. 0 = Normal blanking using horizontal flyback pulse 1 = Wider blanking to obtain well defined left and right edges e.g. for 4:3 picture and 16:9 screen size. LBM : Long Blanking Mode Reg: 04 Bit: 5 Fu: SU This bit sets the 60 Hz vertical blanking interval to the 50 Hz standard. In certain 50/60 Hz applications this can simplify the vertical output stages, regarding the maximum vertical retrace time. With a fixed 50 Hz blanking time, visible vertical retrace lines with 60 Hz can be avoided when the vertical retrace time is too long (> 1 ms). LBM is only working in 1 Fh mode! 0 = Blanking adapted to standard (50 or 60 Hz) 1 = Fixed blanking according 50 Hz standard 49 Fu: SC Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 POC : "Phi-One" (acquisition loop) Control Reg: 00 Bit: 3 Fu: SC When this bit is switched to high, the acquisition-loop is switched off completely. In this mode very stable OSD or TEXT can be displayed, independent of the selected source. Useful for e.g. installation menu's, blue mute. It is also possible to measure the free running frequency in this way. Note: if POC=1 than SL =0 0 = Synchronisation active 1 = Synchronisation not active VGA : Video Graphics Adapter mode Reg: 03 Bit: 1 Fu: SC In normal mode, horizontal and vertical deflection are optimised for displaying signals related to the TV-norm. In VGA mode, the horizontal frequency range is increased (15 to 25 kHz 1Fh, 30 to 50 kHz 2Fh), the allowed number/lines per field is adapted and the vertical amplitude is kept constant independent of the vertical frequency. (Bit only available in TDA 9331/2) 0 = normal mode 1 = VGA mode Output control bit: SL : Sync Lock Reg: 00 Bit: 5 Lock indication of acquisition loop ("Phi-1") to incoming HD pulse: 0 = Not locked 1 = Locked to the incoming HD pulse Fu: SC Analogue controls: DAC: Digital to Analogue Convertor output Reg: 1A Bit: 5.0 Fu: SC This general purpose DAC output can be used for alignment or other DC controlled functions. (only available in TDA 9330/2) Nr. of steps: 63 Range: 0.3 . 4.0 Volt HB3.0: Wide Horizontal Blanking position Reg: 02 Bit: 3.0 Fu: AL When switching on the wide horizontal blanking using HBL, the exact position of the edges can be adjusted with HB3.0. Nr. of steps: 16 Range: - 2.03 . +2.03 µs (1 Fh) - 1.015 . +1.015 µs (2 Fh) HP: Horizontal Parallelogram correction Reg: 0D Bit: 5.0 Fu: SC When the horizontal and vertical deflection yokes are not orthogonal, the vertical lines can be set in correct position. Neutral position: 1F HEX Nr. of steps: 63 Range: - 0.54 . + 0.54 µs (1 Fh mode) - 0.27 . + 0.27 µs (2 Fh mode) HSH: Horizontal Shift Reg: 0C Bit: 5.0 Adjusts the horizontal position of the picture on the screen Nr. of steps: 63 Range: - 4.5 . + 4.5 µs (1 Fh mode) - 2.25 . + 2.25 µs (2 Fh mode) 50 Fu: AL Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 2.2.4.4 Geometry Input control bits: OSO : Overscan Switch-Off Reg: 04 Bit: 3 Fu: SU Enable switch-off in vertical overscan. When switching to stand-by, the vertical deflection is kept high while during switch-off the picture tube is discharged with a fixed current so the white drive is less visible 0 = Switch-off undefined 1 = Enable switch-off in vertical overscan function SBL : Service Blanking Reg: 00 Bit: 5 Fu: AL This bit blanks the bottom half of the picture, starting exactly in the middle of the vertical scan (deflection currents are zero). This bit is intended be used to align the vertical parameter VS in order to compensate for component tolerances. See also the chapter about geometry alignment. 0 = No service blanking 1 = Service blanking active SVF : Set Vertical Frequency Reg: 04 Bit: 2 Fu: SU To control the vertical free running frequency independent from the horizontal frequency (1Fh or 2 Fh) the vertical frequency can be set to 1 Fv (50/60 Hz) or 2 Fv (100/120 Hz). In this way, also progressive scan can be easily applied. The vertical free running frequency (50/100 or 60/120 Hz) can be set using VFF (see below). 0 = 50 / 60 Hz 1 = 100 / 120 Hz VFF : Vertical Free running Frequency Reg: 04 Bit: 6 Fu: SC The vertical free running frequency can be set to 50/100 Hz or 60/120 Hz. The selection between 1 Fv (50/60 Hz) and 2 Fv (100/120 Hz) can be made using SVF (see above). 0 = 50/100 Hz 1 = 60/120 Hz VSR : Vertical Scan Reference Reg: 03 Bit: 6 Fu: SU It is possible to select whether the rising or falling edge from the VD pulse is used for the vertical reference. This increases the flexibility to interface with a variety of scan converters or picture improvement circuits. 0 = Falling edge VD pulse is vertical scan reference 1 = Rising edge VD pulse is vertical scan reference Output control bit: FSI : Field Synchronisation Information Reg: 00 Bit: 6 Fu: SC Indication of the field frequency of theVD pulse. Not valid in VGA mode. 1 Fv (50/60 Hz) or 2 Fv (100/120 Hz) is determined by the setting of SVF (see above) 0 = 50/100 Hz 1 = 60/120 Hz 51 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 Analogue controls: CP: E-W Corner Parabola Reg: 10 Bit: 5.0 Fu: AL Adjusts the top- and bottom curve of the vertical lines. Set CP in neutral position before starting alignment. Neutral position: 1F HEX. Nr. of steps: 63 Range: -21.5.+21.5 % (related to neutral position 1FHEX, -43 . 0 % related to 00HEX 00HEX) EW: E-W Width Reg: 0E Bit: 5.0 Fu: AL Adjusts the picture width. When all higher order terms (CP, PW, TC) are aligned, the geometry corrections will remain correct when changing the EW register for horizontal zoom. Nr. of steps: 63 Range: 65 . 100 % HCS : Horizontal Compensation Sensitivity Reg: 12 Bit: 5.0 Fu: SU Sets the EHT tracking sensitivity to modulate the E-W width using the information on pin 4. EHT tracking compensates picture size variations due to beam current variation. The vertical EHT tracking sensitivity is fixed (9 %/V). The circuit interfacing pin 4 should be designed for correct compensation of the vertical amplitude, the horizontal compensation can be matched using HCS. Nr. of steps: 63 Range: 0 . 9 %/V PW: E-W Parabola Width Adjusts the parabola correction. Nr. of steps: 63 Range: 0 . 22 % Reg: 0F Bit: 5.0 Fu: AL SC: Vertical S-Correction Adjusts the vertical S-correction. Nr. of steps: 63 Range: 0 . 30 % Reg: 15 Bit: 5.0 Fu: AL TC: E-W Trapezium Correction Reg: 11 Bit: 5.0 Fu: AL Adjusts the position of the vertical lines at the sides: can be bend inwards or outwards. The vertical lines remain straight. Set in neutral position before starting alignment. Neutral position: 1F HEX Nr. of steps: 63 Range: -5 . +5 % VA: Vertical Amplitude Reg: 14 Bit: 5.0 Fu: AL Adjusts vertical amplitude. Adjustment does affect all horizontal geometry corrections and also the vertical S-correction. Before using VA, first align VS and VSH. Do not use for vertical zoom because the overscan is not blanked! Nr. of steps: 63 Range: 80 . 120 % 52 Philips Semiconductors TDA9330/31/32 TDA9330/31/32 H TV Display processor Application Note AN98073 AN98073 VS: Vertical Slope Reg: 13 Bit: 5.0 Fu: AL Adjusts the vertical slope. This alignment is meant to compensate for spread on the value of the external sawtooth capacitor (major) and spread on the internal reference current source (minor). This is the first vertical alignment to execute in order to adjust the internal levels to exact nominal value. These nominal values are important to ensure that all derived correction waveforms (vertical S and horizontal geo) are correct. Use SBL (service blanking) for correct alignment. See also chapter geometry alignments. Nr. of steps: 63 Range: -20 . +20 % VSC: Vertical Scroll Reg: 18 Bit: 5.0 Fu: UC Can be used to scroll the picture vertical up and down. Works only when the vertical picture size is zoomed larger than 100 % using VX. In this way, the relevant part of the pic