TDA8007BC2 GSM11-11 80C51 TDA8007BHL/C2 LQFP48 ISO7816 TDA8007B FCE534 - Datasheet Archive

 

DATA SHEET TDA8007BC2 Double multiprotocol IC card interface Preliminary specification V1.5 File under Integrated Circuits, IC02

 

INTEGRATED CIRCUITS DATA SHEET TDA8007BC2 TDA8007BC2 Double multiprotocol IC card interface Preliminary specification V1.5 File under Integrated Circuits, IC02 2001 July 07 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 FEATURES · Control and communication through an 8-bit parallel interface, compatible with multiplexed or non-multiplexed memory access · Specific ISO UART with parallel access on I/O for automatic convention processing, variable baud rate through frequency or division ratio programming, error management at character level for T = 0, extra guard time register · 1 to 8 characters FIFO in reception mode · Parity error counter in reception mode and in transmission mode with automatic retransmission · Dual VCC generation (5 V ±5%, 65 mA (max.) or 3 V ±8%, 50 mA (max.)or 1.8V ±10%, 30mA (max) with controlled rise and fall times) · Dual cards clock generation (up to 10 MHz), with three times synchronous frequency doubling (fXTAL, fXTAL/2, fXTAL/4, fXTAL/8) · Cards clock STOP HIGH, clock STOP LOW or 1.25 MHz (from internal oscillator) for cards Power-down mode · Automatic activation and deactivation sequence through an independent sequencer · Supports the asynchronous protocols T = 0 and T = 1 in accordance with ISO 7816 and EMV · Versatile 24-bit time-out counter for Answer To Reset (ATR) and waiting times processing · Specific Elementary Time Unit (ETU) counter for Block Guard Time (BGT) (22 in T=1, 16 in T=0) · Supports synchronous cards · Current limitations in the event of short-circuit · Special circuitry for killing spikes during power-on/-off · Supply supervisor for power-on/-off reset · Step-up converter (supply voltage from 2.7 to 6 V), doubler, tripler or follower according to VCC and VDD · Additional I/O pin allowing use of the ISO UART for another analog interface (pin I/OAUX) · Additional interrupt pin allowing detection of level toggling on an external signal (pin INTAUX) · Fast and efficient swapping between the 3 cards due to separate buffering of parameters for each card · Chip select input allowing use of several devices in parallel and memory space paging · Enhanced ESD protections on card side [6 kV (min.)] · Software library for easy integration within the application · Power-down mode for reducing current consumption when no activity. APPLICATIONS · Multiple smart card readers for multiprotocol applications (EMV banking, digital pay TV, access control, etc.). GENERAL DESCRIPTION The TDA8007BC2 TDA8007BC2 is a cost effective card interface for dual smart card readers. Controlled through a parallel bus, it takes care of all ISO 7816, EMV and GSM11-11 GSM11-11 requirements. It may be interfaced to the P0/P2 ports of a 80C51 80C51 family microcontroller, and be addressed as a memory through MOVX instructions. It may also be addressed on a non-multiplexed 8-bit data bus, by means of address registers AD0, AD1, AD2 and AD3. The integrated ISO UART and the time-out counters allow easy use even at high baud rates with no real time constraints. Due to its chip select and external I/O and INT features, it greatly simplifies the realization of any number of cards readers. It gives the cards and the reader a very high level of security, due to its special hardware against ESD, short-circuiting, power failure, etc. Its integrated step-up converter allows operation within a supply voltage range of 2.7 to 6 V. (It may be supplied with a voltage higher than the IC's supply) 2001 July 07 2 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 A software library has been developed, taking care of all actions required for T = 0, T = 1 and synchronous protocols (see application reports). ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8007BHL/C2 TDA8007BHL/C2 2001 July 07 LQFP48 LQFP48 DESCRIPTION plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm 3 VERSION SOT313-2 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD supply voltage 2.7 - 6 V VDDA supply voltage for the DC/DC converter VDD - 6 V IDD(pd) supply current in power-down mode VDD = 3.3 V; cards inactive; XTAL oscillator stopped - - 350 µA VDD = 3.3 V; cards active at VCC = 5 V; CLK stopped; XTAL oscillator stopped - - 3 mA IDD(sm) supply current in sleep mode cards powered at 5 V but clock stopped - - 5.5 mA IDD(om) supply current in operating mode VDD = 3.3 V; fXTAL = 20 MHz; VCC1 = VCC2 = 5 V; ICC1 + ICC2 = 80 mA - - 315 mA VCC output card supply voltage 5.0 5.25 V 4.6 - 5.4 V 2.78 - 3.22 V with 24 nC dynamic loads on 200 nF capacitor (3 V card) 2.75 - 3.25 V including static loads (1.8 V card) 1.65 - 1.95 V with 12 nC dynamic loads on 200 nF capacitor (1.8 V card) 1.62 - 1.98 V operating; 5 V card - - 65 mA operating; 3 V card - - 50 mA operating; 1.8 V card - - 30 mA overload detection output card supply current 4.75 including static loads (3 V card) ICC including static loads (5 V card) with 40 nC dynamic loads on 200 nF capacitor (5 V card) - 100 - mA - - 80 mA ICC1 + ICC2 sum of both cards currents SR slew rate on VCC (rise and fall) 0.05 0.16 0.22 V/µs tdeact deactivation cycle duration - - 150 µs tact activation cycle duration - - 225 µs fxtal crystal frequency 4 - 27 MHz fop operating frequency 0 - 25 MHz Tamb ambient temperature -25 - +85 °C 2001 July 07 CL(max) = 300 nF external frequency applied to pin XTAL1 4 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 BLOCK DIAGRAM VDD handbook, full pagewidth GND 19 27 1 RSTOUT DELAY 48 VDDA 100 nF 220 nF SAP SAM 23 21 26 SUPPLY AND SUPERVISOR 220 nF SBP SBM 22 24 STEP-UP CONVERTER AGND 25 20 VUP 220 nF 22 nF 40 39 45 44 43 42 36 37 28 29 30 31 32 33 34 35 38 2 41 6 4 8 10 ISO7816 ISO7816 UART INTERFACE CONTROL INT ALE AD0 AD1 AD2 AD3 RD WR D0 D1 D2 D3 D4 D5 D6 D7 CS I/OAUX INTAUX 9 3 ANALOG DRIVERS AND SEQUENCERS TIME-OUT COUNTER 5 7 14 12 16 18 17 CLOCK CIRCUIT 11 13 15 C41 C81 CLK1 RST1 VCC1 I/O1 PRES1 GNDC1 C42 C82 CLK2 RST2 VCC2 I/O2 PRES2 GNDC2 INT OSC TDA8007B TDA8007B XTAL OSC 47 XTAL1 Fig.1 Block diagram. 2001 July 07 5 46 XTAL2 FCE534 FCE534 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 PINNING SYMBOL PIN DESCRIPTION RSTOUT 1 I/OAUX 2 open-drain output for resetting external chips input or output for an I/O line issued of an auxiliary smart card interface I/O1 3 data line to/from card 1 (ISO C7 contact) C81 4 auxiliary I/O for ISO C8 contact (synchronous cards for instance) for card 1 PRES1 5 card 1 presence contact input (active HIGH) C41 6 auxiliary I/O for ISO C4 contact (synchronous cards for instance) for card 1 GNDC1 7 ground for card 1 (must be connected to GND) CLK1 8 clock output to card 1 (ISO C3 contact) VCC1 9 card 1 supply output voltage (ISO C1 contact) RST1 10 card 1 reset output (ISO C2 contact) I/O2 11 data line to/from card 2 (ISO C7 contact) C82 12 auxiliary I/O for ISO C8 contact (synchronous cards for instance) for card 2 PRES2 13 card 2 presence contact input (active HIGH) C42 14 auxiliary I/O for ISO C4 contact (synchronous cards for instance) for card 2 GNDC2 15 ground for card 2 (must be connected to GND) CLK2 16 clock output to card 2 (ISO C3 contact) VCC2 17 card 2 supply output voltage (ISO C1 contact) RST2 18 card 2 reset output (ISO C2 contact) GND 19 ground connection VUP 20 output of the step-up converter (connect a low ESR 220nF to AGND) SAP 21 contact 1 for the step-up converter (connect a low ESR 220 nF capacitor between pins SAP and SAM) SBP 22 contact 3 for the step-up converter (connect a low ESR 220 nF capacitor between pins SBP and SBM) VDDA 23 positive analog supply voltage for the step-up converter (may be higher than VDD) Decouple with a good quality capacitor to GND SBM 24 contact 4 for the step-up converter (connect a low ESR 220 nF capacitor between pins SBP and SBM) AGND 25 ground connection for the step-up converter SAM 26 contact 2 for the step-up converter (connect a low ESR 220 nF capacitor between pins SAP and SAM) VDD 27 positive supply voltage Decouple with a good quality capacitor to GND D0 28 data 0 or add 0 D1 29 data 1 or add 1 D2 30 data 2 or add 2 D3 31 data 3 or add 3 D4 32 data 4 or add 4 D5 33 data 5 or add 5 D6 34 data 6 or add 6 D7 35 data 7 or add 7 RD 36 read selection signal (read or write in non-multiplexed configuration) 2001 July 07 6 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface SYMBOL PIN TDA8007BC2 TDA8007BC2 DESCRIPTION WR 37 write selection signal (enable in case of non-multiplexed configuration) CS 38 chip select input (active HIGH or LOW) ALE 39 address latch enable in case of multiplexed configuration (connect to VDD in non-multiplexed configuration) INT 40 interrupt output (active LOW) INTAUX 41 auxiliary interrupt input AD3 42 register selection address 3 AD2 43 register selection address 2 AD1 44 register selection address 1 AD0 45 register selection address 0 XTAL2 46 connection pin for an external crystal 37 WR 38 CS 39 ALE 40 INT 41 INTAUX 42 AD3 43 AD2 44 AD1 handbook, full pagewidth 45 AD0 connection pin for an external delay capacitor 46 XTAL2 connection pin for an external crystal or input for an external clock signal 48 47 XTAL1 47 DELAY 48 DELAY XTAL1 RSTOUT 1 36 RD I/OAUX 2 35 D7 I/O1 3 34 D6 C81 4 33 D5 PRES1 5 32 D4 C41 6 31 D3 TDA8007BHL TDA8007BHL GNDC1 7 30 D2 CLK1 8 29 D1 VCC1 9 28 D0 Fig.2 Pin configuration. 2001 July 07 7 SBM 24 VDDA 23 SBP 22 SAP 21 VUP 20 GND 19 RST2 18 25 AGND CLK2 16 C82 12 VCC2 17 26 SAM C42 14 I/O2 11 GNDC2 15 27 VDD PRES2 13 RST1 10 FCE678 FCE678 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface handbook, full pagewidth TDA8007BC2 TDA8007BC2 AD0 to AD3 CS D0 to D7 ALE WR RD LATCH REC MUX MUX addresses RD WR REGISTERS FCE679 FCE679 Fig.3 Multiplexed bus recognition. FUNCTIONAL DESCRIPTION Throughout this specification, it is assumed that the reader is aware of ISO 7816 norm terminology. Interface control The TDA8007BC2 TDA8007BC2 can be controlled via an 8-bit parallel bus (bits D0 to D7). If a microcontroller with a multiplexed address/data bus (such as the 80C51 80C51) is used, then D0 to D7 may be directly connected to P0 to P7. When CS is LOW, the demultiplexing of address and data is performed internally using the ALE signal, a LOW pulse on pin RD allows the selected register to be read, a LOW pulse on pin WR allows the selected register to be written to. The TDA8007BC2 TDA8007BC2 automatically switches to the multiplexed bus configuration if a rising edge is detected on pin ALE. In this event, AD0 to AD3 play no role and may be tied to VDD or GND. Using a 80C51 80C51 microcontroller, the TDA8007BC2 TDA8007BC2 is simply controlled with MOVX instructions. If ALE is tied to VDD or GND, then the TDA8007BC2 TDA8007BC2 will be in the non-multiplexed configuration. In this case, the address bits are external pins AD0 to AD3, RD is the read/write control signal, and WR is a data write or read active LOW enable signal. In both configurations, the TDA8007BC2 TDA8007BC2 is selected only when CS is LOW. INT is an active LOW interrupt signal. In non-multiplexed bus configuration, CS and EN play the same role. In read operations (RD/WR is HIGH), the data corresponding to the chosen address is available on the bus when both CS and EN are LOW. In write operations, the data present on the bus is written when signals RD/WR, CS and EN become LOW. 2001 July 07 8 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 handbook, full pagewidth ALE tW(ALE) tW(RD) tAVLL tAVLL t(RWH-AH) t(RWH-AH) t(AL-RWL) CS t(AL-RWL) ADDRESS D0 to D7 DATA READ ADDRESS DATA WRITE t(DV-WL) RD t(RL-DV) tW(WR) WR FCE680 FCE680 Fig.4 Control with multiplexed bus. address A0/A3 pin RD R/W t3 t1 t2 CS EN (pin WR) data out D0/D7 FCE840 FCE840 Fig.5 Control with non-multiplexed bus. (Read) 2001 July 07 9 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 Write cycle timing chart: control CS address A0/A3 pin RD R/W t7 CS EN (pin WR) t4 high Z D0/D7 t5 data in FCE841 FCE841 Fig.6 Control with non-multiplexed bus. (Write with CS) address A0/A3 pin RD R/W t7 CS EN (pin WR) D0/D7 t6 t4 high Z t5 data in FCE841 FCE841 Fig.7 Control with non-multiplexed bus. (Write with EN) 2001 July 07 10 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 Control registers The TDA8007BC2 TDA8007BC2 has 2 complete analog interfaces which can drive card 1 and card 2. The data to and from these 2 cards share the same ISO UART. The data to and from a third card (card 3), externally interfaced (with a TDA8020 TDA8020 or TDA8004 TDA8004 for example), may also share the same ISO UART. Cards 1, 2 and 3 have dedicated registers for setting the parameters of the ISO UART; Programmable Divider Register (PDR), Guard Time Register (GTR), UART Configuration Register 1 (UCR1), UART Configuration Register 2 (UCR2) and Clock Configuration Register (CCR). Cards 1 and 2 also have dedicated registers for controlling their power and clock configuration. The Power Control Register (PCR) for card 3, is controlled externally. The PCR is also used for writing or reading on the auxiliary card contacts C4 and C8. Card 1, 2 or 3 can be selected via the Card Select Register (CSR). When one card is selected, the corresponding parameters are used by the ISO UART. The CSR also contains one bit for resetting the ISO UART (active LOW). This bit is reset after Power-on, and must be set to HIGH before starting with any one of the cards. It may be reset by software when necessary. When the specific parameters of the cards have been programmed, the UART may be used with the following registers: UART Receive Register (URR), UART Transmit Register (UTR), UART Status Register (USR) and Mixed Status Register (MSR). In reception mode, a FIFO of 1 to 8 characters may be used, and is configured with the FIFO Control Register (FCR).This register is also used for the automatic retransmission of NAKed characters in transmission mode The Hardware Status Register (HSR) gives the status of the supply voltage, of the hardware protections and of the card movements. HSR and USR give interrupts on pin INT when some of their bits have been changed. The MSR does not give interrupts and may be used in the polling mode for some operations; for this use, some of the interrupt sources within the USR and HSR may be masked. A 24-bit time-out counter may be started to give an interrupt after a number of ETUs programmed into time out registers TOR1, TOR2 and TOR3. This will help the microcontroller in processing different real-time tasks (ATR, WWT, BWT, etc.) mainly if the microcontrollers and cards clock are asynchronous. This counter is configured with a register Time-Out counter Configuration (TOC). It may be used as a 24-bit or as a 16 + 8 bits. Each counter can be set to start counting once data has been written, or on detection of a start bit on the I/O, or as auto-reload. 2001 July 07 11 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be . ISO UART TIME-OUT REGISTER 1 UART STATUS REGISTER UART TRANSMIT REGISTER TIME-OUT REGISTER 2 MIXED STATUS REGISTER UART RECEIVE REGISTER TIME-OUT REGISTER 3 FIFO CONTROL REGISTER TIME-OUT CONFIGURATION CARD2 CARD3 PROGRAM DIVIDER REGISTER 1 PROGRAM DIVIDER REGISTER 2 PROGRAM DIVIDER REGISTER 3 GUARD TIME REGISTER 1 GUARD TIME REGISTER 2 GUARD TIME REGISTER 3 UART CONFIGURATION REGISTER 11 UART CONFIGURATION REGISTER 21 UART CONFIGURATION REGISTER 31 UART CONFIGURATION REGISTER 12 UART CONFIGURATION REGISTER 22 UART CONFIGURATION REGISTER 32 CLOCK CONFIGURATION REGISTER 1 CLOCK CONFIGURATION REGISTER 2 CLOCK CONFIGURATION REGISTER 3 POWER CONTROL REGISTER 1 POWER CONTROL REGISTER 2 FCE682 FCE682 Preliminary specification V1.5 Fig.8 Registers summary. TDA8007BC2 TDA8007BC2 handbook, full pagewidth 12 CARD1 Philips Semiconductors HARD STATUS REGISTER Double multiprotocol IC card interface 2001 July 07 GENERAL CARD SELECT REGISTER Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 GENERAL REGISTERS Card Select Register Table 1 Card select register (write and read); address: 0 (all significant bits are cleared after reset, except CS5 which is set and CS4, CS6, CS7 which are reset) CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 0 0 1 0 RIU SC3 SC2 SC1 The Card Select Register (see Table 1) is used for selecting the card on which the UART will act, and also to reset the ISO UART. If SC1 = 1, then card 1 is selected; if SC2 = 1, then card 2 is selected, if SC3 = 1, then card 3 is selected. These bits must be set one at a time. After reset, no card is selected by default. The bit Reset ISO UART (RIU) must be set to logic 1 by software before any action on the UART can take place. When reset, this bit resets a large part of the UART registers to their initial value (See registers table below)A minimum negative pulse of 10ns is necessary. RIU must be reset before any activation. Note: CS5 is set to 1 , CS4, CS6 and CS7 are reset to 0 for identifying C2 version from C1 version. Hardware Status Register Table 2 Hardware status register (read only); address: F (all significant bits are cleared after reset, except for SUPL which is set within the RSTOUT pulse) HS7 HS6 HS5 HS4 HS3 HS2 HS1 HS0 not used PRTL2 PRTL1 SUPL PRL2 PRL1 INTAUXL PTL The Hardware Status Register (see Table 2) gives the status of the chip after a hardware problem has been detected. Presence Latch 1 (PRL1) and Presence Latch 2 (PRL2) are HIGH when a change has occurred on PRES1 and PRES2. Supervisor Latch (SUPL) is HIGH when the supervisor has been activated. Protection 1 (PRTL1) and Protection 2 (PRTL2) are HIGH when a default has been detected on card readers 1 and 2. (PRTL is the OR function of protection on VCC and RST). PTL is set if overheating has occurred. INTAUXL is HIGH if the level on the INTAUX input has been changed. When PRTL2, PRTL1, PRL2 or PRL1 or PTL is HIGH, then INT is LOW. The bits having caused the interrupt are cleared when the HSR has been read-out. The same occurs with bit INTAUXL if not disabled. In case of emergency deactivation (by PRTL1, PRTL2, SUPL, PRL2, PRL1 or PTL), the START bit is automatically reset by hardware. At power-on, or after a supply voltage dropout, SUPL is set and INT is LOW. INT will return HIGH at the end of the alarm pulse on pin RSTOUT. SUPL will be reset only after a status register read-out outside the ALARM pulse (see Fig.13). A minimum time of 2us is needed between 2 successive read operations in HSR, as well as between read of HSR and activation (write in PCR). Time Out Counters These etu counters may only be used when a card is active, with a running CLK. 2001 July 07 13 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface Table 3 TDA8007BC2 TDA8007BC2 Time-out register 1 (write only); address: 9 (all bits are cleared after reset) TO17 TO16 TO15 TO14 TO13 TO12 TO11 TO10 TOL7 TOL6 TOL5 TOL4 TOL3 TOL2 TOL1 TOL0 Table 4 Time-out register 2 (write only); address: A (all bits are cleared after reset) TO27 TO26 TO25 TO24 TO23 TO22 TO21 TO20 TOL15 TOL14 TOL13 TOL12 TOL11 TOL10 TOL9 TOL8 Table 5 Time-out register 3 (write only); address: B (all bits are cleared after reset) TO37 TO36 TO35 TO34 TO33 TO32 TO31 TO30 TOL23 TOL22 TOL21 TOL20 TOL19 TOL18 TOL17 TOL16 The three registers TOR1, TOR2 and TOR3 form a programmable 24-bit ETU counter, or two independant counters (one 16-bit and one 8-bit). The value to load in TOR1, 2 and 3 is the number of ETUs to count. Table 6 Time-out configuration register (read and write); address: 8 (all bits are cleared after reset) TOC7 TOC6 TOC5 TOC4 TOC3 TOC2 TOC1 TOC0 TOC7 TOC6 TOC5 TOC4 TOC3 TOC2 TOC1 TOC0 The TOC register is used for setting different configurations of the time-out counter as given in Table 7 (all other configurations are undefined). The timers can operate in 3 modes: · Soft triggered: · Start bit mode: · Autoreload mode: 2001 July 07 14 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface Table 7 TDA8007BC2 TDA8007BC2 Time-out counter configurations TOC OPERATING MODE 00H all counters are stopped 05H Counters 2 and 3 are stopped; counter 1 continues to operate in autoreload mode. 61H Counter 1 is stopped, and counters 3 and 2 form a 16-bit counter. Counting the value stored in TOR3 and TOR2 is started after 61H is written in the TOC. An interrupt is given, and bit TO3 is set within the USR when the terminal count is reached. The counter is stopped by writing 00H in the TOC, and shall be stopped before reloading a new value in TOR2, TOR3. 65H Counter 1 is an 8-bit auto reload counter, and counters 3 and 2 form a 16-bit counter. Counter 1 starts counting the content of TOR1 on the first start bit (reception or transmission) detected on I/O after 65H is written in the TOC. When counter 1 reaches its terminal count, an interrupt is given, bit TO1 in the USR is set, and the counter automatically restarts the same count until it is stopped. It is not allowed to change the content of TOR1 during a count. Counters 3 and 2 are wired as a single 16-bit counter and starts counting the value TOR3 and TOR2 when 65H is written in the TOC. When the counter reaches its terminal count, an interrupt is given and bit TO3 is set within the USR. Both counters are stopped when 00H is written in the TOC. Counter 3 and 2 shall be stopped by writing 05H in TOC before reloading a new value in TOR2, TOR3. 68H Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in TOR3, TOR2 and TOR1 is started after 68H is written in the TOC. The counter is stopped by writing 00H in the TOC. It is not allowed to change the content of TOR3, TOR2 and TOR1 within a count. 7CH Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in TOR3, TOR2 and TOR1 on the first start bit detected on I/O (reception or transmission) after the value has been written, and then on each subsequent start bit. It is possible to change the content of TOR3, TOR2 and TOR1 during a count; the current count will not be affected and the new count value will be taken into account at the next start bit. The counter is stopped by writing 00H in the TOC. In this configuration TOR3, TOR2 and TOR1 must not be all zero. 85H Same as 05H, except that all the counters will be stopped at the end of the 12th etu following the first received start bit detected after 85H has been written in TOC. E5H Same configuration as TOC = 65H, except that counter 1 will be stopped at the end of the 12th ETU following the first start bit detected after E5H has been written in the TOC. The time-out counter is very useful for processing the clock counting during ATR, the Work Waiting Time, or the waiting times defined in T = 1 protocol. It should be noted that the 200 and 400 CLK counter used during ATR is done by hardware when the start session is set; a specific hardware controls functionality BGT in T = 1 protocol, and a specific register is available for processing the extra guard time. It is not allowed to write in TOC as long as the card is not activated with a running CLK. For restarting the timers in software triggered mode, it is necessary to stop them before. Detailed examples of how to use these specific timers can be found in Application Note AN01010 AN01010. 2001 July 07 15 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 ISO UART REGISTERS Uart Transmission Register Table 8 UART transmit register (write only); address: D (all bits are cleared after reset) UT7 UT6 UT5 UT4 UT3 UT2 UT1 UT0 UT7 UT6 UT5 UT4 UT3 UT2 UT1 UT0 When the microcontroller wants to transmit a character to the selected card, it writes the data in direct convention in the UART Transmit Register (see Table 8). The transmission: · Starts at the end of writing (on the rising edge of WR) if the previous character has been transmitted and if the extra guard time has expired; or · Starts at the end of the extra guard time if this one has not expired; or · Does not start if the transmission of the previous character is not completed. In the case of a synchronous card (bit SAN within UCR2 is set), only D0 is relevant, and is copied on the I/O of the selected card. Mixed Status Register Table 9 Mixed status register (read only); address: C (bits TBE,/RBF, BGT and CLKSW are cleared after reset; bits FE and CRED are set after reset) MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 CLKSW FE BGT CRED PR2 PR1 INTAUX TBE/RBF The Mixed Status Register (see Table 9) relates the status of pin INTAUX, the cards presence contacts PR1 and PR2, the BGT counter, the FIFO empty indication and the transmit/receive ready indicator TBE/RBF. It also gives usefull indications when switching the CLK to or from fint/2 and when driving the TDA8007BC2 TDA8007BC2 with fast controllers. Bit INTAUX is set when the level on pin INTAUX is HIGH, it is reset when the level is LOW. In T=1 protocol, bit BGT is linked with a 22 ETU counter, which is started at every start bit on the I/O. Bit BGT is set if the count is finished before the next start bit. This helps to verify that the card has not answered before 22 ETUs after the last transmitted character, or that the reader is not not transmitting a character before 22 ETUs after the last received character. In T=0 protocol, bit BGT is linked with a 16 ETU counter, which is started at every start bit on the I/O. Bit BGT is set if the count is finished before the next start bit. This helps to verify that the reader is not not transmitting a character before 16 ETUs after the last received character. PR1 is HIGH when card 1 is present, PR2 is HIGH when card 2 is present. FE is set when the reception FIFO is empty. It is reset when at least one character has been loaded in the FIFO. Bit TBE/RBF (Transmit Buffer Empty/Receive Buffer Full) is set when: · Changing from reception mode to transmission mode · A character has been transmitted by the UART · The reception FIFO is full. Bit TBE/RBF is reset after Power-on or after one of the following: · When bit RIU is reset · When a character has been written to the UTR 2001 July 07 16 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 · When at least one character has been read in the FIFO · When changing from transmission mode to reception mode. CLKSW is set when TDA8007BC2 TDA8007BC2 has performed a required clock switch from fXTAL/n to fint/2, and is reset when TDA8007BC2 TDA8007BC2 has performed a required clock switch from fint/2 to fXTAL/n; the application shall wait till this bit is set or reset before sending a new command to the card. This bit is reset at power on. It is advised to use the bit CRED for driving TDA8007BC2 TDA8007BC2 with high speed controllers. Before writing in TOC or UTR, or reading from URR, check if CRED is set. If reset, it means that the writing or reading operation will not be correct because the controller is acting faster than the required time for this operation: · 2/31 or 2/32 etu after rising edge of WR for writing in TOC (tWRTOC - tWR) · 2 CLK cycles after rising edge of WR for writing in UTR (tWRSB - tWR) · 2 CLK cycles after rising edge of RD for reading from URR (tRDEN - tRD) CRED is set at power on. IO TBE INT WR CRED tWR tWRSB Fig.9 Minimum time between 2 write operations in UTR IO RBF FE tSBFE INT tSBRBF RD tRD CRED tRDEN Fig.10 Minimum time between 2 read operations in URR 2001 July 07 17 tRDEN Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 WR tWR CRED tWRTOC Fig.11 Minimum time between 2 write operations in TOC No bits within the MSR act upon INT. FIFO Control Register Table 10 FIFO control register (write only); address: C (all relevant bits are cleared after reset) FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 not used PEC2 PEC1 PEC0 not used FL2 FL1 FL0 · The FIFO Control Register bits are given in Table 10, FL2, FL1 and FL0 determine the depth of the FIFO (000 = length 1, 111 = length 8). PEC2, PEC1 and PEC0 determine the number of allowed repetitions in reception or in transmission before setting bit PE (Parity Error) in the USR and pulling INT LOW; 000 indicates that if only one parity error has occurred, bit PE is set; 111 indicates that bit PE will be set after 8 parity errors. In protocol T = 0: · If a correct character is received before the programmed error number is reached the error counter will be reset. · If the programmed number of allowed parity errors is reached, bit PE in the USR will be set as long as the USR has not been read. · If a transmitted character has been NAKED by the card, then the TDA8007BC2 TDA8007BC2 will automatically retransmit it a number of times equal to the value programmed in PEC2, PEC1, PEC0. The character will be resent at 15 etu. · In transmissiom mode, if PEC2=PEC1=PEC0=0, then the automatic retransmission is invalidated; the character manually rewritten in UTR will start at 13.5 etu. In protocol T = 1: · The error counter has no action (bit PE is set at the first wrong received character). Uart Status Register The UART Status Register (see Table 11) is used by the microcontroller to monitor the activity of the ISO UART and that of the time-out counter. 2001 July 07 18 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 Table 11 UART status register (read only); address: E (all bits are cleared after reset) US7 US6 US5 US4 US3 US2 US1 US0 TO3 not used TO1 EA PE OVR FER TBE/RBF Transmission Buffer Empty (TBE) is HIGH when the UART is in transmission mode, and when the microcontroller may write the next character to transmit in the UTR. It is reset when the microcontroller has written data in the transmit register or when bit T/R within UCR1 has been reset either automatically or by software. After detection of a parity error in transmission, it is necessary to wait 13 ETUs before rewriting the character which has been Not ACKnowledged (NAK) by the card. (Manual mode, see above) Reception Buffer Full (RBF) is HIGH when the FIFO is full. The microcontroller may read some of the characters in the URR, which clears bit RBF. TBE and RBF share the same bit within the USR (when in transmission mode, the relevant bit is TBE; when in reception mode, it is RBF). Framing Error (FER) is HIGH when the I/O was not in the high-impedance state at 10.25 ETUs after a start bit. It is reset when the USR has been read-out. Overrun (OVR) is HIGH if the UART has received a new character whilst the FIFO was full. In this case, at least one character has been lost. In protocol T = 0: Parity Error (PE) is HIGH if the UART has detected a number of received characters with parity errors equal to the number written in PEC2, PEC1 and PEC0 or if a transmitted character has been NAKed by the card a number of times equal to the value programmed in PEC2, 1. 0. It is set at 10.5 etu in reception mode, and at 11.5 etu in transmission mode. In protocol T = 0: a character received with a parity error is not stored in the FIFO (the card is supposed to repeat this character). In protocol T = 1: a character with a parity error is stored in the FIFO and the parity error counter is not active. Early Answer (EA) is HIGH if the first start bit on the I/O during ATR has been detected between 200 and 384 CLK pulses (all activities on the I/O during the 200 first CLK pulses with RST LOW or HIGH are not taken into account). These 2 features are reinitialized at each toggling of RST. Bit TO1 is set when counter 1 has reached its terminal count. Bit TO3 is set when counter 3 has reached its terminal count. If any of the status bits FER, OVR, PE, EA, TO1 or TO3 are set then INT will go LOW. The bit having caused the interrupt is reset 2us after the rising edge of RD during a read operation of USR. If TBE/RBF is set, and if the mask bit DISTBE/RBF within UCR2 is not set, then INT will also be LOW. TBE/RBF is reset 3CLK cycles after a data has been written in UTR, or 3CLK cycles after a data has been read from URR, or when changing from transmission mode to reception mode if the FIFO had not been left full when going to transmission. In order to avoid counting these CLK cycles, the bit CRED described in the MSR may be used. If LCT is used for transmitting the last character, then TBE is not set at the end of the transmission. CARD REGISTERS When cards 1, 2 or 3 are selected, then the following registers may be used for programming some specific parameters. 2001 July 07 19 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 Programmable Divider Register Table 12 Programmable Divider Register (PDR1, 2 and 3) (read and write); address: 2 (all bits are cleared after reset) PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 The Programmable Divider Register (see Table 12) is used for counting the cards clock cycles forming the ETU. It is an auto-reload 8-bit counter decounting from the programmed value down to 0. Uart Configuration Register 2 Table 13 UART configuration register 2 (UCR21 UCR21, 22 and 23) (read and write); address: 3 (all relevant bits are cleared after reset) UC27 UC26 UC25 UC24 UC23 UC22 UC21 UC20 not used DISTBE/RBF DISAUX PDWN SAN AUTOCONV CKU PSC The UART Configuration Register 2 bits are given in Table 13. If bit PSC is set to logic 1, then the prescaler value is 32. If bit PSC is set to logic 0, then the prescaler value is 31. One ETU will last a number of card clock cycles equal to prescaler x PDR. All baud rates specified in ISO 7816 norm are achievable with this configuration. CLK ./. 31 or 32 2xCLK ./. PDR Mux CKU Fig.12 etu generation 2001 July 07 20 ETU Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 Table 14 Baud rates with a 3.58 MHz card clock frequency for PSC=31, 4.92MHz for PSC=32(31;12 means prescaler set to 31 and PDR set to 12) D 1 2 3 F 0 31;12 9600 31;6 19200 31;3 38400 1 31;12 9600 31;6 19200 31;3 38400 2 31;18 6400 31;9 12800 4 3 31;24 4800 31;12 9600 31;6 19200 31;3 38400 4 31;36 3200 31;18 6400 31;9 12800 5 31;48 2400 31;24 4800 31;12 9600 31;6 19200 31;3 38400 6 31;60 1920 31;30 3840 31;15 7680 31;2 57600 31;3 38400 31;4 28800 31;5 23040 31;3 38400 5 9 32;16 9600 32;8 19200 32;4 38400 32;2 76800 32;1 153600 10 32;24 6400 32;12 12800 32;6 25600 32;3 51300 6 8 31;1 31;1 115200 115200 9 32;2 76800 11 32;32 4800 32;16 9600 32;8 19200 32;4 38400 32;2 76800 32;1 153600 12 32;48 3200 32;24 6400 32;12 12800 32;6 25600 32;3 51300 13 32;64 2400 32;32 4800 32;16 9600 32;8 19200 32;4 38400 32;2 76800 32;4 38400 For other baud rates than those given in Table 14, there is the possibility to set bit CKU (clock UART) to logic 1. In this case, the ETU will last half of the formula given above. Note that CKU=1 has no effect if CLK=fXTAL. This means for example that "76800" bauds are not possible when the card is clocked with the frequency on XTAL1. If bit AUTOCONV is set, then the convention is set by software using bit CONV in the UCR1. If it is reset, then the configuration is automatically detected on the first received character whilst the Start Session (SS) bit is set. Note: The bit AUTOCONV shall not be changed during a card session. Synchronous/Asynchronous (SAN) is set by software if a synchronous card is expected. The UART is then bypassed, and only bit 0 in the URR and UTR is connected to the I/O. In this case the CLK is controlled by bit SC in the CCR. When Power-down mode (PDWN) is set by software, the crystal oscillator is stopped. This mode allows low consumption in applications where it is required. During this mode, it is not possible to select another card other than the currently selected one. There are 5 ways of escaping from the Power-down mode: 1. Insert card 1 or card 2 2. Withdraw card 1 or card 2 3. Select the TDA8007BC2 TDA8007BC2 by resetting CS (this assumes that the TDA8007BC2 TDA8007BC2 had been deselected after setting Power-down mode) 4. INTAUXL has been set due to a change on pin INTAUX 5. If CS is permanently set to LOW, reset bit PDWN by software. After any of these 5 events, the TDA8007BC2 TDA8007BC2 will leave the Power-down mode. Except in case of a read operation of HSR,INT will be pulled LOW. The system microcontroller may then read the status registers after 5ms, and INT will return HIGH (if the system microcontroller has woken the TDA8007BC2 TDA8007BC2 by reselecting it, then no bits will be set in the status registers). Note that PDWN can only be entered if bit SUPL in the HSR has been cleared. If the Disable AUX (DISAUX) interrupt bit in UCR2 is set, then a change on INTAUX will not generate an interrupt (but bit INTAUXL in the HSR will be set; it is therefore necessary to read the HSR before a DISAUX reset to avoid an interrupt by INTAUXL). 2001 July 07 21 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 In order to avoid an interrupt during a change of card, it is better to set the DISAUX bit in UCR2 for all cards. If the Disable TBE/RBF (DISTBE/RBF) interrupt bit is set, then reception or transmission of a character will not generate an interrupt: This feature is useful for increasing communication speed with the card; in this case, a copy of the TBE/RBF bit within the MSR must be polled (and not the original) in order not to loose priority interrupts which can occur in the USR. Guard Time Register Table 15 Guard time register (GTR1, 2 and 3) (read and write); address: 5 (all bits are cleared after reset) GT7 GT6 GT5 GT4 GT3 GT2 GT1 GT0 GT7 GT6 GT5 GT4 GT3 GT2 GT1 GT0 The Guard Time Register (see Table 15) is used for storing the number of guard ETUs given by the card during ATR. In transmission mode, the UART will wait this number of ETUs before transmitting the character stored in the UTR. In T = 1 protocol, when GTR = FF means operation at 11 ETUs. In protocol T = 0, GTR = FF means operation at 12 ETUs. Uart Configuration Register 1 Table 16 UART configuration register 1 (UCR11 UCR11, 12 and 13) (read and write); address: 6 (all relevant bits are cleared after reset) UC7 UC6 UC5 UC4 UC3 UC2 UC1 UC0 not used FIP FC PROT T/R LCT SS CONV The UART Configuration Register 1 (see Table 16) is used for setting the parameters of the ISO UART. The Convention (CONV) bit is set if the convention is direct. CONV is either automatically written by hardware according to the convention detected during ATR, or by software if the bit AUTOCONV in UCR2X is set. The SS bit is set by software before ATR for automatic convention detection and early answer detection. It is automatically reset by hardware at 10.5 etu after reception of the initial character. The Last Character to Transmit (LCT) bit is set by software before writing the last character to be transmitted in the UTR. It allows automatic change to reception mode. It is reset by hardware at the end of a successful transmission (11+28/31 or 28/32 etu in T=0, 10+28/31 or 28/32 etu in T=1 protocol). When LCT is beeing reset, the bit T/R is also reset and the UART is ready for receiving a character. The Transmit/Receive (T/R) bit is set by software for transmission mode. A change from logic 0 to logic 1 will set bit TBE in the USR. Bit T/R is automatically reset by hardware if the LCT bit has been used before transmitting the last character. The Protocol (PROT) bit is set if the protocol type is asynchronous T = 1. If PROT = 0, the protocol is T = 0. Bit 5 (FC) is a test bit, and must be left to 0. If the Force Inverse Parity (FIP) bit is set to HIGH the UART will NAK a correctly received character, and will transmit characters with wrong parity bits. 2001 July 07 22 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 Clock Configuration Register Table 17 Clock configuration register (CCR1, 2 and 3) (read and write); address: 1 (all bits are cleared after reset) CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 not used not used SHL CST SC AC2 AC1 AC0 Clock Configuration Register (see Table 17): · For cards 1 and 2, the CCR defines the clock for the selected card. · For cards 1, 2 and 3 it defines the clock to the ISO UART. It should be noted that if bit CKU in the prescaler register of the selected card (UCR2X) is set, then the ISO UART is clocked at twice the frequency of the card, which allows baud rates not foreseen in ISO 7816 norm to be reached. In case of an asynchronous card, the Clock Stop (CST) bit defines whether the clock to the card is stopped or not. If CST is set, then CLK is stopped LOW if SHL = 0, and HIGH if SHL = 1. If CST is reset, then CLK is determined by bits AC0, AC1 and AC2; see Table 18. All frequency changes are synchronous, thus ensuring that no spike or unwanted pulse widths occur during changes. Table 18 CLK value for an asynchronous card AC2 AC1 AC0 CLK 0 0 0 XTAL 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1/ XTAL 2 1/ XTAL 4 1/ XTAL 8 1/ f 2 int 1/ f 2 int 1/ f 2 int 1/ f 2 int Note: fint is the frequency delivered by the internal oscillator In case of CLK=XTAL, the duty cycle must be ensured by the incoming clock signal on XTAL1. When switching from XTAL/n to 1/2fint or vice verse, only bit AC2 must be changed (AC1 and AC0 must remain the same). When switching from XTAL/n or 1/2fint to CLK STOP or vice verse, only bits CST and SHL must be changed. When switching from XTAL/n to 1/2fint or vice verse, a maximum delay of 200 µs can occur between the command and the effective frequency change on CLK (the fastest switching time is from 1/2XTAL to 1/2fint or vice verse, the best for duty cycle is from 1/8XTAL to 1/2fint or vice verse). It is necessary to survey the bit CLKSW in the MSR before retransmitting commands to the card. In the event of a synchronous card, then the CLK contact is the copy of the value written in Synchronous Clock (SC). In reception mode, the data from the card is available to UR0 after a read operation of the URR; in transmission mode, the data is written on the I/O line of the card when the UTR has been written to and remains unchanged when another card is selected. 2001 July 07 23 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 Power Control Register Table 19 Power control register (PCR1 and 2) (read and write); address: 7 (all relevant bits are cleared after reset) PCR7 PCR6 PCR5 PCR4 PCR3 PCR2 PCR1 PCR0 not used not used C8 C4 1V8 RSTIN 3V/5V START The Power Control Register (PCR), see Table 19: · Starts or stops card sessions. · Reads or writes on auxiliary card contacts C4 and C8. · Is available only for cards 1 or 2. If the microcontroller sets START to logic 1, then the selected card is activated (see Section "Activation sequence"). If the microcontroller resets START to logic 0, then the card is deactivated (see Section "Deactivation sequence"). START is automatically reset in case of emergency deactivation. If 3 V/5 V is set to logic 1, then VCC is 3 V. If 3 V/5 V is set to logic 0, then VCC is 5 V. When the card is activated, pin RST is the copy of the value written in RSTIN. If bit 1V8 is set, then VCC = 1.8 V: It should be noted that no specification is guaranteed at this voltage. When writing to the PCR, C4 will output the value written to PCR4, and C8 the value written to PCR5. When reading from the PCR, PCR4 will store the value on C4, and PCR5 the value on C8. For deactivating the card, only bit START should be reset. 2001 July 07 24 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 Register Summary Table 20 Register summary 7 6 R/W CSR 00 R/W 0 1 0 RIU SC3 SC2 SC1 00100000 HSR 0F R not used PRTL2 PRTL1 SUPL PRL2 PRL1 INTAUXL PTL X0010000 X0010000 MSR 0C R CLKSW FE BGT CRED PR2 PR1 INTAUX TOR1 09 W TOL7 TOL6 TOL5 TOL4 TOL3 TOL2 TOL1 TOL0 00000000 = TOR2 0A W TOL15 TOL14 TOL13 TOL12 TOL11 TOL10 TOL9 TOL8 00000000 = TOR3 0B W TOL23 TOL22 TOL21 TOL20 TOL19 TOL18 TOL17 TOL16 00000000 = TOC 08 R/W TOC7 TOC6 TOC5 TOC4 TOC3 TOC2 TOC1 TOC0 00000000 00000000 UTR 0D W UT7 UT6 UT5 UT4 UT3 UT2 UT1 UT0 00000000 00000000 URR 0D R UR7 UR6 UR5 UR4 UR3 UR2 UR1 UR0 00000000 00000000 FCR 0C W not used PEC2 PEC1 PEC0 not used FL2 FL1 FL0 X000X000 X000X000 X000X000 X000X000 USR 0E R TO3 not used TO1 EA PE OVR FER TBE/ RBF 0X000000 0X000000 0X000000 0X000000 PDR 02 R/W PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 00000000 = UCR2 03 R/W not used DISTBE/RBF DISAUX PDWN SAN AUTOC CKU PSC X0000000 X0000000 = GTR 05 R/W GT7 GT3 GT2 GT0 00000000 = UCR1 06 CCR 01 PCR 07 GT6 4 3 2 1 GT1 TBE/RBF 0101XXX0 0101XXX0 00100000 X=XXX= =1=1=0 GT5 GT4 R/W not used FIP FC PROT T/R LCT SS CONV X0000000 X0000000 X=00= R/W not used not used SHL CST SC AC2 AC1 AC0 XX000000 XX000000 XX000000 XX000000 R/W not used not used C8 C4 1V8 RSTIN 3V/5V START XX110000 XX110000 XX110000 XX110000 Note: X means undefined, = means no change Note: PDR, GTR, UCR1, UCR2, CCR, PCR are different according to the selected card. 2001 July 07 0 VALUE WHEN RIU=0 ADDR 0 5 VALUE AT RESET NAME 25 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 handbook, full pagewidth V th1 VDD Vth2 CDELAY tw RSTOUT SUPL INT Status read Power-on Supply dropout Reset by CDELAY Power-off FCE683 FCE683 Fig.13 Voltage supervisor. Supply The TDA8007BC2 TDA8007BC2 operates within a supply voltage range of 2.7 to 6 V. The supply pins are VDD, VDDA, GND and AGND. Pins VDDA and AGND supply the analog drivers to the cards and have to be externally decoupled because of the large current spikes that the cards and the step-up converter can create.VDDA may be different from VDD.Pins VDD and GND supply the rest of the chip. An integrated spike killer ensures that the contacts to the cards remain inactive during power-up or power-down. An internal voltage reference is generated which is used within the step-up converter, the voltage supervisor and the VCC generators. The voltage supervisor generates an alarm pulse, whose length is defined by an external capacitor tied to pin DELAY, when VDD is too low to ensure proper operation (1 ms per 2 nF typical). This pulse may be used as a reset pulse by the system microcontroller (pin RSTOUT, active HIGH). It is also used in order to either block any spurious noise on card contacts during the microcontrollers reset, or to force an automatic deactivation of the contacts in the event of supply dropout (see Sections "Activation sequence" and "Deactivation sequence"). After Power-on, or after a voltage drop, bit SUPL is set within the Hardware Status Register (HSR) and remains set until HSR is read-out outside the alarm pulse. Pin INT is LOW for the duration that RSTOUT is active. Step-up converter Except for the VCC generator and the other cards contacts buffers, the whole circuit is powered by VDD, and VDDA. If the supply voltage is 2.5 V, then a higher voltage is needed for the ISO contacts supply. When a card session is requested by the microcontroller, the sequencer first enables the step-up converter (a switched capacitors type) which is clocked by an internal oscillator at a frequency of approximately 2.5 MHz. Suppose that VCC is the maximum of VCC1 and VCC2, then there are five possible situations: 2001 July 07 26 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 6. VDD = 3 V and VCC = 3 V: in this case the step-up converter acts as a doubler with a regulation of VUP at approximately 4.0 V. 7. VDD = 3 V and VCC = 5 V: in this case the step-up converter acts as a tripler with a regulation of VUP at approximately 5.5 V. 8. VDD = 5 V and VCC = 3 V: in this case the step-up converter acts as a follower: VDD is applied to VUP. 9. VDD = 5 V and VCC = 5 V: in this case the step-up converter acts as a doubler with a regulation of VUP at approximately 5.5 V. 10. If VCC = 1.8V, then the step up converter acts as a follower for any value of VDD The recognition of the supply voltage is done by the TDA8007BC2 TDA8007BC2 at approximately 3.5 V. The output voltage VUP is fed to the VCC generators. VCC and GNDC are used as a reference for all other card contacts. ISO 7816 security The correct sequence during activation and deactivation of the cards is ensured by two specific sequencers, clocked by a division ratio of the internal oscillator. Activation (START bit HIGH in PCR1 or PCR2) is only possible if the card is present (PRES active HIGH with an internal current source to GND) and if the supply voltage is correct (supervisor not active). The presence of the cards is signalled to the microcontroller by the Hardware Status Register (HSR). Bits PR1 or PR2 (in the MSR) are set if card 1 or card 2 is present. PRL1 or PRL2 are set if PRES1 or PRES2 has toggled. During a session, the sequencer performs an automatic emergency deactivation on one card in the event of card take-off, or short-circuit. Both cards are automatically deactivated in the event of a supply voltage drop, or overheating. The hardware status register is updated and the INT line falls, so that the system microcontroller is aware of what happened. 2001 July 07 27 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 Activation sequence When the cards are inactive, VCC, CLK, RST, C4, C8 and I/O are LOW, with low-impedance with respect to GND. The step-up converter is stopped. When everything is satisfactory (voltage supply, card present and no hardware problems), the system microcontroller may initiate an activation sequence on a present card. After selecting the card and leaving the UART reset mode, and then configuring the necessary parameters for the counters and the UART, the START bit can be set within the PCR (t0) (see Fig.14): · The step-up converter is started (t1); if one card was already active, then the step-up converter was already on and nothing more occurs at this step · VCC starts rising (t2) from 0 to 5 V or 3 V with a controlled rise time of 0.17 V/µs (typ.) · I/O rises to VCC (t3); C4 and C8 also rise if bits C4 and C8 within the PCR have been set to logic 1 (integrated 14 k pull-up resistors to VCC) · The CLK is sent to the card and RST is enabled (t4). After a number of CLK pulses that can be counted with the time-out counter, bit RSTIN may be set by software: RST will then rise to VCC. The sequencer is clocked by 1/64fint which leads to a time interval of t = 25 µs (typ.). Thus t1 = 0 to 1/64t, t2 = t1 + 3/2t, t3 = t1 + 7/2t and t4 = t1 + 4t. Deactivation sequence When the session is completed, the microcontroller resets START HIGH (t10). The circuit then executes an automatic deactivation sequence (see Fig.15): · The card is reset (RST falls LOW) (t11) · The CLK is stopped (t12) · I/O, C4 and C8 fall to 0 V (t13) · VCC falls to 0 V with typical 0.17 V/µs slew rate (t14) · The step-up converter is stopped and CLK, RST, VCC and I/O become low-impedance to GND (t15) (if both cards are inactive). t11 = t10 + 1/64t, t12 = t11 + 1/2t, t13 = t11 + t, t14 = t11 + 3/2t and t15 = t11 + 7/2t. tde = time that VCC needs to decrease to less than 0.4 V. 2001 July 07 28 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 handbook, full pagewidth START VUP VCC I/O RSTIN CLK RST t0 t2 t3 t4 = tact ATR FCE684 FCE684 t1 Fig.14 Activation sequence. handbook, full pagewidth START RST CLK I/O VCC VUP t10 t11 t12 t13 t14 t15 tde Fig.15 Deactivation sequence. 2001 July 07 29 FCE685 FCE685 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. -0.5 MAX. analog supply voltage VDD supply voltage -0.5 +6.5 V Vn input voltage on all pins except SAM, SAP, SBM, SBP and VUP -0.5 VDD + 0.5 V input voltage on pins SAM, SAP, SBM, SBP and VUP -0.5 +7.5 V Tamb = -25 to +85 °C +6.5 UNIT VDDA V Ptot total power dissipation - 700 mW Tstg IC storage temperature -55 +150 °C Tj junction temperature - 125 °C Ves electrostatic discharge voltage (HBM) -6 +6 kV on pins I/O1, VCC1, RST1, CLK1, GNDC1, PRES1, I/O2, VCC2, RST2, CLK2, GNDC2 and PRES2 on pins C41, C42, C81 and C82 -5.5 +5.5 kV on pins D0 to D7 -1.8 +1.8 kV on other pins -2 +2 kV HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 2001 July 07 PARAMETER CONDITIONS from junction to ambient in free air 30 VALUE UNIT 78 K/W Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 CHARACTERISTICS VDD = 3.3 V; VDDA = 3.3V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD supply voltage 2.7 - 6.0 V VDDA supply voltage for the DC/DC converter VDD - 6.0 V IDD(pd) supply current in Power-down mode VDD = 3.3 V; cards inactive; XTAL oscillator stopped - - 350 µA VDD = 3.3 V; cards active at VCC = 5 V; CLK stopped; XTAL oscillator stopped - - 3 mA IDD(sm) supply current in Sleep mode both cards powered, but with CLK - stopped - 5.5 mA IDD(om) supply current in operating mode ICC1 = 65 mA; ICC2 = 15 mA; fXTAL = 20 MHz; fCLK = 10 MHz; 5 V cards; VDD = 2.7 V - - 315 mA ICC1 = 50 mA; ICC2 = 30 mA; fXTAL = 20 MHz; fCLK = 10 MHz; 3 V cards; VDD = 2.7 V - - 215 mA ICC1 = 50 mA; ICC2 = 30 mA; fXTAL = 20 MHz; fCLK = 10 MHz; 3 V cards; VDD = 5 V - - 100 mA 2.10 - 2.50 V Vth1 threshold voltage on VDD (falling) Vhys1 hysteresis on Vth1 50 - 170 mV Vth2 threshold voltage on pin DELAY - 1.25 - V VDELAY voltage on pin DELAY V Io(DELAY) output current at pin DELAY ALARM pulse width VDD + 0.3 -2 - µA - 2 - mA 1 - - nF - 10 - ms - - 10 µA capacitance value tW(ALARM) - - VDELAY = VDD (discharge) CDELAY - pin grounded (charge) CDELAY = 22 nF RSTOUT (open-drain active HIGH output) IOH HIGH-level output current active LOW option; VOH = 5 V VOL LOW-level output voltage active LOW option; IOL = 2 mA -0.3 - +0.4 V IOL LOW-level output current active HIGH option; VOL = 0 V - - -10 µA VOH HIGH-level output voltage active HIGH option; IOH = -1 mA 0.8VDD - VDD + 0.3 V Crystal oscillator fXTAL crystal frequency 4 - 25 MHz fext external frequency applied to pin XTAL1 0 - 25 MHz 2 2.5 3.7 MHz Step-up converter fint 2001 July 07 oscillation frequency 31 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface SYMBOL PARAMETER TDA8007BC2 TDA8007BC2 CONDITIONS MIN. TYP. MAX. UNIT Vdet(dt) voltage on pin VUP at least one 5 V card - 5.7 - V both cards 3 V VVUP - 4.1 - V 3.4 3.5 3.6 V 0 - 0.1 V detection voltage on VDD for doubler/tripler selection Reset output to the cards (RST1 and RST2) Vo(inactive) output voltage in inactive mode IRST(inactive) current from pin RST when inactive and pin grounded VOL LOW-level output voltage VOH HIGH-level output voltage tr rise time tf fall time no load 0 - 0.3 V 0 - -1 mA IOL = 200 µA 0 - 0.3 V IOH =-200 µA VCC - 0.5 - VCC V CL = 30 pF - - 0.1 µs CL = 30 pF - - 0.1 µs Iinactive = 1 mA Clock output to the cards (CLK1 and CLK2) Vo(inactive) output voltage in inactive mode no load 0 - 0.1 V Iinactive = 1 mA 0 - 0.3 V 0 - -1 mA ICLK(inactive) current from pin CLK when inactive and pin grounded VOL LOW-level output voltage IOL = 200 µA 0 - 0.3 V VOH HIGH-level output voltage IOH = -200 µA VCC - 0.5 - VCC V tr rise time CL = 30 pF - - 8 ns tf fall time CL = 30 pF - - 8 ns fCLK clock frequency 1 MHz Idle configuration 1 - 1.85 MHz operational 0 - 10 MHz duty factor CL = 30 pF 45 - 55 % SR slew rate (rise and fall) CL = 30 pF 0.2 - - V/ns Card supply voltage (VCC1 and VCC2) (2 ceramic multilayer capacitors with low ESR of minimum 100 nF should be used in order to meet these specifications) Vo(inactive) IVCC(inactive) 2001 July 07 output voltage in inactive mode no load 0 - 0.1 V Iinactive = 1 mA 0 - 0.3 V - - -1 mA current from pin VCC when inactive and pin grounded 32 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface SYMBOL VCC PARAMETER output voltage TDA8007BC2 TDA8007BC2 CONDITIONS MIN. TYP. MAX. UNIT active mode; ICC < 65 mA; 5 V card 4.75 5 5.25 V active mode; ICC < 50 mA; 3 V card 2.78 3 3.22 V active mode; ICC < 30 mA; 1.8 V card 1.65 1.8 1.95 V active mode; current pulses of 40 nC with I < 200 mA; t < 400 ns; f < 20 MHz; 5 V card 4.6 - 5.4 V active mode; current pulses of 24 nC with I < 200 mA; t < 400 ns; f < 20 MHz; 3 V card 2.75 - 3.25 V active mode; current pulses of 1.62 12 nC with I < 200 mA; t < 400 ns; f < 20 MHz; 1.8 V card - 1.98 V SR slew rate ICC1 + ICC2 - - -65 mA - - -50 mA 1.8V card; from 0 to 1.8 V output current 5 V card; from 0 to 5 V 3 V card; from 0 to 3 V ICC - - -30 mA up or down; maximum capacitance = 300 nF 0.05 0.16 0.22 V/µs - - -80 mA V sum of both cards current Data lines (I/O1 and I/O2) (I/O1 has an integrated 14 k pull-up at VCC1 and I/O2 at VCC2) Vo(inactive) output voltage in inactive mode no load 0 - 0.1 Iinactive = 1 mA - - 0.3 V - - -1 mA V Io(inactive) current from I/O when inactive and pin grounded VOL LOW-level output voltage I/O configured as an output; IOL = 1 mA 0 - 0.3 VOH HIGH-level output voltage I/O configured as an output; IOH < -20 µA 0.8VCC - VCC + 0.25 V VCC + 0.25 V I/O configured as an output; IOH < -40 µA (5 and 3V cards) 0.75VCC 75VCC - VIL LOW-level input voltage I/O configured as an input -0.3 - +0.8 V VIH HIGH-level input voltage I/O configured as an input 1.5 - VCC V IIL LOW-level input current on I/O VIL = 0 - - 600 µA ILI(H) input leakage current HIGH on I/O VIH = VCC - - 20 µA ti(tr), ti(tf) input transition times CL < = 30 pF - - 1.2 µs to(tr), to(tf) output transition times CL < = 30 pF - - 0.1 µs Rpu internal pull-up resistance between I/O and VCC 11 14 17 k 2001 July 07 33 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface SYMBOL PARAMETER TDA8007BC2 TDA8007BC2 CONDITIONS MIN. TYP. MAX. UNIT Auxiliary cards contacts (pins C41, C81, C42 and C82) (pins C41 and C81 have an integrated 10 k pull-up at VCC1, pins C42 and C82 have an integrated 10 k pull-up at VCC2) output voltage inactive no load 0 - 0.1 V Iinactive = 1 mA Vo(inactive) - - 0.3 V - - -1 mA V Iinactive current from pins C4 or C8 when inactive and pin grounded VOL LOW-level output voltage C4 or C8 configured as an output; 0 IOL = 1 mA - 0.3 VOH HIGH-level output voltage I/O configured as an output; IOH < -20 µA 0.8VCC - VCC + 0.25 V I/O configured as an output; IOH < -40 µA (5 and 3V cards) 0.75VCC 75VCC - VCC + 0.25 V VIL LOW-level input voltage C4 or C8 configured as an input -0.3 - +0.8 V VIH HIGH-level output voltage C4 or C8 configured as an input 1.5 - VCC V IIL LOW-level input current on pins C4 or C8 VIL = 0 - - 600 µA ILI(H) input leakage current HIGH on pins C4 or C8 VIH = VCC - - 20 µA ti(tr), ti(tf) input transition times CL = 30 pF - - 1.2 µs to(tr), to(tf) output transition times CL = 30 pF - - 0.1 µs tW(pu) width of active pull-up pulse - 200 - ns Rint(pu) internal pull-up resistance between C4/C8 and VCC 8 10 12 k f(max) maximum frequency on C4 or C8 - - 1 MHz tact activation sequence duration - - 130 µs tde deactivation sequence duration - - 150 µs Timing Protections and limitations ICC(sd) shutdown and limitation current at VCC - -100 - mA mA II/O(lim) limitation current on the I/O -15 - +15 ICLK(lim) limitation current on pin CLK -70 - +70 IRST(sd) shutdown current on RST IRST(lim) limitation current on RST -20 - +20 mA Tsd shutdown temperature - 150 - °C -20 mA mA Card presence inputs (pins PRES1 and PRES2) VIL LOW-level input voltage - - 0.3VDD V VIH HIGH-level input voltage 0.7VDD - - V IIL(L) input leakage current LOW -20 - +20 µA 2001 July 07 VIN = 0 34 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface SYMBOL IIL(H) PARAMETER input leakage current HIGH TDA8007BC2 TDA8007BC2 CONDITIONS MIN. -20 VIN = VDD TYP. MAX. - +20 UNIT µA Bidirectional data bus (pins D0 to D7) VIL LOW-level input voltage - - 0.3VDD V VIH HIGH-level input voltage 0.7VDD - - V IIL(L) input leakage current LOW -20 - +20 µA IIL(H) input leakage current HIGH -20 - +20 µA CL load capacitance - - 10 pF VOL LOW-level output voltage IOL = 5 mA - - 0.2VDD V VOH HIGH-level output voltage IOH = -5 mA 0.8VDD - - V to(tr), to(tf) output transition time CL = 50 pF - - 25 ns -0.3 - +0.3VDD V Logic inputs (pins ALE, A0, A1, A2, A3, INTAUX, CS, RD and WR) VIL LOW-level input voltage VIH HIGH-level input voltage 0.7VDD - VDD + 0.3 V IIL(L) input leakage current LOW -20 - +20 µA IIL(H) input leakage current HIGH -20 - +20 µA CL load capacitance - - 10 pF Auxiliary I/O (pin I/OAUX); pin I/O AUX has a 14k pullup to VDD VIL LOW-level input voltage -0.3 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - VDD + 0.3 V IIL(H) input leakage current HIGH -20 - +20 µA IIL LOW-level input current VIL = 0 - - -600 µA VOL LOW-level output voltage IOL = 1 mA - - 300 mV VOH HIGH-level output voltage IOH = 40 µA 0.75VDD 75VDD - VDD +0.25 V Rint(pu) internal pull-up resistance between I/OAUX and VDD 11 14 17 k ti(tr), ti(tf) input transition time CL = 30 pF - - 1 µs to(tr), to(tf) output transition time CL = 30 pF - - 0.1 µs fI/OAUX(max) maximum frequency on pin I/OAUX - - 1 MHz - - 0.3 V - - 10 µA Interrupt line INT (open-drain active LOW output) VOH LOW-level output voltage IIL(H) input leakage current HIGH IOH = 2 mA Timing for multiplexed bus; see Fig.4 tXTAL1 period on XTAL1 50 - - ns tW(ALE) ALE pulse width 20 - - ns tAVLL address valid to ALE LOW 10 - - ns t(AL-RWL) ALE LOW to RD or WR LOW 10 - - ns 2001 July 07 35 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface SYMBOL PARAMETER TDA8007BC2 TDA8007BC2 CONDITIONS MIN. TYP. MAX. UNIT RD pulse width for URR 2tXTAL1 - - ns pulse width for other registers 10 - - ns t(RL-DV) RD LOW to data out valid - - 50 ns t(RWH-AH) RD or WR HIGH to ALE HIGH 10 - - ns tW(WR) WR pulse width 10 - - ns t(DV-WL) data in valid to WR LOW 10 - - ns tW(RD) Timing for non-multiplexed bus; see Fig.5, Fig.6, Fig.7 t1 RD or EN to CS low t2 Access time: CS and EN to data out valid 10 50 ns ns t3 CS and EN to data High impedance 10 ns t4 Data val;id to end of write 10 ns t5 Data hold time 10 ns t6 R/W (RD) low to CS or EN (WR) low 10 ns t7 Address stable to EN or CS high 10 ns Timing for bit CRED; see Fig.8, Fig.9, Fig.10 tWRSB WR low to I/O low tWR+2tCLK tWR+3tCLK ns tRDEN RD low to CRED high tRD+2tCLK tRD+3tCLK ns tWRTOC WR low to CRED high 1/PSC 2/PSC etu 2001 July 07 36 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 APPLICATION INFORMATION: VDD C3 33 µF 16 V C15 TP20 WR 22 pF TP8 TP18 Y2 R2 0 VDD 22 pF I/OAUX I/O1 C81 WR CS 4 33 D7 7 D5 6 D4 5 31 D3 D2 30 D1 29 D0 28 V 27 DD SAM 26 AGND 25 TDA8007B TDA8007B 4 GND 19 VUP 20 SAP 21 SBP 22 VDDA 23 SBM 24 IC1 CLK2 16 VCC2 17 RST2 18 RD D6 32 PRES2 C18 100 nF 37 ALE 34 13 R3 0 TP51 GND VDD 3 2 1 0 P0(7:0) C27 100 nF C24 100 nF 220 K2 C22 100 nF VDD C1 10 µF 16 V C25 100 220 nF C13 100 nF VDD handbook, full pagewidth R4 100 k VDD C2 10 µF 16 V Fig.16 Application diagram. 2001 July 07 37 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 LPSEN ALE LEA P0.7 7 P0.6 6 P0.5 5 P0.4 4 P0.3 3 P0.2 2 P0.1 1 P0.0 0 VCC V 20 SS 21 XTAL1 22 19 XTAL2 23 18 P3.7 24 17 P3.6 25 16 P3.5 26 15 P3.4 27 14 P3.3 28 13 P3.2 29 12 P3.1 30 11 89C51 89C51 P3.0 31 10 RST 32 9 P1.7 8 33 P1.6 7 34 P1.5 6 35 P1.4 5 36 P1.3 4 37 P1.2 3 38 P1.1 2 39 P1.0 1 40 C16 C26 100 nF 220 K1 CARD 2 38 3 15 C19 100 nF CARD_READ_LM01 U6 INT AD2 AD1 AD0 XTAL2 AD3 42 43 44 45 XTAL1 35 14 K2 C8 C7 C6 C5 C11 C21 C31 C41 36 2 5 C41 6 GNDC1 7 CLK1 8 VCC1 9 RST1 10 I/O2 11 C82 12 CARD 1 C4 C3 C2 C1 C51 C61 C71 C81 1 PRES1 K1 CARD_READ_LM01 U5 46 RSTOUT 47 R1 100 k 48 C17 100 nF 100 nF DELAY C23 VDD C42 C8 C7 C6 C5 C11 C21 C31 C41 GNDC2 C4 C3 C2 C1 C51 C61 C71 C81 ALE C14 39 GND INTAUX 2 CS 8007B 8007B TP22 INT 40 +5 V C12 100 nF GND J1 TP23 TP4 1 41 3 V or J1 5V 100 nF VDD TX RX FCE690 FCE690 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 PACKAGE OUTLINE LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M pin 1 index bp Lp L 13 48 1 detail X 12 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A max. A1 A2 1.60 0.20 0.05 1.45 1.35 A3 bp c D (1) E (1) 0.25 0.27 0.17 0.18 0.12 7.1 6.9 7.1 6.9 e HD HE 0.5 9.15 8.85 9.15 8.85 L Lp 1.0 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 7 0o 0.95 0.55 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT313-2 136E05 136E05 MS-026 MS-026 2001 July 07 EIAJ EUROPEAN PROJECTION ISSUE DATE 99-12-27 00-01-19 38 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: · Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. · For packages with leads on two sides and a pitch (e): ­ larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; ­ smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. · For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 2001 July 07 39 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE REFLOW(1) BGA, LFBGA, SQFP, TFBGA not suitable suitable HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable(2) suitable PLCC(3), SO, SOJ suitable suitable LQFP, QFP, TQFP not recommended(3)(4) suitable SSOP, TSSOP, VSO not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2001 July 07 40 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 DATA SHEET STATUS DATA SHEET STATUS PRODUCT STATUS DEFINITIONS (1) Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Note 1. Please consult the most recently issued data sheet before initiating or completing a design. 2001 July 07 41 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2001 July 07 42 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface TDA8007BC2 TDA8007BC2 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2001 July 07 43 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface NOTES 2001 July 07 44 TDA8007BC2 TDA8007BC2 Philips Semiconductors Preliminary specification V1.5 Double multiprotocol IC card interface Printed in The Netherlands 2001 July 07 753504/03/pp45 Date of release: 2001 45 TDA8007BC2 TDA8007BC2 July 07 Document order number: 9397 750 07619