TCM38C17 SPAU019 SLWS040 C5402 TMC38C17 HC5514 SW7-10 J1-A31 J1-A32 J1-A30 - Datasheet Archive

 

Four-Channel Pulse-Code Modulated (PCM) Codec Evaluation Module (EVM) U s e r 's G u i d e User's Guide 2001 Mixed Signal

 

TCM38C17 TCM38C17 Four-Channel Pulse-Code Modulated (PCM) Codec Evaluation Module (EVM) U s e r 's G u i d e User's Guide 2001 Mixed Signal Broadband Communications U s e r 's G u Printed in U.S.A., August 2001 i d e SPAU019 SPAU019 TCM38C17 TCM38C17 Four-Channel Pulse-Code Modulated (PCM) Codec Evaluation Module (EVM) User's Guide SPAU019 SPAU019 August 2001 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, license, warranty or endorsement thereof. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Resale of TI's products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright © 2001, Texas Instruments Incorporated Preface Read This First About This Manual This document describes the TCM38C17 TCM38C17 evaluation module test interfaces that include the SLIC EVM cards, switches and required jumpers, test points, example test scenarios, schematics, PCM4 test-equipment use, and the PC board layout. How to Use This Manual This document contains the following chapters: Y Y Y Y Y Y Y Y Y Y Y Y Y Y Chapter 1 ­ Introduction Chapter 2 ­ TCM38C17 TCM38C17 EVM Chapter 3 ­ Interfaces Chapter 4 ­ Switches, Jumpers, and Test Points Chapter 5 ­ EVM Configurations When Used With the PCM4 Chapter 6 ­ Example Test Scenario Chapter 7 ­ Printed-Circuit-Board (PCB) Construction Appendix A ­ TCM38C17 TCM38C17 EVM Board Layout Appendix B ­ TCM38C17 TCM38C17 EVM Connections to the PCM4 Appendix C ­ PCM4 General Parameters Configuration Appendix D ­ DSP Starter-Kit Interface Appendix E ­ Test Points Appendix F ­ Schematics and Bill of Material Appendix G ­ References TCM38C17 TCM38C17 Codec Documentation Overview The remainder of the TCM38C17 TCM38C17 documentation consists of: Y TCM38C17 TCM38C17 data sheet, literature number SLWS040 SLWS040 iii Information About Cautions and Warnings Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment. CAUTION This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you. WARNING The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. Trademarks Intersil is a trademark of Intersil Americas Inc. QCombo is a trademark of Texas Instruments. iv Contents Introduction . 1-1 1.1 Primary Functions and Applications. 1-2 TCM38C17 TCM38C17 EVM. 2-1 2.1 Basic Components of EVM . 2-2 Interfaces . 3-1 3.1 SLIC Card I/O Interface . 3-2 3.2 Power-Supply Interface . 3-4 3.3 PCM4 Test-Equipment Interface. 3-4 3.3.1 3.3.2 Digital Interface to the PCM4.3-5 Analog Interface to the PCM4.3-6 Switches, Jumpers, and Test Points . 4-1 4.1 Switch SW6 (Reset Switch) . 4-2 4.2 Switch SW7 . 4-2 4.3 Jumpers. 4-3 4.4 Test Points . 4-3 EVM Configurations When Used With the PCM4 . 5-1 5.1 TCM38C17 TCM38C17 EVM Stand-Alone Testing (No SLIC EVM Cards Attached) . 5-2 5.2 TCM38C17 TCM38C17 EVM Testing (With SLIC EVM Cards Installed). 5-5 Example Test Scenario. 6-1 6.1 Example Test Scenario. 6-2 Printed-Circuit-Board (PCB) Construction . 7-1 7.1 PCB Construction . 7-2 7.2 Bypass Capacitors. 7-2 v Appendix TCM38C17 TCM38C17 EVM Board Layout.A-1 TCM38C17 TCM38C17 EVM Connections to the PCM4.B-1 PCM4 General Parameters Configuration .C-1 DSP Starter-Kit Interface .D-1 Test Points . E-1 Schematics and Bill of Material . F-1 References .G-1 vi Figures Figure 1. TCM38C17 TCM38C17 EVM Block Diagram. 2-2 Figure 2. Switch Definitions (SW7). 4-2 Figure 3. Mode A32 Variable Gain Versus Frequency Expected Test Results, Analog-to-Digital Operation . 5-3 Figure 4. Mode A32 Variable Gain Versus Frequency Expected Test Results, Digital-to-Analog Operation . 5-3 Figure 5. Mode A32 Variable Gain Versus Frequency Expected Test Results, Analog-to-Analog Operation . 5-3 Figure 6. Mode A55 Total Distortion Versus Signal-Level Expected Test Results, Analog-to-Digital Operation . 5-4 Figure 7. Mode A55 Total Distortion Versus Signal-Level Expected Test Results, Digital-to-Analog Operation . 5-4 Figure 8. Mode A55 Total Distortion Versus Signal-Level Expected Test Results, Analog-to-Analog Operation . 5-4 Figure 9. Mode A32 Variable Gain Versus Frequency Expected Test Results, Digital-to-Analog Operation . 6-4 Figure 10. Mode A44 Variable Gain Versus Signal-Level Expected Test Results, Digital-to-Analog Operation . 6-4 Figure 11. Mode A55 Total Distortion Versus Signal-Level Expected Test Results, Digital-to-Analog Operation . 6-4 Figure 12. TCM38C17 TCM38C17 EVM Board Layout. A-2 Figure 13. TCM38C17 TCM38C17 EVM Connections to PCM4 (Stand-Alone Testing). B-3 Figure 14. TCM38C17 TCM38C17 EVM Connections to PCM4 (With SLIC EVM Card Connected) . B-4 Figure 15. C5402 C5402 DSK and TCM38C17 TCM38C17 EVM Interconnection . D-3 vii Tables Table 1. SLIC I/O Connector Terminal Assignments (J1­J4) . 3-3 Table 2. Power-Supply Interface Connectors . 3-4 Table 3. PCM4 Digital Interface to the TCM38C17 TCM38C17 EVM . 3-5 Table 4. PCM4 Digital Test-Equipment Interface. 3-5 Table 5. CH0 PCM4 Analog Interface . 3-6 Table 6. CH1 PCM4 Analog Interface . 3-6 Table 7. CH2 PCM4 Analog Interface . 3-7 Table 8. CH3 PCM4 Analog Interface . 3-7 Table 9. Switch SW7-7 and SW7-8 Configurations. 4-3 Table 10. Jumper Configuration Matrix. 4-4 Table 11. Required Hardware Configuration for TCM38C17 TCM38C17 EVM Stand-Alone Testing With PCM4 . 5-2 Table 12. Required Hardware CH0 Configuration With SLIC EVM Card Attached . 5-6 Table 13. Required Hardware CH1 Configuration With SLIC EVM Card Attached . 5-6 Table 14. Required Hardware CH2 Configuration With SLIC EVM Card Attached . 5-7 Table 15. Required Hardware CH3 Configuration With SLIC EVM Card Attached . 5-7 Table 16. TCM38C17 TCM38C17 Channel as Seen by PCM4.B-2 Table 17. General Parameter Settings on the PCM4 .C-2 Table 18. DSK Connector Terminal Assignment (J22).D-4 Table 19. Test Points. E-2 viii Chapter 1 Introduction The QComboTM TCM38C17 TCM38C17 is a four-channel single-chip pulse-code modulated (PCM) codec with voice-band filters. It performs the transmit encoding (ADC conversion) and receive decoding (DAC conversion), as well as the transmit and receive filtering functions required to meet CCITT G.711 and G.714 specifications in a PCM system. This chapter contains an introduction to the TCM38C17 TCM38C17 evaluation module (EVM) used to evaluate the operation of the TCM38C17 TCM38C17. Topic 1.1 Introduction Page 1-2 1-1 Introduction 1.1 Primary Functions and Applications The TCM38C17 TCM38C17 evaluation module (EVM) provides a way to evaluate the operation of the TCM38C17 TCM38C17 quad combo, as well as evaluating the device with up to four subscriber line interface circuit (SLIC) evaluation cards. With the SLIC cards, the operation of the EVM provides a way to demonstrate the device in a line card application. The TCM38C17 TCM38C17 is a four-channel PCM codec with voice band filters. It performs transmit encoding (analog-to-digital conversion) and receive decoding (digital-to-analog conversion), as well as filtering functions required to meet CCITT G.711 and G.714 specifications in a PCM system. Each channel provides all the functions required to interface a full-duplex, four-line voice telephone circuit, with a time-division multiplexed system. The TCM38C17 TCM38C17 is specifically designed for fixed data-rate applications. Primary applications for the TCM38C17 TCM38C17 include digital transmission and switching of E1 carrier, PABX and central office telephone systems, and subscriber-line concentrators. The TCM38C17 TCM38C17 serves as the analog termination of a PCM line or trunk to the POTS local-loop line. Other applications include any PCM digital-audio interface that can benefit from the reduced footprint of a quadruple codec configuration and single-rail operation. 1-2 Chapter 2 TCM38C17 TCM38C17 EVM The TCM38C17 TCM38C17 EVM provides the user with the ability to evaluate and demonstrate the operation of the QCombo TCM38C17 TCM38C17 using several methods, which include: Y Y Y 1-to-4 SLIC cards Analog signal generator and TCM38C17 TCM38C17 in digital loopback Wandel and Golterman PCM4 channel measuring set Topic 2.1 Basic Components of EVM Page 2-2 2-1 TCM38C17 TCM38C17 EVM 2.1 Basic Components of EVM See appendix A for the board layout of the EVM (see Figure 12). The basic components making up the EVM include the TCM38C17 TCM38C17, a field-programmable gate array (FPGA), an oscillator, a power supervisor, configuration switches, test points, diagnostic LEDs, and interface connectors. Figure 1 shows a block diagram of the TCM38C17 TCM38C17 EVM. Audio In (CH0) Audio Out (CH0) Audio In (CH1) Audio Out (CH1) TCM38C17 TCM38C17 Audio In (CH2) Audio Out (CH2) Audio In (CH3) Audio Out (CH3) 2.048 MHz oscillator PCM In/Out PCM4 I/O 2.048 MHz CLK FPGA Control DSP Starter Kit I/O 5V Power Supervisor Power On Reset Reset Figure 1. TCM38C17 TCM38C17 EVM Block Diagram The FPGA provides timing for the frame synchronization, clocking and control of the PCM4, and optional DSP starter kit (DSK). This FPGA is not a standard requirement when designing with the TCM38C17 TCM38C17. It is used to interface with the PCM4 test equipment, as well as the DSK, both of which have different interface requirements. 2-2 Chapter 3 Interfaces The TCM38C17 TCM38C17 EVM consists of the following interfaces to external hardware: Y Y Y SLIC card I/O interface Power-supply interface PCM4 test-equipment interface Topic Page 3.1 SLIC I/O Interface 3-2 3.2 Power-Supply Interface 3-4 3.3 PCM4 Test-Equipment Interface 3-4 3-1 Interfaces 3.1 SLIC Card I/O Interface The SLIC card I/O interface consists of four 64-terminal connectors designated J1 through J4, allowing connection to four independent SLIC cards. The interface connectors (J1­J4) have the terminal assignments shown in Table 1. On the TCM38C17 TCM38C17, J1 is assigned to channel 0, J2 is assigned to channel 1, J3 is assigned to channel 2, and J4 is assigned to channel 3. As an example, this user's guide refers to interfacing to the IntersilTM HC5514x SLIC EVM. Any other SLIC EVM with a compatible interface can be attached to the SLIC card I/O interface. 3-2 Interfaces Table 1. SLIC I/O Connector Terminal Assignments (J1­J4)R Location Terminal Name Location Terminal Name A1 A2 A3 A4 A5 A6 A7 PWRO+ GSR PWRO­ B1 B2 B3 B4 B5 B6 B7 AGND AGND AGND AGND B8 B9 ­ B10 ­ B11 B12 B13 B14 B15 B16 ­ ­ ­ B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 A28 ­ B28 ­ A29 A30 A31 A32 ­ B29 B30 B31 B32 ­ A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 ­ ­ ­ ­ AUX0 AUX1 Reserved for 5-V digital power ­48 V ­24 V 5-V analog 5-V analog ­ ­ ­ ­ CLKX ­ FSX ­ TDX ­ ­ ­ ­ ANIN­ GSX ­ ­ ­ ­ ­ ­ ­ ­ ­ Reserved for DGND Reserved for DGND Reserved for DGND Reserved for DGND Reserved for DGND Reserved for DGND Reserved for DGND Reserved for DGND ­ ­ AGND AGND AGND Terminal assignments shown are with respect to the TCM38C17 TCM38C17 EVM. The interface consists of the analog inputs and outputs from the TCM38C17 TCM38C17, along with power (5-V dc, ­48-V dc, and ­24-V dc). Both the TCM38C17 TCM38C17 EVM and the HC5514x SLIC EVM contain footprints for gain-setting resistors for both the analog input and output of the TCM38C17 TCM38C17. When using the TCM38C17 TCM38C17 EVM with the SLIC EVM, the gain-setting resistors that exist on the TCM38C17 TCM38C17 EVM must either be removed or shorted. See Tables 12­15 for the required hardware configuration. 3-3 Interfaces Note that terminals B18 through B25 are connected together on each SLIC interface connector on the TCM38C17 TCM38C17 EVM, but are not tied to digital ground. Also note that the AUX0, AUX1, CLKX, FSX, and TDX signals are routed to each SLIC connector (J1­J4), but are not currently used. 3.2 Power-Supply Interface External power-supplies are required to supply power to the TCM38C17 TCM38C17 EVM. The power-supply interface consists of banana jacks. The power to the SLIC EVM is provided via these banana jacks as well. Power-supply jacks are provided for 5-V analog power, 5-V digital power, ­24-V power, and ­48-V power, along with analog and digital grounds. Table 2 lists the power-supply input connectors on the TCM38C17 TCM38C17 EVM. Table 2. Power Power-Supply Interface Connectors Connector Reference Designator 5-V digital J16A Required by TCM38C17 TCM38C17 and digital circuits Digital ground J16B TCM38C17 TCM38C17 and digital circuits 5-V analog J15A TCM38C17 TCM38C17 and SLICs Analog ground J15B TCM38C17 TCM38C17 and SLICs ­24 V J18A SLICs ­24-V ground J18B SLICs ­48 V J19A SLICs ­48-V ground J19B SLICs The ­48-V and ­24-V power supplies are only required by the SLIC EVM. When using the TCM38C17 TCM38C17 EVM in stand-alone mode, the ­24-V and ­48-V power supplies can be omitted. Separate analog and digital power and ground planes exist on the TCM38C17 TCM38C17 EVM. Jumper JP7 allows the connection of the analog and digital ground planes. 3.3 PCM4 Test-Equipment Interface The TCM38C17 TCM38C17 EVM allows communication and interaction with the PCM4 channel measuring set. The information provided explains how to connect the TMC38C17 TMC38C17 EVM to the PCM4 and general parameter setups, but does not provide a tutorial on how to operate the PCM4. Appendix B contains information explaining the physical connections between the PCM4 and the TCM38C17 TCM38C17 EVM, including the setup of the general parameters in the PCM4. There are two ways in which the PCM4 can be utilized in testing of the TCM38C17 TCM38C17 EVM: Y Y 3-4 TCM38C17 TCM38C17 EVM as a stand-alone EVM TCM38C17 TCM38C17 EVM connected to the SLIC EVMs Interfaces In the configuration where the TCM38C17 TCM38C17 EVM is being evaluated without the Intersil SLIC EVMs, the analog and digital I/O PCM4 test-equipment interfaces allow the user to: Y Y Provide and receive four-wire analog voice band signals to each of the four channels Transmit and receive digital PCM data from the TCM38C17 TCM38C17 In the configuration where the TCM38C17 TCM38C17 EVM is being evaluated with the SLIC EVMs, the PCM4 digital interface is used. The SLIC EVM is configured for two-wire loopback. The analog input on the PCM4 can be used, but it requires a connection directly to the SLIC EVM. Note: In either case, the TCM38C17 TCM38C17 EVM push-button reset switch must be pressed after the PCM4 clocks (8 kHz and 2.048 MHz) have been connected to the TCM38C17 TCM38C17 EVM and power has been applied. The TCM38C17 TCM38C17 EVM synchronizes its frame synchronization signals with the applied clocks. If the clocks are not present when power is applied, the TCM38C17 TCM38C17 device holds all channels in the power-down state. 3.3.1 Digital Interface to the PCM4 The digital interface to the PCM4 is described in Table 3 Table 3. PCM4 Digital Interface to the TCM38C17 TCM38C17 EVM Connector Reference Designator Function Connector Type Direction (with respect to the EVM) J9 2.048-MHz master clock input BNC Input J10 8-kHz synchronization input BNC Input J11 PCM data in BNC Input J12 PCM data out BNC Output These signals are at TTL levels. The PCM data output from the TCM38C17 TCM38C17 EVM is capable of driving a 50-b line. In addition to the BNC connectors that connect directly to the PCM4, a separate digital test-equipment interface (J14) exists to evaluate the digital PCM data signals, clock, and frame synchronizations received from, or applied to, the PCM4. The digital test-equipment interface allows easy connection to a logic analyzer or scope for evaluation purposes. The terminal assignment on the digital test-equipment interface (J14) is shown in Table 4. Table 4. PCM4 Digital Test-Equipment Interface Terminal Number J14 Signal/Function 1 2.048-MHz clock from the PCM4 2 TCM38C17 TCM38C17 frame synchronization for channel 0 3 TCM38C17 TCM38C17 frame synchronization for channel 1 4 TCM38C17 TCM38C17 frame synchronization for channel 2 5 TCM38C17 TCM38C17 frame synchronization for channel 3 6 PCM data input to TCM38C17 TCM38C17 7 PCM data output from TCM38C17 TCM38C17 (after line driver) 3-5 Interfaces 3.3.2 Analog Interface to the PCM4 The analog interface to the PCM4 is described in Tables 5 through 8. The analog interface of the PCM4 is used for testing when the TCM38C17 TCM38C17 EVM is not connected to the Intersil SLIC EVM cards. Note that there is only one analog channel interface to the PCM4. Therefore, only one set of analog I/O connectors on the TCM38C17 TCM38C17 EVM (J5A­J5E, for example) can be attached to the PCM4 at any given time. Table 5. Connector Reference Designator CH0 PCM4 Analog Interface Function Connector Type Direction (with respect to the EVM) J5A AGND Banana jack Input/output J5B Negative analog input for TCM38C17 TCM38C17 CH0 Positive analog input for TCM38C17 TCM38C17 CH0, connected on board to the 2.375-V AREF signal. Provides reference voltage to PCM4. Banana jack Input Banana jack Input/output J5D Positive analog output from TCM38C17 TCM38C17 CH0 Banana jack Output J5E Negative analog output from TCM38C17 TCM38C17 CH0 Banana jack Output J5C Table 6. Connector Reference Designator CH1 PCM4 Analog Interface Function Connector Type Direction (with respect to the EVM) J6A Banana jack Input Negative analog input for TCM38C17 TCM38C17 CH1 Banana jack Input J6C Positive analog input for TCM38C17 TCM38C17 CH1, connected on board to the 2.375-V AREF signal. Provides reference voltage to PCM4. Banana jack Input/output J6D Positive analog output from TCM38C17 TCM38C17 CH1 Banana jack Output J6E 3-6 AGND J6B Negative analog output from TCM38C17 TCM38C17 CH1 Banana jack Output Interfaces Table 7. Connector Reference Designator CH2 PCM4 Analog Interface Function Direction Connector Type (with respect to the EVM) J7A AGND Banana jack Input J7B Negative analog input for TCM38C17 TCM38C17 CH2 Banana jack Input J7C Positive analog input for TCM38C17 TCM38C17 CH2, connected on board to the 2.375-V AREF signal. Provides reference voltage to PCM4. Banana jack Input/output J7D Positive analog output from TCM38C17 TCM38C17 CH2 Banana jack Output J7E Negative analog output from TCM38C17 TCM38C17 CH2 Banana jack Output Table 8. Connector Reference Designator CH3 PCM4 Analog Interface Function Connector Type Direction (with respect to the EVM) J8A AGND Banana jack Input J8B Negative analog input for TCM38C17 TCM38C17 CH3 Positive analog input for TCM38C17 TCM38C17 CH3, connected on board to the 2.375-V AREF signal. Provides reference voltage to PCM4. Banana jack Input Banana jack Input/output J8D Positive analog output from TCM38C17 TCM38C17 CH3 Banana jack Output J8E Negative analog output from TCM38C17 TCM38C17 CH3 Banana jack Output J8C 3-7 Interfaces 3-8 Chapter 4 Switches, Jumpers, and Test Points Topic Page 4.1 Switch SW6 (Reset Switch) 4-2 4.2 Switch SW7 4-2 4.3 Jumpers 4-3 4.4 Test Points 4-4 4-1 Switches, Jumpers, and Test Points 4.1 Switch SW6 (Reset Switch) Switch SW6 is the board reset switch. Pressing this switch resets the FPGA logic, as well as the TCM38C17 TCM38C17. Resetting the board after power is applied is required. This is to allow the EVM and any external test equipment, or DSK that might be attached, to synchronize. Pushing the reset switch does not download the FPGA program from the PROM to the FPGA. Pushing the reset switch resets the logic in the FPGA to a known state. To download the FPGA program, the power to the EVM must be cycled. 4.2 Switch SW7 There are several configuration switches available on the TCM38C17 TCM38C17 EVM. They are located in the dipswitch with reference designator SW7. Figure 2 defines the switch settings. GND (closed) SW7 VCC (Open) 10 9 8 7 6 5 4 3 2 1 PCM4 Select (active low) Loopback Select (active low) Time slot Select MSB Time slot Select LSB A-law select (active low) Not used Ch3 power down (active low) Ch2 power down (active low) Ch1 power down (active low) Ch0 power down (active low) ON Identifies default setting Figure 2. Switch Definitions (SW7) Selecting PCM4 operation (by setting switch 10 on SW7 to the grounded position) allows clocking and frame synchronization signals to be generated from the clocks provided by the PCM4. This allows the TCM38C17 TCM38C17 EVM to operate correctly with the PCM4 test equipment. When switch 10 on SW7 is set to the VCC position, the EVM operates correctly with the C5402 C5402 DSK. An onboard clock oscillator provides the master clock in this case. Selecting loopback operation, by setting switch 9 on SW7 to the grounded position, allows the digital output of the TCM38C17 TCM38C17 to loop back to the digital input of the TCM38C17 TCM38C17. This allows an analog input to be provided by the PCM4 and allows the PCM4 to evaluate the same signal on the analog output. When switch 9 on SW7 is set to the VCC position, normal operation occurs. Setting switches 7 and 8 on SW7 configures the channel on the TCM38C17 TCM38C17 that transmits or receives conversion data first. Table 9 defines the switch settings. 4-2 Switches, Jumpers, and Test Points Table 9. Switch SW7-7 and SW7-8 Configurations Switch First Channel to Communicate SW7-8 (MSB) SW7-7 (LSB) 0 0 Channel 0 (default) 0 1 Channel 1 1 0 Channel 2 1 1 Channel 3 Switch 6 on SW7 selects either A-law companding when grounded or µ-law companding when set high. Switch 5 on SW7 is not used. Switches 1­4 set the selected channel into a power-down state when the switch is grounded. Setting switches 1­4 to VCC configures all channels on the TCM38C17 TCM38C17 to the operating mode. 4.3 Jumpers The TCM38C17 TCM38C17 EVM uses many jumpers. Table 10 describes the function of the jumpers and the default settings. 4-3 Switches, Jumpers, and Test Points Table 10. Jumper Configuration Jumper Configuration Matrix Function Terminal 1 to terminal 2 FPGA PROM is installed. FPGA is operational when power is applied. No download required. OpenR CH0 analog-output gain setting resides on the SLIC EVM. Closed CH0 analog-output gain is set to unity gain. CH1 analog-output gain setting resides on the SLIC EVM. Closed CH1 analog-output gain is set to unity gain. OpenR CH2 analog-output gain setting resides on the SLIC EVM. Closed CH2 analog-output gain is set to unity gain. OpenR CH3 analog-output gain setting resides on the SLIC EVM. Closed CH3 analog-output gain is set to unity gain. OpenR TCM38C17 TCM38C17 digital input and output are not shorted. Shunted TCM38C17 TCM38C17 digital data output is shorted to TCM38C17 TCM38C17 digital data input (loopback). Open Separates analog and digital grounds ShuntedR Connects analog and digital grounds OpenR DSK and EVM 5-V supplies are separate. Shunted Allows DSK to provide 5-V digital power to the EVM OpenR DSK and EVM 5-V supplies are separate. Shunted JP2 Terminal 2 to terminal 3R OpenR JP1 FPGA download pod is installed, requiring FPGA code to be downloaded from external PC. Allows DSK to provide 5-V digital power to the EVM JP3 JP4 JP5 JP6 JP7 JP8 JP9 Default setting 4.4 Test Points Various test points and test connectors are available on the TCM38C17 TCM38C17 EVM. These are provided to allow easy access to signals that can be observed via a scope or logic analyzer. Appendix E lists the test point number and signal provided in Table 19. In addition, ground points are conveniently scattered around the board to provide a place to connect a test-equipment ground lead. Points are also provided to measure the power-supply voltages. 4-4 Chapter 5 EVM Configurations When Used With the PCM4 This chapter describes two different hardware configurations used with the TCM38C17 TCM38C17 EVM and the PCM channel measuring set. Topic Page 5.1 TCM38C17 TCM38C17 EVM Stand-Alone Testing (No SLIC EVM Cards Attached) 5-2 5.2 TCM38C17 TCM38C17 EVM Testing (With SLIC EVM Cards Installed) 5-5 5-1 EVM Configurations When Used With the PCM4 5.1 TCM38C17 TCM38C17 EVM Stand-Alone Testing (No SLIC EVM Cards Attached) Table 11 shows the hardware configuration that must be present on the TCM38C17 TCM38C17 EVM for stand-alone testing. Both analog and digital testing can be performed. When the TCM38C17 TCM38C17 EVM is used for stand-alone testing, the PCM4 channel measuring set is configured for a 600-b analog input and output impedance and the analog transmit level must be adjusted to ­6 dBr. The analog transmit level is changed by pressing the "send dBr" button on the right side of the PCM4 face plate. This prevents the PCM4 from overdriving the TCM38C17 TCM38C17 analog inputs. Table 11. Required Hardware Configuration for TCM38C17 TCM38C17 EVM Stand-Alone Testing With PCM4 Required Configuration Channel 0 testing Channel 1 testing Channel 2 testing Channel 3 testing Notes R19 and R20 installed (10 kb, each) Input gain setting JP2 shorted Maximum gain on output R16 and R21 installed (10 kb, each) Input gain setting JP3 shorted R17 and R23 installed (10 kb, each) Maximum gain on output Input gain setting JP4 shorted Maximum gain on output R18 and R22 installed (10 kb, each) JP5 shorted Input gain setting Maximum gain on output When using the PCM4 channel measuring set with the TCM38C17 TCM38C17 EVM as a stand-alone system, several types of tests can be conducted (see Figure 13 in appendix B that shows the proper test connections of the PCM4 to TCM38C17 TCM38C17 EVM). These tests include analog-to-digital testing, digital-to-analog testing and analog-to-analog testing. A brief description of each of these follows: Y Y Y Analog-to-digital (A-D) (see Figures 3 and 6): the PCM4 provides an analog signal into a specific channel's voiceband analog input. The codec (TCM38C17 TCM38C17) converts this signal to digital. The PCM4 evaluates the digital results. Digital-to-analog (D-A) (see Figures 4 and 7): the PCM4 provides a digital representation of a voiceband signal into a specific time slot in the PCM stream that is input to the codec (TCM38C17 TCM38C17). The codec converts this signal to analog and presents it on the specific channel's analog output. The PCM4 evaluates the voiceband analog result. Analog-to-analog (A-A) (see Figures 5 and 8): the PCM4 provides an analog signal into a specific channel's voiceband analog input. The codec (TCM38C17 TCM38C17) converts this signal to digital and provides it in the specific channel on the PCM output of the device. With the loopback switch on the EVM configured for loopback operation, this digital representation of the signal provided via the PCM output is routed back to the PCM input on the TCM38C17 TCM38C17. The TCM38C17 TCM38C17 converts this digital signal to analog and presents it on the specific channel's analog output. The PCM4 evaluates the voiceband analog result. Examples of the expected results for A-D, D-A, and A-A testing using mode list A, test number 32 (variation of gain with frequency) and mode list A, test number 55 (total distortion) for a standalone TCM38C17 TCM38C17 connected to the PCM4 are shown in Figures 3­8. 5-2 EVM Configurations When Used With the PCM4 Figure 3. Figure 4. Figure 5. Mode A32 Variable Gain Versus Frequency Expected Test Results, Analog-to-Digital Operation Mode A32 Variable Gain Versus Frequency Expected Test Results, Digital-to-Analog Operation Mode A32 Variable Gain Versus Frequency Expected Test Results, Analog-to-Analog Operation 5-3 EVM Configurations When Used With the PCM4 Figure 6. Figure 7. Figure 8. 5-4 Mode A55 Total Distortion Versus Signal-Level Expected Test Results, Analog-to-Digital Operation Mode A55 Total Distortion Versus Signal-Level Expected Test Results, Digital-to-Analog Operation Mode A55 Total Distortion Versus Signal-Level Expected Test Results, Analog-to-Analog Operation EVM Configurations When Used With the PCM4 5.2 TCM38C17 TCM38C17 EVM Testing (With SLIC EVM Cards Installed) A different hardware configuration is required when testing with the PCM4 channel measuring set while the SLIC EVM cards are connected to TCM38C17 TCM38C17 EVM. The analog input and output gain-setting resistors reside on the SLIC EVM card, so the TCM38C17 TCM38C17 EVM must be modified. The required hardware configuration is described in Tables 12 through 15. The TCM38C17 TCM38C17 EVM's default configuration expects that SLIC EVM cards are connected. The simplest testing that can be performed is digital-to-digital testing, where the SLIC EVM card is configured for two-wire loopback. The PCM4 provides the digital PCM data to the appropriate channel on the TCM38C17 TCM38C17 and evaluates the PCM data from that same channel, while the SLIC is in two-wire loopback. Two-wire loopback occurs on the HC5514 HC5514 EVM when the C1­C3 configuration switches are set as: Y Y Y C1: high C2: high C3: low Two-wire loopback is considered analog loopback to this test. Analog testing with the PCM4 can only be performed when the PCM4 is evaluating the analog output of the SLIC (analog input to the TCM38C17 TCM38C17). In terms of the PCM4, this type of testing is considered digital-to-analog testing. The PCM4 provides the digital PCM data to the TCM38C17 TCM38C17 and evaluates the four-wire analog output of the SLIC when the SLIC is in a two-wire loopback mode. Because the input gain-setting resistors reside on the SLIC EVM card and the banana jacks that connect to the PCM4 reside on the TCM38C17 TCM38C17 EVM (after the gain-setting resistors), the connection to the PCM4 must be made to a test point on the SLIC EVM card. The positive and ground jacks from the PCM4 must both connected to the analog ground jack on the TCM38C17 TCM38C17 EVM. However, the PCM4 negative input should be connected to a point before the gain-setting resistors, which is located at test-point TP8 on the SLIC EVM card. By making the above connections, the PCM4 can be used to run digital-to-analog tests. For both digital-to-digital and digital-to-analog testing, the transmit and receive time slots must be set to the same time slot on the PCM4 (see Table 16 in appendix B). When performing tests with the SLIC EVM cards installed, the required hardware configuration is described in Tables 12 through 15. Refer to Figure 14 in appendix B showing the proper connection of the PCM4 and the TCM38C17 TCM38C17 EVM. Note: The analog input impedance on the PCM4 must be set to >30 kb for the tests to provide correct results. The analog output impedance is of no consequence and is not used. 5-5 EVM Configurations When Used With the PCM4 Table 12. Required Hardware CH0 Configuration With SLIC EVM Card Attached TCM38C17 TCM38C17 EVM Required Configuration R19 shorted (default) R20 removed (default) JP2 OPEN (default) Channel 0 testing PCM4 negative input is driven by SLIC EVM card. TCM38C17 TCM38C17 analog output is not used. Required Hardware CH1 Configuration With SLIC EVM Card Attached TCM38C17 TCM38C17 EVM Required Configuration R16 removed (default) R21 shorted (default) JP3 OPEN (default) Channel 1 testing Notes Gain-setting resistors on TCM38C17 TCM38C17 EVM are bypassed. Gain-setting resistors are present on SLIC EVM card. PCM4 positive input connects to J6C (2.375-V AREF) PCM4 GND connects to J6A. PCM4 negative input connects to TP8 on SLIC EVM. J6B, J6D, J6E not connected 5-6 Gain-setting resistors are present on SLIC EVM card. PCM4 positive input connects to J5C (2.375-V AREF). PCM4 GND connects to J5A. PCM4 negative input connects to TP8 on SLIC board. J5B, J5D, J5E not connected Table 13. Notes Gain-setting resistors on TCM38C17 TCM38C17 EVM are bypassed. PCM4 negative input is driven by SLIC EVM card. TCM38C17 TCM38C17 analog output is not used. EVM Configurations When Used With the PCM4 Table 14. Required Hardware CH2 Configuration With SLIC EVM Card Attached TCM38C17 TCM38C17 EVM Required Configuration R17 removed (default) R23 shorted (default) JP4 OPEN (default) Channel 2 testing Gain-setting resistors are present on SLIC EVM card. PCM4 positive input connects to J7C (2.375-V AREF). PCM4 GND connects to J7A. PCM4 negative input connects to TP8 on SLIC EVM. J7B, J7D, J7E not connected Table 15. Notes Gain-setting resistors on TCM38C17 TCM38C17 EVM are bypassed. PCM4 negative input is driven by SLIC EVM card. TCM38C17 TCM38C17 analog output is not used. Required Hardware CH3 Configuration With SLIC EVM Card Attached TCM38C17 TCM38C17 EVM Required Configuration R18 removed (default) R22 shorted (default) JP5 open (default) Channel 3 testing Notes Gain-setting resistors on TCM38C17 TCM38C17 EVM are bypassed. Gain-setting resistors are present on SLIC EVM card. PCM4 positive input connects to J8C (2.375-V AREF). PCM4 GND connects to J8A. PCM4 negative input connects to TP8 on SLIC EVM. J8B, J8D, J8E not connected PCM4 negative input is driven by SLIC EVM card. TCM38C17 TCM38C17 analog output is not used. 5-7 EVM Configurations When Used With the PCM4 5-8 Chapter 6 Example Test Scenario This chapter describes an example test procedure. Topic 6.1 Example Test Scenario Page 6-2 6-1 Example Test Scenario 6.1 Example Test Scenario The following procedure describes an example test scenario with the TCM38C17 TCM38C17 EVM, a single HC5514x SLIC EVM card, and the PCM4 channel measuring set. 1) Connect the TCM38C17 TCM38C17 EVM channel 0 (J1) to the SLIC EVM channel 0 card. 2) Set the configuration switches on the TCM38C17 TCM38C17 EVM as: Y Y Y Y Y Y Y Y Y Y SW7-10 SW7-10 closed (GND, PCM4 mode selected) SW7-9 open (high, loopback not selected) SW7-8 closed (GND, time slot MSB = 0) SW7-7 closed (GND, time slot LSB = 0) SW7-6 closed (GND, A-law selected) SW7-5 don't care, not used SW7-4 open (high, CH3 not powered down) SW7-3 open (high, CH2 not powered down) SW7-2 open (high, CH1 not powered down) SW7-1 open (high, CH0 not powered down) 3) Set the configuration switches on the SLIC EVM card as: Y Y Y C3: low C2: high C1: high 4) Verify that the jumpers on the TCM38C17 TCM38C17 EVM are configured: Y Y Y Y Y Y Y Y JP1: terminal 2 shunted to terminal 3 (FPGA PROM installed) JP2: open (gain-setting resistors on SLIC EVM) JP3: open (gain-setting resistors on SLIC EVM) JP4: open (gain-setting resistors on SLIC EVM) JP5: open (gain-setting resistors on SLIC EVM) JP6: open (external loopback not configured) JP7: shunted (analog and digital grounds connected) JP8 and JP9: open (power supplied by external power supplies) 5) Connect the TCM38C17 TCM38C17 EVM and SLIC EVM card to the PCM4 test equipment as shown in Figure 14 in appendix B. 6) Program the parameters in the PCM4 as described in Table 17 in appendix C. 6-2 Example Test Scenario 7) Connect power to the TCM38C17 TCM38C17 EVM (5-V analog, 5-V digital, ­48 V, ­24 V with grounds). 8) Apply power to the system (apply 5 V, then ­24 V and ­48 V). 9) All four of the channel power-down LEDs are illuminated, along with the PWR LED and the A-SEL LED. 10) Press the TCM38C17 TCM38C17 reset switch. The channel power-down LEDs turn off. The RSET LED illuminates when the reset switch is pressed. 11) Configure the PCM4 to evaluate time slot 0 for both the transmit and receive channels. 12) Select a test on the PCM4 (example, mode-A tests, test A32). Evaluate the results. Expected test results when performing digital-to-analog testing are shown in Figures 9, 10, and 11 for test modes A32, A44, and A55. 6-3 Example Test Scenario Figure 9. Mode A32 Variable Gain Versus Frequency Expected Test Results, Digital-to-Analog Operation Figure 10. Mode A44 Variable Gain Versus Signal-Level Expected Test Results, Digital-to-Analog Operation Figure 11. Mode A55 Total Distortion Versus Signal-Level Expected Test Results, Digital-to-Analog Operation 6-4 Chapter 7 Printed-Circuit-Board (PCB) Construction Topic Page 7.1 PCB Construction 7-2 7.2 Bypass Capacitors 7-2 7-1 Printed-Circuit-Board (PCB) Construction 7.1 PCB Construction The TCM38C17 TCM38C17 EVM PCB is constructed of four layers. The outer two layers are signal layers, while the inner two layers are power and ground planes. The power and ground layers are split planes. The power layer is split into analog and digital power planes. The ground layer is split into analog and digital ground planes. The analog circuitry and signals are located over the analog power and ground planes. The digital circuitry and signals are located over the digital power and ground planes. Because the TCM38C17 TCM38C17 device is a mixed-signal device, the analog and digital power/ground planes are located under the appropriate sections of the device. The split between the power planes occurs under the TCM38C17 TCM38C17. Splitting power and ground planes helps prevent digital noise currents from inducing noise into the analog ground of the TCM38C17 TCM38C17. For the best signal-to-noise ratio, it is recommended that the ground plane be split into separate analog and digital sections, joined together at a single point. This type of construction is used on the TCM38C17 TCM38C17 EVM. The joining of the power planes is accomplished via a jumper, JP7. 7.2 Bypass Capacitors Both low-frequency and high-frequency bypass capacitors are located at the 5-V analog and digital power inputs to the board. No bypass capacitors are present for the ­24-V or ­48-V supply inputs, since these inputs are rerouted directly to the SLIC interface connectors and are not used by circuitry on the TCM38C17 TCM38C17 EVM. Low-frequency and high-frequency bypass capacitors also are present at the analog and digital power-supply inputs to the TCM38C17 TCM38C17. A 0.1-«f capacitor is required on AREF (terminal 2) of the TCM38C17 TCM38C17. In addition, 1-«F ceramic capacitors are required on the REFLTR terminals (terminals 47 and 48). The FPGA U3 is heavily bypassed. There is one low-frequency bypass capacitor and two high-frequency bypass capacitors per side of the device. 7-2 Appendix A TCM38C17 TCM38C17 EVM Board Layout Topic A.1 TCM38C17 TCM38C17 EVM Board Layout Page A-2 A-1 TCM38C17 TCM38C17 EVM Board Layout A.1 TCM38C17 TCM38C17 EVM Board Layout The TCM38C17 TCM38C17 EVM board layout is shown in Figure 12. J9 J10 J11 J12 J2 JP3 J6A J6C J6B J6D J6E JP1 J5D JP2 J23 J5E J22 J14 J16B J15B J18B J19B J20B J21B JP9 J5A J1 J15A J18A J19A J20A J21A SW7 J16A JP8 J5C FPGA JP7 TCM38C17 TCM38C17 J5B JP6 J8B J8C J7B J8A J7C J7E J8E J8D J7D JP5 JP4 J4 Figure 12. TCM38C17 TCM38C17 EVM Board Layout A-2 J7A J3 Appendix B TCM38C17 TCM38C17 EVM Connections to the PCM4 Topic B.1 Physical Connections to the PCM4 Page B-2 B-1 TCM38C17 TCM38C17 EVM Connections to the PCM4 B.1 Physical Connections to the PCM4 Figure 13 describes the required physical connections between the TCM38C17 TCM38C17 EVM and the PCM4 equipment when testing the TCM38C17 TCM38C17 EVM as a stand-alone item (no SLIC EVM cards attached). The PCM4 only can test one channel at a time. Therefore, the analog connections to the PCM4 must be physically connected to a specific channel's analog interface on the TCM38C17 TCM38C17 EVM or SLIC EVM card to test that particular channel. Figure 14 describes the physical connections when a SLIC EVM card is attached. In addition, the PCM4 is a 32-channel, or time-slot, machine (when configured as all time slots assigned to telephone channels). The data for each TCM38C17 TCM38C17 channel communicates in a specific time slot, as shown in Table 16. Table 16. TCM38C17 TCM38C17 Channel as Seen by PCM4 TCM38C17 TCM38C17 Channel Time Slot as Seen by PCM4R CH0 0 CH1 8 CH2 CH3 16 24 This assumes that CH0 is configured as the first channel to communicate; SW7-7 and SW7-8 are set to GND. See description of switch SW7 settings in Figure 2 (chapter 4). . B-2 Printed-Circuit-Board (PCB) Construction EXT. FRAME (63) PCMIN (J11) PCMOUT (J12) 8KHz IN (J10) 2.048 MHz CLK (J9) CH0 ANIN- (J5B) AREF (J5C) (2.375 V) TX SIGNAL (21) RX SIGNAL (20) FRAME TRIGGER (61) TX CLOCK (22) + SEND TX (25) + - RECEIVE RX (23) GND CH0 PWR0+ (J5D) CH0 PWR0- (J5E) AN GND (J5A) CH1 ANIN- (J6B) AREF (J6C) (2.375 V) CH1 PWR0+ (J6D) CH1 PWR0- (J6E) AN GND (J6A) GND PCM4 Channel Measuring Set CH2 ANIN- (J7B) AREF (J7C) (2.375 V) CH2 PWR0+ (J7D) CH2 PWR0- (J7E) AN GND (J7A) CH3 ANIN- (J8B) AREF (J8C) (2.375 V) CH3 PWR0+ (J8D) CH3 PWR0- (J8E) AN GND (J8A) TCM38C17 TCM38C17 EVM Figure 13. TCM38C17 TCM38C17 EVM Connections to PCM4 (Stand-Alone Testing) B-3 TCM38C17 TCM38C17 EVM Connections to the PCM4 EXT. FRAME (63) PCMIN (J11) PCMOUT (J12) 8KHz IN (J10) 2.048 MHz CLK (J9) CH0 ANIN- (J5B, J1-A31 J1-A31) AREF (J5C) TX SIGNAL (21) RX SIGNAL (20) FRAME TRIGGER (61) TX CLOCK (22) + J1-A2 NC SEND TX (25) GND CH0 PWR0+ (J5D, J1-A1) CH0 PWR0- (J5E, J1-A3) AN GND (J5A, J1-B1) J1-A32 J1-A32 J1-A30 J1-A30 J1-B32 J1-B32 CH1 ANIN- (J6B, J2-A31 J2-A31) AREF (J6C) CH1 PWR0+ (J6D, J2-A1) CH1 PWR0- (J6E, J2-A3) AN GND (J6A, J2-B1) + SLIC EVM (in 2-wire loopback) VTX RECEIVE RX (23) GND PCM4 Channel Measuring Set CH2 ANIN- (J7B, J3-A31 J3-A31) AREF (J7C) CH2 PWR0+ (J7D, J3-A1) CH2 PWR0- (J7E, J3-A3) AN GND (J7A, J3-B1) CH3 ANIN- (J8B, J4-A31 J4-A31) AREF (J8C) CH3 PWR0+ (J8D, J4-A1) CH3 PWR0- (J8E, J4-A3) AN GND (J8A, J4-B1) TCM38C17 TCM38C17 EVM Figure 14. TCM38C17 TCM38C17 EVM Connections to PCM4 (With SLIC EVM Card Connected) B-4 Appendix C PCM4 General Parameters Configuration Topic C.1 PCM4 General Parameters Configuration Page C-2 C-1 PCM4 General Parameters Configuration C.1 PCM4 General Parameters Configuration Table 17 describes the general parameters that are set up on the PCM4 to communicate properly with the TCM38C17 TCM38C17 EVM. Table 17. General Parameter Settings on the PCM4 Setting Item Number (1) Digital configuration General configuration Digital loop (A-A) General Parameter TX/RX 2M/2Mbits/s selected 2 Mbits/s/all TS 11 21 (2) Frame selection TX frame type RX frame type CRC-4 multiframe All 32 TS teleph All 32 TS teleph Off 14 24 31 (3) Digital TX interface Line code Output impedance Clock NRZ 75 ohms unbalanced Int. 2048 kHz 13 22 31 (4) Digital RX interface Line code Input impedance NRZ 120/75 ohms 13 21 (5) Digital words in TX frame Frame words Send signal Reset to standard values In select channels 11 21 (6) TX error insertion Off 11 (7) PCM coding TX encoding law RX encoding law Must match switch S7-6 on TCM38C17 TCM38C17 EVM. Default setting on EVM is A-law. 11 to match EVM default Must match TX encoding law 21 to match EVM default (8) Scanner parameter VF-input number VF-output number 11 21 (9) Special parameter Level display Two-wire term Digital channel number C-2 1 1 dBm0 Infinite Time Slot 11 13 16 Appendix D DSP Starter-Kit Interface This chapter describes the EVM interface (J22) that allows a connection to the C5402 C5402 DSP starter kit (DSK) expansion port. This allows the user to develop software applications using the TCM38C17 TCM38C17 EVM. Topic D.1 DSK Interface Page D-2 D-1 DSP Starter-Kit Interface D.1 DSK Interface The ability to connect to a C5402 C5402 DSK is provided, but not used, on the TCM38C17 TCM38C17 EVM. The interface consists of a single 80-terminal surface-mount connector, J22 (not populated, Samtec part number TFM-140-32-S-D-LC TFM-140-32-S-D-LC), allowing connection to the C5402 C5402 DSK expansion-port interface. The DSK interface is provided for users that develop software applications for use with the TCM38C17 TCM38C17 EVM. The DSK interface is discussed, but no software examples are provided. Terminal 75 of the DSK interface connector (J22) has been intentionally grounded. It alerts the DSK that a daughter board is connected. It is recommended that the C5402 C5402 DSK not be used to power the TCM38C17 TCM38C17 EVM. However, there are two jumpers (JP8 and JP9) on the TCM38C17 TCM38C17 EVM that allow the DSK to supply the 5-V power to the EVM when they are shorted together. Open is the default configuration for these jumpers. Figure 15 shows the hardware configuration provided when DSK operation is used. DSK operation is configured when switch S7-10 S7-10 is not selecting PCM4 operation (SW7-10 SW7-10 is set to VCC, switch is open). The DSK interface connector (J22) has the terminal assignment shown in Table 18. DSK operation has the following features: Y Y Y Y Y D-2 PCM data output from the DSK drives the TCM38C17 TCM38C17 PCM input. PCM data output from the TCM38C17 TCM38C17 drives the DSK PCM input. Onboard 2.048-MHz oscillator drives the TCM38C17 TCM38C17 master clock (MCLK) input. Frame synchronization signals are synchronized with the 2.048-MHz MCLK and drive the DSK and the TCM38C17 TCM38C17. An 8-kHz output is provided. This 8-kHz signal is generated by the FPGA and is synchronized with the TCM38C17 TCM38C17 MCLK signal and the time-slot 0 frame synchronization signal. This provides an optional interrupt that drives the DSK interrupt input. DSP Starter-Kit Interface C5402 C5402 DSK TCM38C17 TCM38C17 EVM X_CLKX0 X_CLKR0 X_DX0 X_DR0 X_FSX0 X_FSR0 X_INT0# DB_DET# 21 J22-21 J22-21 27 J22-27 J22-27 24 J22-24 J22-24 30 J22-30 J22-30 23 J22-29 J22-29 53 J22-53 J22-53 75 J22-75 J22-75 PCMIN (PCM_FROM_DSK) PCMOUT (PCM_TO_DSK) J22-23 J22-23 29 2.048MHz CLK (SCLK_TO_DSK) Frame sync (DSK_FS) 8 kHz interrupt (DSK_8KHZ) DGND Figure 15. C5402 C5402 DSK and TCM38C17 TCM38C17 EVM Interconnection D-3 DSP Starter-Kit Interface Table 18. Terminal Signal Function on C5402 C5402 DSK 1 3 DSK Connector Terminal Assignment (J22) Signal Function on TCM38C17 TCM38C17 Terminal Signal Function on C5402 C5402 DSK Signal Function on TCM38C17 TCM38C17 12 V (not used) 5 7 2 12 V (not used) DGND 4 DGND 5 V from DSK DGND GND 6 8 5 V from DSK DGND 9 5 V from DSK 10 5 V from DSK 11 Not used 12 Not used 13 Not used 14 Not used 15 Not used 16 Not used 17 Not used 18 Not used 19 3.3 V (not used) 20 3.3 V (unused) 21 X_CLKX0 SCLK_TO_FS 22 Not used 23 X_FSX0 DSK_FS 24 DGND 26 25 27 X_CLKR0 SCLK_TO_FS X_FSR0 DSK_FS 30 PCM from DSK DGND 28 29 X_DX0 Not used X_DR0 PCM to DSK 31 DGND 32 DGND 33 Not used 34 Not used 35 37 Not used DGND 36 38 Not used DGND 39 Not used 40 Not used 41 Not used 42 Not used 43 DGND 44 DGND 45 Not used 46 Not used 47 Not used 48 Not used 49 Not used 50 Not used 51 DGND 52 DGND DSK8KHZ 54 Not used 55 Not used 56 Not used 57 Not used 58 Not used 59 Not used 60 Not used 61 DGND 62 DGND 63 Not used 64 Not used 65 67 Not used Not used 66 68 Not used Not used 69 Not used 70 Not used 71 Not used 72 Not used 53 X_INT0# 73 Not used 74 Not used DGND 76 DGND 77 DGND 78 Not used 79 DGND 80 DGND 75 D-4 DB_DET# Appendix E Test Points E-1 Test Points Table 19. Test Points Test Points Test Points Signal TP1 ANINO­ TP27 Not populated TP2 3FS TP28 Not populated TP3 N/A TP29 Not populated TP4 2FS TP30 Not populated TP5 0PWRO+ TP31 Not populated TP6 1FS TP32 Not populated TP7 0PWRO­ TP33 Not populated TP8 0FS TP34 Not populated TP9 ANIN1­ TP35 Not populated TP10 3PWRO­ TP36 Not populated TP11 N/A TP37 DGND TP12 3PWRO+ TP38 DGND TP13 1PWRO+ TP39 DGND TP14 N/A TP40 DGND TP15 1PWRO­ TP41 AGND TP16 ANIN3­ TP42 AGND TP17 ANIN2­ TP43 AGND TP18 2PWRO­ TP44 AGND TP19 N/A TP45 DGND TP20 2PWRO+ TP46 DGND TP21 C17_PCMOUT TP47 DGND TP22 C17_PCMIN TP48 DGND TP23 C17_MCLK TP49 5VANLG TP24 ­48VBAT 48VBAT TP50 5VDIG TP25 ­24VNBAT 24VNBAT TP51 AGND TP26 E-2 Signal Not populated TP52 AGND Appendix F Schematics and Bill of Material F-1 Schematics and Bill of Material F-2 Schematics and Bill of Material F-3 Schematics and Bill of Material F-4 Schematics and Bill of Material F-5 Schematics and Bill of Material F-6 Schematics and Bill of Material F-7 Schematics and Bill of Material F-8 Schematics and Bill of Material F-9 Schematics and Bill of Material Bill Of Material ITEM QTY 3 10 MFG MFG PART# Ref Des *AVX 08051C104JATMA 08051C104JATMA C19-C22 C19-C22,C26 * 13 VALUE or FUNCTION CAPACITOR,SMT0805 SMT0805 100v, 5%, 0.1uF CAPACITOR,SMT0805 SMT0805 100V, 5%, 0.01uF HEADER,2PIN HDR,W/SHUNT 2PIN .1SPC TERMINAL ASSEMBLYTESTPOINT SOCKET C30,C48,C49 * 4 DESCRIPTION C50,C51 AVX 08051C103JATMA 08051C103JATMA * C23,C24,C27 C31-C39 C31-C39,C52 27 8 AMP 103321-2 JP2-JP9 195 48 VERO 20-2136J 20-2136J TP1,TP2,TP4 * TP5-TP10 TP5-TP10,TP12 * TP13,TP15,TP16 * TP17,TP18,TP20 * TERMINAL ASSY AMP/531220-2 AMP/531220-2 TP21-TP52 TP21-TP52 593 2 KEMET T491C106K016AS T491C106K016AS C17,C47 CAPACITOR,SMT,TANT 10%, 16V,10.0uF 594 8 KEMET T491D226K020AS T491D226K020AS C41-C46 C41-C46,C53 CAPACITOR,SMT,TANT 10%, 20V, 22.0uF CAPACITOR,SMT0805 SMT0805 10V, 20%, 1.0uF CONN,THRU,64P CONN 64P INVERSE DIN FEMALE CONN,SMT,80P CONN,80P,2X40,SMT.05 X .0 CONNECTOR CONNECTOR, BANANA,FEMALE CONNECTOR CONN, BNC, COAX, FEMALE * C54 595 2 AVX 0805ZG105ZAT2A 0805ZG105ZAT2A C14,C15 596 4 3M 7164-50B2TH 7164-50B2TH J1-J4 597 1 SAMTEC TFM-140-32-S-D-LC TFM-140-32-S-D-LC 598 32 HHSMITH 101 J22 J5A,J5B,J5C * J5D,J5E,J6A * J6B,J6C,J6D * J6E,J7A,J7B * J7C,J7D,J7E * J8A,J8B,J8C * J8D,J8E,J15A * J15B,J16A,J16B * J18A,J18B,J19A * J19B,J20A,J20B * J21A,J21B 599 4 AMP 227161-1 J9-J12 J9-J12 600 1 SAMTEC TSM-104-01-T-DV TSM-104-01-T-DV J14 HEADER,2X4,.1CTR,SMT HEADER, 2X4, .1CTR,SMT 601 1 SAMTEC TSM-109-01-T-DV TSM-109-01-T-DV J23 HEADER 602 1 SAMTEC TSM-103-01-T-SV TSM-103-01-T-SV JP1 HEADER HEADER,MALE,3P,SMT 603 2 SAMTEC TSM-112-01-T-DV TSM-112-01-T-DV J13A,J13B HEADER HEADER,MALE,24PIN 24PIN,SMT,.1X 604 1 EPSON SG-531 SG-531 2.048MHz OSC1 IC,DIP,4P 2.048 MHz 605 1 TI TLC7705ID TLC7705ID U2 IC,SMT,8P uPOWER SUPPLY VOLTAGE SUP 606 1 TI SN74128N SN74128N U7 IC,DIP,300MIL 300MIL,14P 50 OHM LINE DRIVER F-10 HEADER,MALE,18P,SMT,.1X.2 AMP/50935/X14 AMP/50935/X14 Schematics and Bill of Material Bill Of Material (continued) ITEM QTY MFG MFG PART# Ref Des DESCRIPTION VALUE or FUNCTION 607 1 TI SN74ALS241CDW SN74ALS241CDW U5 IC,SOIC,20P OCTAL BUFFER AND LINE DRI 608 1 TI SN74ALS244CDW SN74ALS244CDW U6 IC,SOIC,20P 609 1 TI TCM38C17IDL TCM38C17IDL U1 IC,SMT,48P 610 1 XILINX XC4010E-4PQ208 XC4010E-4PQ208 U3 IC,SMT,208P 611 1 XILINX XC17256EPD8C XC17256EPD8C U4 IC,DIP,8P 612 7 DIALIGHT 521-9324 L0-L6 LED,T-1 OCTAL BUFFER AND LINE DRI QCOMBO 4 CHAN PCM COMBO XILINX FPGA SERIAL CONFIGURATION PROM RED,1mA 613 1 DALE CRCW080522R1F CRCW080522R1F R29 RESISTOR,SM,1/10w,1% 22.1 OHM 614 4 DALE CRCW08051002F CRCW08051002F R37-R40 R37-R40 RESISTOR,SM,1/10w,1% SOCKET 10.0K OHM 615 1 DALE CRCW08051003F CRCW08051003F R27 RESISTOR,SM,1/10w,1% 100K OHM 616 13 DALE CRCW08054751F CRCW08054751F R10-R15 R10-R15,R30 RESISTOR,SM,1/10w,1% 4.75K OHM 617 7 DALE CRCW12065110F CRCW12065110F R6-R9,R24,R25 RESISTOR,SMT,1/8w,1% AMP/50935/X8 AMP/50935/X8 * R31-R36 R31-R36 * 511 OHM R26 618 1 DALE CRCW12101003F CRCW12101003F R1 619 8 *DALE RN60C1002B RN60C1002B R16-R23 R16-R23 RESISTOR,SMT,1/4w,1% 100K OHM RESISTOR,1/4w,0.1% 10.0K OHM 620 1 C&K 8121SD9V3GE 8121SD9V3GE 621 1 C&K BD10 SW6 SWITCH,SPDT,PB SWITCH,SPDT,PUSH BUTTON SW7 SWITCH,DIP,20P DIP SWITCH 20P AUGAT/820AG11D AUGAT/820AG11D F-11 Schematics and Bill of Material F-12 Appendix G References TCM38C17IDL TCM38C17IDL QComboTM Four-Channel (Quad) PCM Combo data sheet, literature number SLWS040 SLWS040. HC5503PRC HC5503PRC SLIC and the Texas Instruments TCM38C17 TCM38C17 Quad Combo, literature number SLWA016 SLWA016. TCM38C17 TCM38C17 Quad Combo Design Considerations, literature number SLWA014 SLWA014. G-1