TC9400/9401/9402 TC9401 TC9400 TC9402 TC940X 10CREF IN914 TC9400A TC9401A - Datasheet Archive
Voltage-to-Frequency / Frequency-to-Voltage Converters Features: General Description: VOLTAGE-TO-FREQUENCY The TC9400/9401/9402
TC9400/9401/9402 TC9400/9401/9402 Voltage-to-Frequency / Frequency-to-Voltage Converters Features: General Description: VOLTAGE-TO-FREQUENCY The TC9400/9401/9402 TC9400/9401/9402 are low-cost Voltage-to-Frequency (V/F) converters, utilizing low-power CMOS technology. The converters accept a variable analog input signal and generate an output pulse train, whose frequency is linearly proportional to the input voltage. · Choice of Linearity: - TC9401 TC9401: 0.01% - TC9400 TC9400: 0.05% - TC9402 TC9402: 0.25% · DC to 100 kHz (F/V) or 1 Hz to 100 kHz (V/F) · Low Power Dissipation: 27 mW (Typ.) · Single/Dual Supply Operation: - +8V to +15V or ±4V to ±7.5V · Gain Temperature Stability: ±25 ppm/°C (Typ.) · Programmable Scale Factor FREQUENCY-TO-VOLTAGE · Operation: DC to 100 kHz · Choice of Linearity: - TC9401 TC9401: 0.02% - TC9400 TC9400: 0.05% - TC9402 TC9402: 0.25% · Programmable Scale Factor The devices can also be used as highly accurate Frequency-to-Voltage (F/V) converters, accepting virtually any input frequency waveform and providing a linearly proportional voltage output. A complete V/F or F/V system only requires the addition of two capacitors, three resistors, and reference voltage. Package Type 14-Pin Plastic DIP/CERDIP IBIAS 1 14 VDD ZERO ADJ 2 13 NC IIN 3 TC9400 TC9400 TC9401 TC9401 TC9402 TC9402 VSS 4 Applications: · · · · · · · Microprocessor Data Acquisition 13-bit Analog-to-Digital Converters (ADC) Analog Data Transmission and Recording Phase Locked Loops Frequency Meters/Tachometer Motor Control FM Demodulation VREFOUT 5 12 AMPLIFIER OUT THRESHOLD 11 DETECTOR 10 FREQ/2 OUT GND 6 9 OUTPUT COMMON VREF 7 8 PULSE FREQ OUT 14-Pin SOIC IBIAS 1 14 VDD ZERO ADJ 2 13 NC IIN 3 12 AMPLIFIER OUT VSS 4 11 THRESHOLD DETECTOR VREFOUT 5 10 FREQ/2 OUT GND 6 9 OUTPUT COMMON VREF 7 8 PULSE FREQ OUT TC9400 TC9400 TC9401 TC9401 TC9402 TC9402 NC = No Internal Connection © 2007 Microchip Technology Inc. DS21483D-page 1 TC9400/9401/9402 TC9400/9401/9402 Functional Block Diagram Integrator Capacitor Input Voltage Integrator Op Amp Threshold Detector One Shot RIN IIN Pulse Output ÷2 Reference Capacitor Pulse/2 Output TC9400 TC9400 IREF Reference Voltage DS21483D-page 2 © 2007 Microchip Technology Inc. TC9400/9401/9402 TC9400/9401/9402 1.0 ELECTRICAL CHARACTERISTICS Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings VDD VSS .+18V IIN .10 mA VOUTMAX VOUT Common.23V VREF VSS .-1.5V Storage Temperature Range.-65°C to +150°C Operating Temperature Range: C Device . 0°C to +70°C E Device.-40°C to +85°C Package Dissipation (TA 70°C): 8-Pin CerDIP .800 mW 8-Pin Plastic DIP .730 mW 8-Pin SOIC .470 mW TC940X TC940X ELECTRICAL SPECIFICATIONS Electrical Characteristics: unless otherwise specified, VDD = +5V, VSS = -5V, VGND = 0V, VREF = -5V, RBIAS = 100 k, Full Scale = 10 kHz. TA = +25°C, unless temperature range is specified (-40°C to +85°C for E device, 0°C to +70°C for C device). Parameter Min Typ Max Min Typ Max Min Typ Max Units Test Conditions Voltage-to-Frequency Accuracy TC9400 TC9400 TC9401 TC9401 TC9402 TC9402 Linearity 10 kHz - 0.01 0.05 - 0.004 0.01 - 0.05 0.25 % Output Deviation from Full Scale Straight Line Between Normalized Zero and Full Scale Input Linearity 100 kHz - 0.1 0.25 - 0.04 0.08 - 0.25 0.5 % Output Deviation from Full Scale Straight Line Between Normalized Zero Reading and Full Scale Input Gain Temperature Drift (Note 1) - ±25 ±40 - ±25 ±40 - ±50 ±100 ppm/°C Variation in Gain A due Full Scale to Temperature Change Gain Variance - ±10 - - ±10 - - ±10 - % of Nominal Zero Offset (Note 2) - ±10 ±50 - ±10 ±50 - ±20 ±100 mV Correction at Zero Adjust for Zero Output when Input is Zero Zero Temperature Drift (Note 1) - ±25 ±50 - ±25 ±50 - ±50 ±100 µV/°C Variation in Zero Offset Due to Temperature Change Note 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: Variation from Ideal Accuracy Full temperature range; not tested. IIN = 0. Full temperature range, IOUT = 10 mA. IOUT = 10 µA. Threshold Detect = 5V, Amp Out = 0V, full temperature range. 10 Hz to 100 kHz; not tested. 5 µs minimum positive pulse width and 0.5 µs minimum negative pulse width. tR = tF = 20 ns. RL 2 k, tested @ 10 k. Full temperature range, VIN = -0.1V. © 2007 Microchip Technology Inc. DS21483D-page 3 TC9400/9401/9402 TC9400/9401/9402 TC940X TC940X ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: unless otherwise specified, VDD = +5V, VSS = -5V, VGND = 0V, VREF = -5V, RBIAS = 100 k, Full Scale = 10 kHz. TA = +25°C, unless temperature range is specified (-40°C to +85°C for E device, 0°C to +70°C for C device). Parameter Min Typ Max Min Typ Max Min Typ Max Units Test Conditions - 10 - - 10 - - 10 - µA Full Scale Analog Input Current to achieve Specified Accuracy IIN Over Range - - 50 - - 50 - - 50 µA Over Range Current Response Time - 2 - - 2 - - 2 - Cycle Settling Time to 0.1% Full Scale Analog Input IIN Full Scale Digital Section TC9400 TC9400 TC9401 TC9401 TC9402 TC9402 VSAT @ IOL = 10mA - 0.2 0.4 - 0.2 0.4 - 0.2 0.4 V Logic "0" Output Voltage (Note 3) VOUTMAX VOUT Common (Note 4) - - 18 - - 18 - - 18 V Voltage Range Between Output and Common Pulse Frequency Output Width - 3 - - 3 - - 3 - µs Frequency-to-Voltage Supply Current IDD Quiescent (Note 5) - 1.5 6 - 1.5 6 - 3 10 mA Current Required from Positive Supply during Operation ISS Quiescent (Note 5) - -1.5 -6 - -1.5 -6 - -3 -10 mA Current Required from Negative Supply during Operation VDD Supply 4 - 7.5 4 - 7.5 4 - 7.5 V Operating Range of Positive Supply VSS Supply -4 - -7.5 -4 - -7.5 -4 - -7.5 V Operating Range of Negative Supply -2.5 - - -2.5 - - -2.5 - - V Range of Voltage Reference Input Non-Linearity (Note 10) - 0.02 0.05 - 0.01 0.02 - 0.05 0.25 Input Frequency Range (Notes 7 and 8) 10 - 100k 10 - 100k 10 - 100k Reference Voltage VREF VSS Accuracy Note 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: % Deviation from ideal Full Scale Transfer Function as a Percentage Full Scale Voltage Hz Frequency Range for Specified Non-Linearity Full temperature range; not tested. IIN = 0. Full temperature range, IOUT = 10 mA. IOUT = 10 µA. Threshold Detect = 5V, Amp Out = 0V, full temperature range. 10 Hz to 100 kHz; not tested. 5 µs minimum positive pulse width and 0.5 µs minimum negative pulse width. tR = tF = 20 ns. RL 2 k, tested @ 10 k. Full temperature range, VIN = -0.1V. DS21483D-page 4 © 2007 Microchip Technology Inc. TC9400/9401/9402 TC9400/9401/9402 TC940X TC940X ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: unless otherwise specified, VDD = +5V, VSS = -5V, VGND = 0V, VREF = -5V, RBIAS = 100 k, Full Scale = 10 kHz. TA = +25°C, unless temperature range is specified (-40°C to +85°C for E device, 0°C to +70°C for C device). Parameter Min Typ Max Min Typ Max Min Typ Max Units Test Conditions Positive Excursion 0.4 - VDD 0.4 - VDD 0.4 - VDD V Voltage Required to Turn Threshold Detector On Negative Excursion -0.4 -2 -0.4 - -2 -0.4 - -2 V Voltage Required to Turn Threshold Detector Off Frequency Input Minimum Positive Pulse Width (Note 8) - 5 - - 5 - - 5 - s Time between Threshold Crossings Minimum Negative Pulse Width (Note 8) - 0.5 - - 0.5 - - 0.5 - s Time Between Threshold Crossings Input Impedance - 10 - - 10 - - 10 M Analog Outputs TC9400 TC9400 TC9401 TC9401 TC9402 TC9402 Output Voltage (Note 9) - VDD 1 - - VDD 1 - - VDD 1 - V Output Loading 2 - - 2 - - 2 - - k Resistive Loading at Output of Op Amp - 1.5 6 - 3 10 mA Current Required from Positive Supply During Operation -1.5 -6 - -3 -10 mA Current Required from Negative Supply During Operation Supply Current TC9400 TC9400 TC9401 TC9401 Voltage Range of Op Amp Output for Specified Non-Linearity TC9402 TC9402 IDD Quiescent (Note 10) - 1.5 6 ISS Quiescent (Note 10) - -1.5 -6 VDD Supply 4 - 7.5 4 - 7.5 4 - 7.5 V Operating Range of Positive Supply VSS Supply -4 - -7.5 -4 - -7.5 -4 - -7.5 V Operating Range of Negative Supply -2.5 - - -2.5 - - -2.5 - - V Range of Voltage Reference Input Reference Voltage VREF VSS Note 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: Full temperature range; not tested. IIN = 0. Full temperature range, IOUT = 10 mA. IOUT = 10 µA. Threshold Detect = 5V, Amp Out = 0V, full temperature range. 10 Hz to 100 kHz; not tested. 5 µs minimum positive pulse width and 0.5 µs minimum negative pulse width. tR = tF = 20 ns. RL 2 k, tested @ 10 k. Full temperature range, VIN = -0.1V. © 2007 Microchip Technology Inc. DS21483D-page 5 TC9400/9401/9402 TC9400/9401/9402 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin No. Symbol 1 IBIAS 2 ZERO ADJ Description This pin sets bias current in the TC9400 TC9400. Connect to VSS through a 100 k resistor. Low frequency adjustment input. Input current connection for the V/F converter. 3 IIN 4 VSS 5 VREF OUT 6 GND Analog ground. 7 VREF Voltage reference input, typically -5V. 8 PULSE FREQ OUT 9 OUTPUT COMMON 10 FREQ/2 OUT This open drain output is a square wave at one-half the frequency of the pulse output (Pin 8). Output transitions of this pin occur on the rising edge of Pin 8. 11 THRESHOLD DETECTOR Input to the Threshold Detector. This pin is the frequency input during F/V operation. 12 Negative power supply voltage connection, typically -5V. Reference capacitor connection. Frequency output. This open drain output will pulse LOW each time the Freq. Threshold Detector limit is reached. The pulse rate is proportional to input voltage. Source connection for the open drain output FETs. AMPLIFIER OUT Output of the integrator amplifier. 13 2.1 NC No internal connection. 14 VDD Positive power supply connection, typically +5V. Bias Current (IBIAS) An external resistor, connected to VSS, sets the bias point for the TC9400 TC9400. Specifications for the TC9400 TC9400 are based on RBIAS = 100 k ±10%, unless otherwise noted. Increasing the maximum frequency of the TC9400 TC9400 beyond 100 kHz is limited by the pulse width of the pulse output (typically 3 µs). Reducing RBIAS will decrease the pulse width and increase the maximum operating frequency, but linearity errors will also increase. RBIAS can be reduced to 20 k, which will typically produce a maximum full scale frequency of 500 kHz. 2.2 Zero Adjust This pin is the non-inverting input of the operational amplifier. The low frequency set point is determined by adjusting the voltage at this pin. 2.3 Input Current (IIN) The inverting input of the operational amplifier and the summing junction when connected in the V/F mode. An input current of 10 A is specified, but an over range current up to 50 A can be used without detrimental effect to the circuit operation. IIN connects the summing junction of an operational amplifier. Voltage sources cannot be attached directly, but must be buffered by external resistors. DS21483D-page 6 2.4 Voltage Capacitor (VREF Out) The charging current for CREF is supplied through this pin. When the op amp output reaches the threshold level, this pin is internally connected to the reference voltage and a charge, equal to VREF x CREF, is removed from the integrator capacitor. After about 3sec, this pin is internally connected to the summing junction of the op amp to discharge CREF. Break-before-make switching ensures that the reference voltage is not directly applied to the summing junction. 2.5 Voltage Reference (VREF) A reference voltage from either a precision source, or the VSS supply is applied to this pin. Accuracy of the TC9400 TC9400 is dependent on the voltage regulation and temperature characteristics of the reference circuitry. Since the TC9400 TC9400 is a charge balancing V/F converter, the reference current will be equal to the input current. For this reason, the DC impedance of the reference voltage source must be kept low enough to prevent linearity errors. For linearity of 0.01%, a reference impedance of 200 or less is recommended. A 0.1 µF bypass capacitor should be connected from VREF to ground. © 2007 Microchip Technology Inc. TC9400/9401/9402 TC9400/9401/9402 2.6 Pulse Freq Out 2.9 This output is an open-drain N-channel FET, which provides a pulse waveform whose frequency is proportional to the input voltage. This output requires a pullup resistor and interfaces directly with MOS, CMOS, and TTL logic (see Figure 2-1). 2.7 Output Common The sources of both the FREQ/2 OUT and the PULSE FREQ OUT are connected to this pin. An output level swing from the drain voltage to ground, or to the VSS supply, may be obtained by connecting this pin to the appropriate point. 2.8 Freq/2 Out In the V/F mode, this input is connected to the AMPLIFIER OUT output (Pin 12) and triggers a 3 µs pulse when the input voltage passes through its threshold. In the F/V mode, the input frequency is applied to this input. The nominal threshold of the detector is half way between the power supplies, or (VDD + VSS)/2 ±400 mV. The TC9400 TC9400's charge balancing V/F technique is not dependent on a precision comparator threshold, because the threshold only sets the lower limit of the op amp output. The op amp's peak-to-peak output swing, which determines the frequency, is only influenced by external capacitors and by VREF. 2.10 This output is an open-drain N-channel FET, which provides a square-wave one-half the frequency of the pulse frequency output. The FREQ/2 OUT output will change state on the rising edge of PULSE FREQ OUT. This output requires a pull-up resistor and interfaces directly with MOS, CMOS, and TTL logic. Threshold Detector Input Amplifier Out This pin is the output stage of the operational amplifier. During V/F operation, a negative going ramp signal is available at this pin. In the F/V mode, a voltage proportional to the frequency input is generated. 3 ms Typ. FOUT 1/f FOUT/2 VREF CREF CINT 0V Amp Out Note 1: To adjust FMIN, set VIN = 10 mV and adjust the 50 k offset for 10 Hz output. 2: To adjust FMAX, set VIN = 10V and adjust RIN or VREF for 10 kHz output. 3: To increase FOUTMAX to 100 kHz, change CREF to 2 pF and CINT to 75 pF. 4: For high performance applications, use high stability components for RIN, CREF. VREF (metal film resistors and glass capacitors). Also, separate output ground (Pin 9) from input ground (Pin 6). FIGURE 2-1: Output Waveforms. © 2007 Microchip Technology Inc. DS21483D-page 7 TC9400/9401/9402 TC9400/9401/9402 3.0 DETAILED DESCRIPTION 3.1 Voltage-to-Frequency (V/F) Circuit Description The TC9400 TC9400 V/F converter operates on the principal of charge balancing. The operation of the TC9400 TC9400 is easily understood by referring to Figure 3-1. The input voltage (VIN) is converted to a current (IIN) by the input resistor. This current is then converted to a charge on the integrating capacitor and shows up as a linearly decreasing voltage at the output of the op amp. The lower limit of the output swing is set by the threshold detector, which causes the reference voltage to be applied to the reference capacitor for a time period long enough to charge the capacitor to the reference voltage. This action reduces the charge on the integrating capacitor by a fixed amount (q = CREF x VREF), causing the op amp output to step up a finite amount. At the end of the charging period, CREF is shorted out. This dissipates the charge stored on the reference capacitor, so that when the output again crosses zero, the system is ready to recycle. In this manner, the continued discharging of the integrating capacitor by the input is balanced out by fixed charges from the refer- ence voltage. As the input voltage is increased, the number of reference pulses required to maintain balance increases, which causes the output frequency to also increase. Since each charge increment is fixed, the increase in frequency with voltage is linear. In addition, the accuracy of the output pulse width does not directly affect the linearity of the V/F. The pulse must simply be long enough for full charge transfer to take place. The TC9400 TC9400 contains a "self-start" circuit to ensure the V/F converter always operates properly when power is first applied. In the event that, during power-on, the op amp output is below the threshold and CREF is already charged, a positive voltage step will not occur. The op amp output will continue to decrease until it crosses the -3.0V threshold of the "self-start" comparator. When this happens, an internal resistor is connected to the op amp input, which forces the output to go positive until the TC9400 TC9400 is in its normal Operating mode. The TC9400 TC9400 utilizes low-power CMOS processing for low input bias and offset currents, with very low power dissipation. The open drain N-channel output FETs provide high voltage and high current sink capability. +5V + 5V 14 VDD 11 Threshold Detect FOUT 8 3 ms Delay RL 10 k +5V Threshold Detector FOUT/2 10 ÷2 SelfStart RL 10 k 9 -3V Output Common 12 AMP OUT 5 CINT 820 pF INPUT VIN 510 k 2 Zero Adjust 60 pF Op Amp + IBIAS -5V Offset Adjust TC9400 TC9400 TC9401 TC9401 TC9402 TC9402 12 pF 3 IIN +5V 50 k 20 k CREF 180 pF RIN 1 M 0V 10V VREFOUT 10 k 1 VSS VREF 4 7 RBIAS 100 k GND 6 Reference Voltage (Typically -5V) -5V FIGURE 3-1: DS21483D-page 8 10 Hz to 10 kHz V/F Converter. © 2007 Microchip Technology Inc. TC9400/9401/9402 TC9400/9401/9402 3.2 Voltage-to-Time Measurements The TC9400 TC9400 output can be measured in the time domain as well as the frequency domain. Some microcomputers, for example, have extensive timing capability, but limited counter capability. Also, the response time of a time domain measurement is only the period between two output pulses, while the frequency measurement must accumulate pulses during the entire counter time-base period. Time measurements can be made from either the TC9400 TC9400's PULSE FREQ OUT output, or from the FREQ/2 OUT output. The FREQ/2 OUT output changes state on the rising edge of PULSE FREQ OUT, so FREQ/2 OUT is a symmetrical square wave at one-half the pulse output frequency. Timing measurements can, therefore, be made between successive PULSE FREQ OUT pulses, or while FREQ/2 OUT is high (or low). © 2007 Microchip Technology Inc. DS21483D-page 9 TC9400/9401/9402 TC9400/9401/9402 4.0 4.1 VOLTAGE-TO-FREQUENCY (V/F) CONVERTER DESIGN INFORMATION Input/Output Relationships The output frequency (FOUT) is related to the analog input voltage (VIN) by the transfer equation: 4.2.3 CREF The exact value is not critical and may be used to trim the full scale frequency (see Section 6.1 "Input/Output Relationships", Input/Output Relationships). Glass film or air trimmer capacitors are recommended because of their stability and low leakage. Locate as close as possible to Pins 5 and 3 (see Figure 4-1). 500 VDD = +5V VSS = -5V RIN = 1MW VIN = +10V TA = +25°C EQUATION 4-1: 400 4.2 4.2.1 CREF (pF) +12pF V IN 1 Frequency Out = - · -R IN ( V REF ) ( C REF ) External Component Selection RIN 10 kHz 200 100 The value of this component is chosen to give a full scale input current of approximately 10 µA: EQUATION 4-2: V FULL SCALE RIN IN 10 A EQUATION 4-3: RIN 10V = 1 M 10 A Note that the value is an approximation and the exact relationship is defined by the transfer equation. In practice, the value of RIN typically would be trimmed to obtain full scale frequency at VIN full scale (see Section 4.3 "Adjustment Procedure", Adjustment Procedure). Metal film resistors with 1% tolerance or better are recommended for high accuracy applications because of their thermal stability and low noise generation. 4.2.2 300 CINT The exact value is not critical but is related to CREF by the relationship: 3CREF CINT 10CREF 10CREF Improved stability and linearity are obtained when CINT 4CREF. Low leakage types are recommended, although mica and ceramic devices can be used in applications where their temperature limits are not exceeded. Locate as close as possible to Pins 12 and 13. DS21483D-page 10 100 kHz 0 -1 FIGURE 4-1: VREF. 4.2.4 -2 -3 -4 VREF (V) -5 -6 -7 Recommended CREF vs. VDD, VSS Power supplies of ±5V are recommended. For high accuracy requirements, 0.05% line and load regulation and 0.1 µF disc decoupling capacitors, located near the pins, are recommended. 4.3 Adjustment Procedure Figure 3-1 shows a circuit for trimming the zero location. Full scale may be trimmed by adjusting RIN, VREF, or CREF. Recommended procedure for a 10 kHz full scale frequency is as follows: 1. 2. Set VIN to 10 mV and trim the zero adjust circuit to obtain a 10 Hz output frequency. Set VIN to 10V and trim either RIN, VREF, or CREF to obtain a 10 kHz output frequency. If adjustments are performed in this order, there should be no interaction and they should not have to be repeated. 4.4 Improved Single Supply V/F Converter Operation A TC9400 TC9400, which operates from a single 12 to 15V variable power source, is shown in Figure 4-2. This circuit uses two Zener diodes to set stable biasing levels for the TC9400 TC9400. The Zener diodes also provide the reference voltage, so the output impedance and temperature coefficient of the Zeners will directly affect power supply rejection and temperature performance. Full scale adjustment is accomplished by trimming the input current. © 2007 Microchip Technology Inc. TC9400/9401/9402 TC9400/9401/9402 The circuit of Figure 4-2 will directly interface with CMOS logic operating at 12V to 15V. TTL or 5V CMOS logic can be accommodated by connecting the output pull-up resistors to the +5V supply. An optoisolator can also be used if an isolated output is required; also, see Figure 4-3. Trimming the reference voltage is not recommended for high accuracy applications unless an op amp is used as a buffer, because the TC9400 TC9400 requires a lowimpedance reference (see Section 2.5 "Voltage Reference (VREF)", VREF pin description, for more information). +12 to +15V 1.2 k 14 V DD 1 µF R1 910 k R4 100 k D2 5.1 VZ R3 CINT CREF 11 Threshold Detect 12 Amp Out 5 CREF 3 I IN 2 Zero Adjust 6 GND 100 k Input Voltage (0 to 10V) 10 k TC9400 TC9400 Gain R2 910 k 10 k R5 91 k D1 5.1 VZ FOUT 8 FOUT/2 0.1 µF BIAS 100 k Output Frequency Output 9 Common 7 V REF 1 I Rp Offset 20 k 10 VSS 4 Digital Ground Analog Ground Component Selection F/S Freq. CREF CINT 1 kHz 180 pF 470 pF 100 kHz FIGURE 4-2: 2200 pF 4700 pF 10 kHz 27 pF 75 pF Voltage-to-Frequency. © 2007 Microchip Technology Inc. DS21483D-page 11 TC9400/9401/9402 TC9400/9401/9402 V+ = 8V to 15V (Fixed) R2 R1 0.9 Offset Adjust RIN 1 M 8 0.01 µF 10 k 0.01 11 µF 0.2 R1 10 VREF FOUT/2 12 5 820 pF 180 pF 3 IIN VIN 0V10V FOUT TC9400 TC9400 7 2 k 10 k 2 6 5V 8.2 k Gain Adjust 14 V2 IIN 1 4 9 100 k V+ 1 M 10 k 12V 1.4 M 14 k 15V DS21483D-page 12 R2 10V FIGURE 4-3: R1 2 M 20 k 1 F OUT = I IN -( V 2 V 7 ) ( C REF ) ( V IN V 2 ) ( V+ V 2 ) I IN = - + -( 0.9R 1 + 0.2R 1 ) R IN Fixed Voltage Single Supply Operation. © 2007 Microchip Technology Inc. TC9400/9401/9402 TC9400/9401/9402 5.0 FREQUENCY-TO-VOLTAGE (F/V) CIRCUIT DESCRIPTION When used as an F/V converter, the TC9400 TC9400 generates an output voltage linearly proportional to the input frequency waveform. Each zero crossing at the threshold detector's input causes a precise amount of charge (q = CREF x VREF) to be dispensed into the op amp's summing junction. This charge, in turn, flows through the feedback resistor, generating voltage pulses at the output of the op amp. A capacitor (CINT) across RINT averages these pulses into a DC voltage, which is linearly proportional to the input frequency. © 2007 Microchip Technology Inc. DS21483D-page 13 TC9400/9401/9402 TC9400/9401/9402 6.0 6.1 F/V CONVERTER DESIGN INFORMATION 6.2 Input/Output Relationships The output voltage is related to the input frequency (FIN) by the transfer equation: EQUATION 6-1: VOUT = [VREF CREF RINT] FIN The response time to a change in FIN is equal to (RINT CINT). The amount of ripple on VOUT is inversely proportional to CINT and the input frequency. CINT can be increased to lower the ripple. Values of 1 µF to 100 µF are perfectly acceptable for low frequencies. When the TC9400 TC9400 is used in the Single Supply mode, VREF is defined as the voltage difference between Pin 7 and Pin 2. Input Voltage Levels The input frequency is applied to the Threshold Detector input (Pin 11). As discussed in the V/F circuit section of this data sheet, the threshold of Pin 11 is approximately (VDD + VSS)/2 ±400 mV. Pin 11's input voltage range extends from VDD to about 2.5V below the threshold. If the voltage on Pin 11 goes more than 2.5 volts below the threshold, the V/F mode start-up comparator will turn on and corrupt the output voltage. The Threshold Detector input has about 200 mV of hysteresis. In ±5V applications, the input voltage levels for the TC9400 TC9400 are ±400 mV, minimum. If the frequency source being measured is unipolar, such as TTL or CMOS operating from a +5V source, then an AC coupled level shifter should be used. One such circuit is shown in Figure 6-1(a). The level shifter circuit in Figure 6-1(b) can be used in single supply F/V applications. The resistor divider ensures that the input threshold will track the supply voltages. The diode clamp prevents the input from going far enough in the negative direction to turn on the start-up comparator. The diode's forward voltage decreases by 2.1 mV/°C, so for high ambient temperature operation, two diodes in series are recommended. +8V to +15V +5V 14 VDD 10 k TC9400 TC9400 TC9400 TC9400 Frequency Input 33 k +5V 0V 0.01 µF 11 Frequency Input DET +5V IN914 IN914 1.0 M 0V GND 6 VSS 4 14 VDD 33 k 0.01 µF 11 IN914 IN914 DET 1.0 M 0.1 µF 10 k VSS 4 -5V (a) ±5V Supply FIGURE 6-1: DS21483D-page 14 (b) Single Supply Frequency Input Level Shifter. © 2007 Microchip Technology Inc. TC9400/9401/9402 TC9400/9401/9402 V+ = 10V to 15V 14 10 k VDD 6 GND .01 µF 6.2V TC9400 TC9400 10 k VREFOUT 500 k 2 Zero Adjust 100 k V+ Offset Adjust 33 k Frequency Input 47 pF IIN 3 Amp Out 12 1.0 k 0.01 µF 11 DET IN914 IN914 1.0 M 0.1 µF 5 IBIAS GND 6 1 M .001 µF VOUT VREF VSS 7 4 1.0 k 100 k Note: FIGURE 6-2: 6.3 The output is referenced to Pin 6, which is at 6.2V (Vz). For frequency meter applications, a 1 mA meter with a series scaling resistor can be placed across Pins 6 and 12. F/V Single Supply F/V Converter. Input Buffer FOUT and FOUT/2 are not used in the F/V mode. However, these outputs may be useful for some applications, such as a buffer to feed additional circuitry. Then, FOUT will follow the input frequency waveform, except that FOUT will go high 3 µs after FIN goes high; FOUT/2 will be square wave with a frequency of one-half FOUT. 0.5 ms Min If these outputs are not used, Pins 8, 9 and 10 should be connected to ground (see Figure 6-3 and Figure 6-4). 5.0 ms Min Input FOUT Delay = 3 ms FOUT/2 FIGURE 6-3: F/V Digital Outputs. © 2007 Microchip Technology Inc. DS21483D-page 15 TC9400/9401/9402 TC9400/9401/9402 +5V V+ 14 VDD TC9400A TC9400A TC9401A TC9401A TC9402A TC9402A Frequency Input Level Shifter FIN 42 V+ Output Common 9 * Threshold Detect 11 * FOUT 8 3 ms Delay *Optional If Buffer is Needed Threshold Detector VREF OUT 5 CREF 56 pF 12 pF Offset Adjust IIN 3 +5V 2 k 100 k 2 Zero Adjust 2.2 k IBIAS VSS 1 60 pF Amp Out 12 Op Amp + 4 VREF RINT 1 M + See Figure 7-1: * FOUT/2 10 CINT 1000 pF VOUT GND 6 7 10 k VREF (Typically -5V) -5V FIGURE 6-4: 6.4 DC 10 kHz Converter. Output Filtering The output of the TC9400 TC9400 has a sawtooth ripple superimposed on a DC level. The ripple will be rejected if the TC9400 TC9400 output is converted to a digital value by an integrating Analog-to-Digital Converter, such as the TC7107 TC7107. The ripple can also be reduced by increasing the value of the integrating capacitor, although this will reduce the response time of the F/V converter. The sawtooth ripple on the output of an F/V can be eliminated without affecting the F/V's response time by using the circuit in Figure 6-1. The circuit is a capacitance multiplier, where the output coupling capacitor is multiplied by the AC gain of the op amp. A moderately fast op amp, such as the TL071 TL071, should be used. VREFOUT 5 47 pF TC9400 TC9400 AMP OUT 12 1 M .001 µF 200 .01 µF 1M GND 6 2 +5 7 6 3 + 4 1 -5 M FIGURE 6-5: DS21483D-page 16 IIN 3 0.1 µF VOUT TL071 TL071 Ripple Filter. © 2007 Microchip Technology Inc. TC9400/9401/9402 TC9400/9401/9402 7.0 F/V POWER-ON RESET In some cases, however, the TC9400 TC9400 output must be zero at power-on without a frequency input. In such cases, a capacitor connected from Pin 11 to VDD will usually be sufficient to pulse the TC9400 TC9400 and provide a Power-on Reset (see Figure 7-1 (a) and (b). Where predictable power-on operation is critical, a more complicated circuit, such as Figure 7-1 (b), may be required. In F/V mode, the TC9400 TC9400 output voltage will occasionally be at its maximum value when power is first applied. This condition remains until the first pulse is applied to FIN. In most frequency measurement applications, this is not a problem because proper operation begins as soon as the frequency input is applied. (a) (b) VDD VDD 14 1000 pF FIN 1 k 3 11 Threshold Detector TC9400 TC9400 FIGURE 7-1: 16 VCC CLRA 2 R CD4538 CD4538 100 k 4 A 1 µF 5 B VSS 8 1 C Q 6 To TC9400 TC9400 FIN Power-On Operation/Reset. © 2007 Microchip Technology Inc. DS21483D-page 17 TC9400/9401/9402 TC9400/9401/9402 8.0 PACKAGE INFORMATION 8.1 Package Marking Information 14-Lead CERDIP Example: (Front View) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN TC9400EJD TC9400EJD 0731256 Example: (Back View) Y2026 Y2026 Example: (Front View) 14-Lead PDIP XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN TC9400 TC9400 CPD ^^ e3 0731256 Example: (Back View) Y2026 Y2026 14-Lead SOIC (.150") XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Example: (Front View) TC9400 TC9400 e EOD ^^ 3 0731256 Example: (Back View) Y2026 Y2026 Legend: XX.X Y YY WW NNN e3 * Note: DS21483D-page 18 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2007 Microchip Technology Inc. TC9400/9401/9402 TC9400/9401/9402 14-Lead Ceramic Dual In-Line (JD) .300" Body [CERDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N E1 NOTE 1 1 2 D E A2 A c L A1 b1 b E2 e Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 14 Pitch e Top to Seating Plane A Standoff § A1 .015 Ceramic Package Height A2 .140 .175 Shoulder to Shoulder Width E .290 .325 Ceramic Package Width E1 .230 .288 .300 Overall Length D .740 .760 .780 Tip to Seating Plane L .125 .200 Lead Thickness c .008 .015 b1 .045 .065 b .015 .023 E2 .320 .410 Upper Lead Width Lower Lead Width Overall Row Spacing .100 BSC .200 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-002B C04-002B © 2007 Microchip Technology Inc. DS21483D-page 19 TC9400/9401/9402 TC9400/9401/9402 14-Lead Plastic Dual In-Line (PD) 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 14 Pitch e Top to Seating Plane A .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .735 .750 .775 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 b1 .045 .060 .070 b .014 .018 .022 eB Upper Lead Width Lower Lead Width Overall Row Spacing § .100 BSC .430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-005B C04-005B DS21483D-page 20 © 2007 Microchip Technology Inc. TC9400/9401/9402 TC9400/9401/9402 14-Lead Plastic Small Outline (OD) Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 e h b A A2 c L A1 L1 Units Dimension Limits Number of Pins h MILLIMETERS MIN N NOM MAX 14 Pitch e Overall Height A 1.27 BSC Molded Package Thickness A2 1.25 Standoff § A1 0.10 0.25 Overall Width E Molded Package Width E1 3.90 BSC Overall Length D 1.75 6.00 BSC 8.65 BSC Chamfer (optional) h 0.25 0.50 Foot Length L 0.40 1.27 Footprint L1 1.04 REF Foot Angle 0° 8° Lead Thickness c 0.17 0.25 Lead Width b 0.31 0.51 Mold Draft Angle Top 5° 15° Mold Draft Angle Bottom 5° 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-065B C04-065B © 2007 Microchip Technology Inc. DS21483D-page 21 TC9400/9401/9402 TC9400/9401/9402 NOTES: DS21483D-page 22 © 2007 Microchip Technology Inc. TC9400/9401/9402 TC9400/9401/9402 APPENDIX A: REVISION HISTORY Revision D (September 2007) The following is the list of modifications: 1. 2. 3. 4. Corrected Figure 6-1. Added History section. Updated package marking information and package outline drawings Added Product identification System section. Revision C (May 2006) Revision B (May 2002) Revision A (April 2002) · Original Release of this Document. © 2007 Microchip Technology Inc. DS21483D-page 23 TC9400/9401/9402 TC9400/9401/9402 NOTES: DS21483D-page 24 © 2007 Microchip Technology Inc. TC9400/9401/9402 TC9400/9401/9402 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Examples: a) b) Device Temperature Range TC9400 TC9400: Voltage-to-Frequency Converter TC9401 TC9401: Voltage-to-Frequency Converter TC9402 TC9402: Voltage-to-Frequency Converter E C = -40°C to +85°C (Extended) = 0°C to +70°C (Commercial) c) d) TC9400COD TC9400COD: 0°C to +70°C, 14LD SOIC package. TC9400COD713 TC9400COD713:0°C to +70°C, 14LD SOIC package, Tape and Reel TC9400CPD TC9400CPD: 0°C to +70°C, 14LD PDIP package. TC9400EJD TC9400EJD: -40°C to +85°C, 14LD PDIP package. JD PD OD OD713 OD713 = = = = Ceramic Dual-Inline (.300" Body), 14-lead Plastic Dual-Inline (300 mil Body), 14-lead Plastic Small Outline (3.90 MM Body), 14-lead Plastic Small Outline (3.90 MM Body), 14-lead Tape and Reel. © 2007 Microchip Technology Inc. TC9401CPD TC9401CPD: b) TC9401EJD TC9401EJD: a) TC9402CPD TC9402CPD: b) Package a) TC9402EJD TC9402EJD: 0°C to +70°C, 14LD PDIP package. -40°C to +85°C, 14LD CERDIP package. 0°C to +70°C, 14LD PDIP package. -40°C to +85°C, 14LD CERDIP package. DS21483D-page 25 TC9400/9401/9402 TC9400/9401/9402 NOTES: DS21483D-page 26 © 2007 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: · Microchip products meet the specification contained in their particular Microchip Data Sheet. · Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. · There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. · Microchip is willing to work with the customer who is concerned about the integrity of their code. · Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949 ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2007 Microchip Technology Inc. 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