TC74HC597AP/AF TC74HC597AP TC74HC597AF TC74HC597A 74LS597 DIP16-P-300-2

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC597AP,TC74HC597AF 8-Bit Latch/Shift Register The TC74HC597A is a

TC74HC597AP/AF TC74HC597AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC597AP TC74HC597AP,TC74HC597AF TC74HC597AF 8-Bit Latch/Shift Register The TC74HC597A TC74HC597A is a high speed CMOS 8-BIT PARALLEL-IN/SERIAL-IN SERIAL-OUT LATCH/SHIFT REGISTER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. It consists of an 8-bit data register feeding an 8-bit shift register. The parallel data on the A to H inputs is stored in the input register on the positive going transition of RCK. When the SLOAD input is held low, the input register data is passed into the shift registers. When SLOAD input is held high, the serial data input (SI) is enabled and the eight flip-flops perform serial shifting on the positive transition of SCK. A direct clear input ( SCLR ) sets the 8-bit shift register to zero. All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74HC597AP TC74HC597AP TC74HC597AF TC74HC597AF Features · High speed: fmax = 60 MHz (typ.) at VCC = 5 V · Low power dissipation: ICC = 4 A (max) at Ta = 25°C · High noise immunity: VNIH = VNIL = 28% VCC · Output drive capability: 10 LSTTL loads · · Symmetrical output impedance: |IOH| = IOL = 4 mA (min) Balanced propagation delays: tpLH - tpHL · Wide operating voltage range: VCC (opr) = 2 to 6 V · Pin and function compatible with 74LS597 74LS597 Weight DIP16-P-300-2 DIP16-P-300-2.54A SOP16-P-300-1.27A : 1.00 g (typ.) : 0.18 g (typ.) Pin Assignment 1 2007-10-01 TC74HC597AP/AF TC74HC597AP/AF IEC Logic Symbol Truth Table Inputs Function SI SCK SCLR SLOAD RCK X X L H X S.R. is cleared to "L" X X H L X Input register data is stored into S.R. L H H X First stage of S.R. become "L". Other stages store the data of previous stage, respectively. H H H X First stage of S.R. become "H". Other stages store the data of previous stage, respectively. X H H X State of S.R. is not changed. X X X X Input data on A to H line is stored into input register. X X X X Storage register stage is not changed. X: Don't care 2 2007-10-01 TC74HC597AP/AF TC74HC597AP/AF Timing Chart 3 2007-10-01 TC74HC597AP/AF TC74HC597AP/AF System Diagram 4 2007-10-01 TC74HC597AP/AF TC74HC597AP/AF Absolute Maximum Ratings (Note 1) Characteristics Symbol Rating Unit Supply voltage range VCC -0.5 to 7.0 V DC input voltage VIN -0.5 to VCC + 0.5 V VOUT -0.5 to VCC + 0.5 V Input diode current IIK ±20 mA Output diode current IOK ±20 mA DC output current IOUT ±25 mA DC VCC/ground current ICC ±50 mA Power dissipation PD 500 (DIP) (Note 2)/180 (SOP) mW Storage temperature Tstg -65 to 150 °C DC output voltage Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = -40 to 65°C. From Ta = 65 to 85°C a derating factor of -10 mW/°C should be applied until 300 mW. Operating Ranges (Note) Characteristics Symbol Rating Unit Supply voltage VCC 2 to 6 V Input voltage VIN 0 to VCC V VOUT 0 to VCC V Operating temperature Topr -40 to 85 °C Input rise and fall time tr, tf Output voltage 0 to 1000 (VCC = 2.0 V) 0 to 500 (VCC = 4.5 V) ns 0 to 400 (VCC = 6.0 V) Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. 5 2007-10-01 TC74HC597AP/AF TC74HC597AP/AF Electrical Characteristics DC Characteristics Symbol Ta = -40 to 85°C Ta = 25°C Test Condition Characteristics 1.50 3.15 3.15 4.20 4.20 0.50 0.50 4.5 1.35 1.35 1.80 1.80 2.0 1.9 2.0 1.9 4.5 4.4 4.5 4.4 6.0 5.9 6.0 5.9 IOH = -4 mA 4.5 4.18 4.31 4.13 IOH = -5.2 mA 6.0 5.68 5.80 5.63 2.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 6.0 0.0 0.1 0.1 IOL = 4 mA 4.5 0.17 0.26 0.33 IOL = 5.2 mA 6.0 0.18 0.26 0.33 VIL VOL 1.50 4.5 VIN = VIH or VIL VIN = VIH or VIL Unit Max 6.0 Low-level output voltage Min VIH VOH Max 2.0 High-level output voltage Typ. 6.0 Low-level input voltage Min 2.0 High-level input voltage VCC (V) IOH = -20 A IOL = 20 A V V V V Input leakage current IIN VIN = VCC or GND 6.0 ±0.1 ±1.0 A Quiescent supply current ICC VIN = VCC or GND 6.0 4.0 40.0 A 6 2007-10-01 TC74HC597AP/AF TC74HC597AP/AF Timing Requirements (input: tr = tf = 6 ns) Characteristics Ta = 25°C Test Condition Symbol Ta = -40 to 85°C Unit VCC (V) (SI-SCK) Minimum set-up time (PI-RCK) Minimum hold time Minimum removal time ( SCLR , SLOAD ) Clock frequency 13 16 75 95 4.5 15 19 13 16 2.0 75 95 4.5 15 19 13 16 2.0 100 125 4.5 20 25 6.0 17 21 2.0 75 95 4.5 15 19 13 16 2.0 75 95 4.5 15 19 13 16 0 0 4.5 0 0 0 0 2.0 75 95 4.5 15 19 6.0 13 16 6 5 4.5 30 24 6.0 Minimum set-up time 2.0 (RCK- SLOAD ) 19 6.0 Minimum set-up time 15 2.0 ( SLOAD ) 6.0 Minimum pulse width 4.5 6.0 ( SCLR ) 95 6.0 Minimum pulse width 75 6.0 35 28 Test Condition Min Typ. Max Unit 5 8 ns 16 25 ns 20 32 ns tW (L) 6.0 (SCK, RCK) Limit 2.0 tW (H) Limit 2.0 Minimum pulse width Typ. 18 30 ns 25 37 ns 30 59 MHz tW (L) tW (L) ts ts ts th trem f ns ns ns ns ns ns ns ns MHz AC Characteristics (CL = 15 pF, VCC = 5 V, Ta = 25°C, input: tr = tf = 6 ns) Characteristics Output transition time Symbol tTLH tTHL Propagation delay time tpLH (SCK-QH') tpHL Propagation delay time ( SCLR -QH') tpHL Propagation delay time tpLH ( SLOAD -QH') tpHL Propagation delay time tpLH (RCK-QH') tpHL Clock frequency fmax SLOAD = "L" 7 2007-10-01 TC74HC597AP/AF TC74HC597AP/AF AC Characteristics (CL = 50 pF, input: tr = tf = 6 ns) Symbol Ta = -40 to 85°C Ta = 25°C Test Condition Characteristics Unit Max 32 75 95 4.5 8 15 19 7 13 16 2.0 78 145 180 4.5 20 29 36 6.0 16 25 31 2.0 90 175 220 4.5 24 35 44 20 30 37 2.0 80 175 220 4.5 22 35 44 6.0 18 30 37 2.0 112 210 265 4.5 30 42 53 6.0 24 36 45 2.0 6 12 5 4.5 30 48 24 6.0 tpHL Propagation delay time Min 6.0 tpLH (SCK-QH') Max 35 50 28 5 10 10 pF 60 pF tTHL Propagation delay time Typ. 2.0 tTLH Min 6.0 Output transition time VCC (V) tpHL ( SCLR -QH') Propagation delay time tpLH ( SLOAD -QH') tpHL Propagation delay time tpLH (RCK-QH') tpHL Maximum clock frequency SLOAD = "L" fmax Input capacitance CIN Power dissipation capacitance CPD Note: (Note) ns ns ns ns ns MHz CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPDVCCfIN + ICC 8 2007-10-01 TC74HC597AP/AF TC74HC597AP/AF Package Dimensions Weight: 1.00 g (typ.) 9 2007-10-01 TC74HC597AP/AF TC74HC597AP/AF Package Dimensions Weight: 0.18 g (typ.) 10 2007-10-01 TC74HC597AP/AF TC74HC597AP/AF RESTRICTIONS ON PRODUCT USE · Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. · This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission. · Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. 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