TC59LM906AMG-37 TC59LM906AMG TC59LM906-37 18HSTL P-BGA64-1317-1 BA2A13 A13BA0 - Datasheet Archive

 

MOS CMOS 512M FCRAM1 (SSTL_18, HSTL Interface) - 8,388,608 × 8 ×8 TC59LM906AMG CMOS 536,870,912 (FCRAMTM) 2

 

TC59LM906AMG-37 TC59LM906AMG-37 MOS CMOS 512M FCRAM1 (SSTL_18, HSTL Interface) - 8,388,608 × 8 ×8 TC59LM906AMG TC59LM906AMG CMOS 536,870,912 (FCRAMTM) 2 TC59LM906AMG TC59LM906AMG 8,388,608 × 8 × 8 RAM DQS 533M / FCRAMTM DDR SDRAM TC59LM906AMG TC59LM906AMG TC59LM906-37 TC59LM906-37 tCK CLK () 3.75 ns tRC / () 22.5 ns tRAC () 22.0 ns IDD1S () () 280 mA lDD2P () () 90 mA lDD6 · · · · · · · · · · · · · () 20 mA · (DDR) DQS(/)/ · (CLK & CLK ) CS , FN CLK (DQ & DQS) CLK CLK CLK CLK : 266 MHz : 533M / 8 · & · ( 3.9 µs) · · = CAS -1 CAS / CAS = 5 = 24 : TC59LM906AMG TC59LM906AMG : 8,388,608 × 8 × 8 VDD: 2.5 V ± 0.125V VDDQ: 1.4 V ~ 1.9 V : SSTL_18HSTL 18HSTL : 60Ball BGA, 1mm × 1mm Ball pitch (P-BGA64-1317-1 P-BGA64-1317-1.00AZ) : "FCRAM"() Rev 1.1 2005-11-08 1/47 TC59LM906AMG-37 TC59LM906AMG-37 A0~A13 DQS / DQS / BA0~BA2 VDD (+2.5 V) DQ0~DQ7 VSS () CS VDDQ (+1.5 V / +1.8 V) (DQ ) FN VSSQ () (DQ ) PD VREF CLK, CLK NC BA2 A14 4 () ball pitch=1.0 x 1.0mm x8 1 2 5 6 VSS DQ7 DQ0 VDD B NC VSSQ VDDQ NC C DQ6 VDDQ VSSQ DQ1 D NC DQ5 DQ2 NC E NC VSSQ VDDQ NC DQ4 VDDQ VSSQ DQ3 G NC VSSQ VDDQ NC H NC DQS DQS NC J VREF VSS VDD BA2 CLK CLK FN A13 L A12 PD CS NC M A11 A9 BA1 BA0 N A8 A7 A0 A10 P A5 A6 A2 A1 R VSS A4 A3 VDD A F K Index NC NC 3 4 NC NC : Rev 1.1 2005-11-08 2/47 TC59LM906AMG-37 TC59LM906AMG-37 PD CS FN DLL #7 #6 #5 #4 #3 #2 #1 CLK CLK A0~A13 BA0~BA2 #0 / DQS DQS DQ DQ0~DQ7 : TC59LM906AMG TC59LM906AMG 8 16384 × 512 × 8 DQ DQS DQS Rev 1.1 2005-11-08 3/47 TC59LM906AMG-37 TC59LM906AMG-37 -0.3 ~ 3.3 V (DQ ) -0.3~VDD+ 0.3 V VIN -0.3~VDD+ 0.3 V VOUT (DQ ) -0.3~VDDQ + 0.3 V VREF -0.3~VDD+ 0.3 V Topr () 0~85 °C Tstg -55~150 °C Tsolder (10 ) 260 °C PD 2 W IOUT ±50 mA VDD VDDQ : DCAC (: 1) (TCASE = 0~85°C) VDD VDDQ (DQ ) VREF 2.375 2.5 2.625 V 1.4 1.9 V VDDQ/2 × 95% VDDQ/2 VDDQ/2 × 105% V 2 VIH (DC) (DC) VREF + 0.125 VDDQ + 0.2 V 5 VIL (DC) (DC) -0.1 VREF - 0.125 V 5 VICK (DC) DC -0.1 VDDQ + 0.1 V 10 VID (DC) (DC) 0.4 VDDQ + 0.2 V 7, 10 VIH (AC) (AC) VREF + 0.2 VDDQ + 0.2 V 3, 6 VIL (AC) (AC) -0.1 VREF - 0.2 V 4, 6 VID (AC) (AC) 0.5 VDDQ + 0.2 V 7, 10 VX (AC) (AC) VDDQ/2 - 0.125 VDDQ/2 + 0.125 V 8, 10 VISO (AC) (AC) VDDQ/2 - 0.125 VDDQ/2 + 0.125 V 9, 10 Rev 1.1 2005-11-08 4/47 TC59LM906AMG-37 TC59LM906AMG-37 : (1) VSSVSSQ (2) VREF VDDQ (DC) VREF VREF (DC) ±2% (3) : 5 ns VIH (max) = VDDQ + 0.7 V (4) : 5 ns VIL (min) = -0.7 V (5) VIH (DC) VIL (DC) (6) VIH (AC) VIL (AC) (7) VID VTR VCP (8) VX (AC) VDDQ/2 (9) VISO {VICK (VTR) + VICK (VCP)} /2 (10) VTR CLK, DQS VCP CLK DQS VTR Vx Vx Vx Vx Vx VID (AC) VCP VICK VICK VICK VISO (min) VICK VISO (max) VSS |VID (AC)| 0 V Differential VISO VSS (11) (VTT) VREF (DC) ± 0.04 V (VDD = 2.5V, VDDQ = 1.8 V, f = 1 MHz, Ta = 25°C) (MAX) UNIT CIN (CLK CLK ) 1.5 2.5 0.25 pF CINC (CLK CLK ) 1.5 2.5 0.25 pF CI/O (DQ, DQS, DQS ) 2.5 4 0.5 pF CNC NC 4 pF : Rev 1.1 2005-11-08 5/47 TC59LM906AMG-37 TC59LM906AMG-37 (VDD = 2.5V ± 0.125V, VDDQ = 1.4V ~ 1.9V, TCASE = 0 ~ 85°C) IDD1S tCK = minIRC = min / 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN VDDQ, 1 = 4 IRC 2 280 1, 2 120 1, 2 90 1, 2 IDD2N tCK = min CS = VIH PD = VIH 0 V VIN VIL (AC) (max)VIH (AC) (min) VIN VDDQ : 4 × tCK 1 () IDD2P tCK = min CS = VIH PD = VIL () 0 V VIN VDDQ : (8 ) IDD4W 8 tCK = minIRC = min Burst Length = 4 CAS Latency = 5 0 V VIN VIL (AC) (max)VIH (AC) (min) VIN VDDQ 1 DQ DQS 1 2 450 1, 2 mA (8 ) IDD4R 8 tCK = minIRC = minIOUT = 0mA Burst Length = 4 CAS Latency = 5 0 V VIN VIL (AC) (max)VIH (AC) (min) VIN VDDQ 1 1 2 450 1,2 280 1, 2, 3 20 2 IDD5B tCK = minIREFC = min CAS Latency = 5 0 V VIN VIL (AC) (max)VIH (AC) (min) VIN VDDQ IREFC 2 DQ DQS 1 2 IDD6 : PD = 0.2 V0 V VIN VDDQ 1. tCKtRC IRC 2. VDD ­ VSS 3. IDD5B tREFI Rev 1.1 2005-11-08 6/47 TC59LM906AMG-37 TC59LM906AMG-37 (VDD = 2.5V ± 0.125V, VDDQ = 1.4V ~ 1.9V, TCASE = 0 ~ 85°C) () ILI ( 0 V VIN VDDQ 0 V) -5 5 µA ILO (0 V VOUT VDDQ) -5 5 µA IREF VREF -5 5 µA VOH = 1.420 V -5.6 VOL = 0.280 V 5.6 VOH = 1.420 V -9.8 IOH (DC) Normal Output Driver IOL (DC) IOH (DC) Strong Output Driver IOL (DC) VOL = 0.280 V 9.8 IOH (DC) (VDDQ = 1.7V~1.9V) VOH = 1.420 V -2.8 VOL = 0.280 V 2.8 VOH = 1.420 V -13.4 VOL = 0.280 V 13.4 VOH = VDDQ ­ 0.4V -4 VOL = 0.4V 4 VOH = VDDQ ­ 0.4V -8 VOL= 0.4V 8 1 Weak Output Driver IOL (DC) IOH (DC) Full Strength Output Driver IOL (DC) IOH (DC) Normal Output Driver IOL (DC) IOH (DC) Strong Output Driver IOL (DC) IOH (DC) (VDDQ = 1.4V~1.6V) Not defined Not defined -10 10 1 VOL= 0.4V 1, 2 VOH = VDDQ ­ 0.4V mA Weak Output Driver IOL (DC) IOH (DC) IOL (DC) : Full Strength Output Driver mA 1, 2 1. 2. Full Strength Output Driver Off Chip Driver (OCD)Full Strength Output Driver Rev 1.1 2005-11-08 7/47 TC59LM906AMG-37 TC59LM906AMG-37 AC (: 1, 2) (VDD = 2.5V ± 0.125V, VDDQ = 1.4V ~ 1.9V, TCASE = 0 ~ 85°C) tRC 22.5 3 tCK 3.75 8.5 3 tRAC 22.0 3 tCH 0.45 × tCK 3 tCL 0.45 × tCK 3 tCKQS DQS -0.45 0.45 3,8,10 tQSQ DQS ­ DQ 0.25 4 tAC -0.5 0.5 3,8,10 tOH -0.5 0.5 3, 8 tQSPRE DQS () tHP CLK (tCH, tCL ) tQSP 0.9 × tCK 1.1 × tCK 3, 8 min(tCH, tCL) 3 DQS () tHP-tQHS 4, 8 tQSQV tHP-tQHS 4, 8 tQHS DQ 0.055 × tCK +0.17 tDQSS DQS () 0.75 × tCK 1.25 × tCK 3 tDSPRE DQS () 0.25 ×tCK 4 0 3 tDSPREH DQS 1st 0.25 × tCK 3 tDSP DQS 0.35 × tCK 0.65 × tCK 4 tDSS DQS ­ CLK 0.75 3, 4 tDSH DQS ­ CLK 0.55 3, 4 tDSPST DQS () 0.4 × tCK 4 0.75 3, 4 tDSPRES DQS 1st tDSPSTH DS () ns tDS 0.35 4 tDH 0.35 4 tIS / 0.5 3 tIH / 0.5 3 Rev 1.1 2005-11-08 8/47 TC59LM906AMG-37 TC59LM906AMG-37 AC (: 1, 2) () -0.5 3,6,8 0.5 3,7,8 tLZ tHZ tQSLZ DQS -0.5 3,6,8 tQSHZ DQS -0.5 0.5 3,7,8 tQPDH PD 0 tPDEX 0.6 tT / 0.1 1 tFPDL PD () -0.5 × tCK 5 tOIT OCD 0 12 tREFI 0.4 3.9 tPAUSE 200 IRC /() 6 IRCD RDA/WRA-LAL () 1 LAL-RDA/WRA () 5 () 2 2 3 5 () µs RDA LAL-WRA BL = 2 3 IRBD 3 1 IRAS ns IRWD BL = 4 IWRD WRA LAL-RDA () 1 IRSC 6 IPD PD 1 IPDA PD 1 IPDV REF 22 IREFC 22 ICKD REF ( ) IREFC ILOCK DLL (RDA ) 200 cycle Rev 1.1 2005-11-08 9/47 TC59LM906AMG-37 TC59LM906AMG-37 AC VIH (min) (AC) VREF + 0.2 V VIL (max) (AC) VREF - 0.2 V VREF VDDQ/2 V VTT VREF V VSWING 0.7 V Vr VX (AC) V VID (AC) CLK, CLK 1.0 V SLEW 2.5 V/ns VOTR VDDQ/2 V 9 VDDQ VTT VIH min (AC) VSWING 25 VREF Output VIL max (AC) Measurement point VSS T T AC Test Load SLEW = (VIH min (AC) - VIL max (AC)/T : (1) VIH min (DC) VIL max (DC) (2) Cycle tCK 2 ( : tDQSS = 0.75 × tCK, tCK = 5 ns, 0.75 × 5 ns = 3.75 ns 3.8 ns) (3) (CLK CLK ) AC (4) DQS VREF DQS DQS DQS (5) tREFI (max) tREFI (min) tREFI (min) 8 400ns 3.2 µs (8 × 400 ns) 8 (6) VDDQ/2 ± 0.2 V (7) (8) (9) Normal Output Driver VDDQ = 1.4V 1.6V Strong Output Driver (10) tCK 6.0ns CK 6.0ns Speed version t tCKQS (MIN/MAX) = -0.6ns / 0.6ns, tAC (MIN/MAX) = -0.65ns / 0.65ns Rev 1.1 2005-11-08 10/47 TC59LM906AMG-37 TC59LM906AMG-37 (1) (VDDVDDQ) PD ( 0.2 V) (2) VDDQ VDD VDD (3) VREF VDDQ VDDQ (4) (CLK CLK ) 200 µs (5) NOP (DESL) PD (6) EMRS DLL A7A9 "0" (OCD calibration mode exit )(: 1, 2) (7) CAS (CL) (BT) (BL) ( 1) (8) 2 ( 1) (9) EMRS 200 (10) Off Chip Driver (OCD)OCD : (1) (6)(7)(8) (2) TC59LM906AMG TC59LM906AMG DQS (3) """" (4) DQ 2.5V(TYP) VDD 1.5V or 1.8V(TYP) VDDQ 1/2 VDDQ(TYP) VREF CLK CLK lRSC tPDEX lRSC lREFC lREFC 200us(min) PD lLOCK = 200clock cycle(min) lPDA Command DESLRDA MRS DESL op-code RDA MRS DESL WRA REF DESL WRA REF DESL op-code Address EMRS MRS DQ Hi-Z DQS Hi-Z DQS EMRS MRS Auto Refresh cycle Normal Operation Rev 1.1 2005-11-08 11/47 TC59LM906AMG-37 TC59LM906AMG-37 tCK tCK tCH tCL CLK CLK tIS tIH tIS 1st CS tIS 2nd tIH tIS 1st FN tIS A0~A13 BA0~BA2 tIH tIH 2nd tIH tIH tIS UA, BA LA · DQS DQS DQS tDS tDH tDS tDH tDS tDH tDS tDH DQ (input) · DQS DQS DQ (input) . CLK, CLK tCH tCL VIH VIH (AC) VIL (AC) VIL CLK CLK tT tT tCK VIH CLK VID (AC) CLK VX VX VIL VX Rev 1.1 2005-11-08 12/47 TC59LM906AMG-37 TC59LM906AMG-37 (Burst Length = 4) tCH tCL tCK CLK CLK tIS tIH LAL (after RDA) Input (control & addresses) DESL tCKQS tQSLZ tCKQS tQSPRE DQS/ DQS (output) tQSHZ Hi-Z PostAMGl PreAMGle tLZ tQSQ DQ (output) tCKQS tQSP tQSP Hi-Z tQSQV tQS Q0 tAC tQSQ tQSQV Q1 tAC Q2 tHZ Q3 tAC tOH DQS DQS DQS EMRS Rev 1.1 2005-11-08 13/47 TC59LM906AMG-37 TC59LM906AMG-37 (Burst Length = 4) tCH tCL tCK CLK CLK tIS tIH LAL (after WRA) Input (control & addresses) DESL tDSS tDSPRES tDSS tDSPSTH tDSPREH tDSP tDSP tDSP tDSPST DQS/ DQS (input) PreAMGle tDSPRE PostAMGl tDS tDS tDH DQ (input) D0 tDQSS tDS tDH D1 D2 tDH D3 tDQSS DQS DQS DQS EMRS Rev 1.1 2005-11-08 14/47 TC59LM906AMG-37 TC59LM906AMG-37 tREFI, tPAUSE, Ixxxx CLK CLK tREFI, tPAUSE, IXXXX tIS tIH tIS tIH Input (control & addresses) Command Command : "IXXXX""IRC""IRCD""IRAS" Rev 1.1 2005-11-08 15/47 TC59LM906AMG-37 TC59LM906AMG-37 (: 1, 2, 3) (: 4) · 1st CS FN BA2~BA0 A13~A9 A8 A7~A0 NOTES DESL Device Deselect H × × × × × - RDA Read with Auto-close L H BA UA UA UA - WRA Write with Auto-close L L BA UA UA UA - CS FN BA1~BA0 BA2 A13 A12~A9 A8 A7~A0 NOTES · 2nd LAL Lower Address Latch H × × V V × LA LA - REF Auto-Refresh L × × × × × × × - MRS Mode Register Set L × V L L L L V - : 1. L = Logic Low, H = Logic High, × = either L or H, V = Valid (specified value), BA = Bank Address, UA = Upper Address, LA = Lower Address 2. 3. SELFX PDEX CLK 4. 1 2 "" () CS FN BA2~BA0 A13~A9 A8 A7~A0 NOTES RDA (1st) L H BA UA UA UA - LAL (2nd) H × × × LA LA - () CS FN BA1~BA0 BA2 A13 A12~A9 A8 A7~A0 NOTES WRA (1st) L L BA BA UA UA UA UA - LAL (2nd) H × × VW0 VW1 × LA LA - : 6. BA2A13 BA2A13~ A11 Rev 1.1 2005-11-08 16/47 TC59LM906AMG-37 TC59LM906AMG-37 () (VW) VW0 VW1 Write All Words L × Write First One Word H × Reserved L L Write All Words H L Write First Two Words L H Write First One Word H H BL=2 BL=4 () FN BA2~BA0 A13~A8 RDA (1st) L H × × × - MRS (2nd) : CS L × V V V 8 CS FN BA2~BA0 A13~A8 A7~A0 NOTES 8. "" () Active WRA (1st) Auto-Refresh REF (2nd) PD A7~A0 NOTES n-1 n Standby H H L L × × × - Active H H L × × × × - CS FN BA2~BA0 A13~A8 () Active WRA (1st) Self-Refresh Entry PD Self-Refresh Continue Self-Refresh Exit A7~A0 NOTES n-1 n Standby H H L L × × × - REF (2nd) Active H L L × × × × 9, 10 Self-Refresh L L × × × × × - SELFX Self-Refresh L H H × × × × 11 CS FN BA2~BA0 A13~A8 Power Down Entry Power Down Continue Power Down Exit : 9. () PDEN PD A7~A0 NOTES n-1 n Standby H L H × × × × 10 Power Down L L × × × × × - PDEX Power Down L H H × × × × 11 PD REF tFPDL 10. PD DQ 11. PD Rev 1.1 2005-11-08 17/47 TC59LM906AMG-37 TC59LM906AMG-37 () PD n-1 n CS FN Idle H H H H H L H H H L L × H L L H L × × H L × × × × BA, UA BA, UA × × × DESL RDA WRA PDEN Row Active for Read H H H H L H H L L × H L H L × × × × × × LA Op-code × × × LAL MRS/EMRS PDEN MRS/EMRS Row Active for Write H H H H L H H L L × H L H L × × × × × × LA × × × × LAL REF PDEN REF (self) Read H H H H H L H H H L L × H L L H L × × H L × × × × BA, UA BA, UA × × × DESL RDA WRA PDEN H H H × × DESL H H H H L H H L L × L L H L × H L × × × BA, UA BA, UA × × × RDA WRA PDEN Data Write & Continue Burst Write to End Illegal Illegal Illegal Illegal Invalid Auto-Refreshing H H H H H L H H H L L × H L L H L × × H L × × × × BA, UA BA, UA × × × DESL RDA WRA PDEN NOP Idle after IREFC Illegal Illegal Self-Refresh Entry Illegal Refer to Self-Refreshing State Mode Register Accessing H H H H H L H H H L L × H L L H L × × H L × × × × BA, UA BA, UA × × × DESL RDA WRA PDEN NOP Idle after IRSC Illegal Illegal Illegal Illegal Invalid H L × L × × × × × × L H H × × PDEX L H L × × Invalid Maintain Power Down Mode Exit Power Down Mode Idle after tPDEX Illegal H L L L × L H H × × H L × × × × × × × × SELFX Invalid Maintain Self-Refresh Exit Self-Refresh Idle after IREFC Illegal Write Power Down Self-Refreshing : NOP Row activate for Read Row activate for Write Power Down Entry Illegal Refer to Power Down State 12 Begin Read Access to Mode Register Illegal Illegal Invalid Begin Write Auto-Refresh Illegal Self-Refresh Entry Invalid Continue Burst Read to End Illegal Illegal Illegal Illegal Invalid 13 13 13 13 14 12. 13. 14. tFPDL Rev 1.1 2005-11-08 18/47 TC59LM906AMG-37 TC59LM906AMG-37 MRS () (: 1) *1 ADDRESS *1 BA1 BA0 0 0 Register BA2, A13~A8 0 A7 *3 A6~A4 A3 A2~A0 CL BT BL TE A7 TEST MODE (TE) A3 BURST TYPE (BT) 0 Regular (default) 0 Sequential 1 Test Mode Entry 1 Interleave A2 A1 A0 *2 0 0 0 *2 0 0 1 2 Reserved*2 0 1 0 4 *2 0 1 1 A6 A5 A4 CAS LATENCY (CL) 0 0 × Reserved 0 1 0 Reserved 0 1 1 1 0 0 Reserved 1 0 1 5 1 1 0 Reserved 1 1 1 Reserved BURST LENGTH (BL) Reserved Reserved *2 *2 × × A10 A9~A7 A6 A5~A2 A1 DQS OCD DIC 0 DIC 1 *2 *2 EMRS () (: 4) ADDRESS *4 *4 BA1 BA0 0 1 Register BA2, A13~A12 0 A11 0 *6 A6 A1 0 0 Drive (1) 0 1 Strong Output Driver 1 0 Drive (0) 1 0 Weak Output Driver 1 0 0 Adjust mode 1 1 Full Strength Output Driver 1 1 1 DS Normal Output Driver 1 *5 OUTPUT DRIVE IMPEDANCE CONTROL (DIC) OCD Calibration mode exit A0 OCD Calibration default A9 A8 A7 0 0 0 0 0 0 Driver Impedance Adjustment A10 DLL SWITCH (DS) Disable 0 DLL Enable 1 1. 2. 3. 4. 5. 6. A0 0 : DQS Enable Enable 1 DLL Disable BA0 = 0 BA1 = 0 "Reserved" A7 "0" () BA0 = 1 BA1 = 0 A0 "0"() A11 "0"() Rev 1.1 2005-11-08 19/47 TC59LM906AMG-37 TC59LM906AMG-37 SELFREFRESH POWER DOWN SELFX ( PD = H) PDEX ( PD = H) PD = L PDEN ( PD = L) STANDBY (IDLE) PD = H AUTOREFRESH MODE REGISTER WRA RDA REF MRS ACTIVE (RESTORE) ACTIVE LAL LAL WRITE (BUFFER) READ Command input Automatic return 2 RDA WRA 1 Rev 1.1 2005-11-08 20/47 TC59LM906AMG-37 TC59LM906AMG-37 0 1 2 3 4 5 6 7 8 9 10 11 12 13 RDA 14 LAL 15 CLK CLK IRC = 6 cycles IRC = 6 cycles Command RDA LAL IRCD=1 cycle Address UA Bank Add. DESL IRAS = 5 cycles #0 LA RDA LAL IRCD=1 cycle UA DESL IRAS = 5 cycles LA IRCD=1 cycle UA #0 DESL LA #0 BL = 2 DQS/ DQS (output) Hi-Z CL = 5 DQ (output) Hi-Z CL = 5 Q0 Q1 Q0 Q1 BL = 4 DQS/ DQS (output) Hi-Z CL = 5 DQ (output) Hi-Z CL = 5 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Rev 1.1 2005-11-08 21/47 TC59LM906AMG-37 TC59LM906AMG-37 0 1 2 3 4 5 6 7 8 9 10 11 12 13 WRA 14 LAL 15 CLK CLK IRC = 6 cycles Command WRA LAL IRCD=1 cycle Address UA Bank Add. DESL IRC = 6 cycles WRA IRAS = 5 cycles LAL IRCD=1 cycle #0 LA UA DESL IRAS = 5 cycles DESL IRCD=1 cycle LA UA #0 LA #0 BL = 2 DQS/ DQS (input) WL = 4 DQ (input) WL = 4 D0 D1 D0 D1 BL = 4 DQS/ DQS (input) WL = 4 DQ (input) WL = 4 D0 D1 D2 D3 D0 D1 D2 D3 Rev 1.1 2005-11-08 22/47 TC59LM906AMG-37 TC59LM906AMG-37 / 0 1 2 3 4 5 6 7 8 9 10 11 12 13 RDA LAL UA 14 15 LA CLK CLK IRC = 6 cycles IRC = 6 cycles RDA LAL Address UA LA Bank Add. #0 Command BL = 2 DQS DQS DESL WRA LAL UA DESL LA #0 DESL #0 Hi-Z Hi-Z CL = 5 WL = 4 Hi-Z Q0 Q1 DQ D0 D1 BL = 4 DQS DQS Hi-Z Hi-Z WL = 4 CL = 5 DQ Hi-Z Q0 Q1 Q2 Q3 D0 D1 D2 D3 Rev 1.1 2005-11-08 23/47 TC59LM906AMG-37 TC59LM906AMG-37 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK IRBD = 2 cycles Command Address Bank Add. IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles RDA LAL RDA LA UA LA Bank "a" DESL Bank "b" RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL UA LAL UA IRBD = 2 cycles LA UA LA UA LA UA LA UA LA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" IRC (Bank"a") = 6 cycles IRC (Bank"b") = 6 cycles BL = 2 DQS/ DQS (output) Hi-Z CL = 5 CL = 5 DQ (output) Hi-Z Qa0Qa1 Qb0Qb1 Qa0Qa1 Qb0Qb1 BL = 4 DQS/ DQS (output) Hi-Z CL = 5 CL = 5 DQ (output) Hi-Z : Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2Qa3Qb0Qb1Qb2 lRC Rev 1.1 2005-11-08 24/47 TC59LM906AMG-37 TC59LM906AMG-37 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK IRBD = 2 cycles Command WRA LAL WRA LAL UA LA UA LA Address Bank Add. IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles Bank "a" Bank "b" WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL UA DESL LA UA LA UA LA UA LA UA LA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" IRC (Bank"a") = 6 cycles IRC (Bank"b") = 6 cycles BL = 2 DQS/ DQS (input) WL = 4 WL = 4 DQ (input) Da0Da1 Db0Db1 Da0 Da1 Db0 Db1 Dc0 Dc1 BL = 4 DQS DQS (input) WL = 4 WL = 4 DQ (input) Da0Da1Da2Da3Db0Db1Db2Db3 : Da0 Da1 Da2 Da3 Db0 Db1 Db2Db3Dc0Dc1 lRC Rev 1.1 2005-11-08 25/47 TC59LM906AMG-37 TC59LM906AMG-37 / (BL = 2) 0 1 2 3 4 5 6 7 8 LAL RDA LAL 9 10 11 12 13 14 15 LAL RDA LAL DESL WRA LA UA LA CLK CLK IRBD = 2 cycles Command WRA LAL RDA IWRD = 1 cycle Address Bank Add. UA Bank "a" LA UA LAL DESL WRA IRWD = 2 cycles IWRD = 1 cycle LA Bank "b" UA Bank "c" LA UA DESL WRA IRWD = 2 cycles LA Bank "d" UA Bank "a" UA Bank "b" Bank "c" IRC (Bank"a") IRC (Bank"b") DQS DQS Hi-Z Hi-Z CL = 5 WL = 4 DQ : Hi-Z Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1 lRC Rev 1.1 2005-11-08 26/47 TC59LM906AMG-37 TC59LM906AMG-37 / (BL = 4) 0 1 2 3 4 5 6 7 8 9 WRA LAL RDA 10 LAL 11 12 13 14 15 WRA LAL RDA LAL CLK CLK IRBD = 2 cycles Command WRA LAL RDA IWRD = 1 cycle Address Bank Add. UA Bank "a" LA UA DESL LAL IRWD = 3 cycles LA IWRD = 1 cycle UA Bank "b" LA Bank "c" UA DESL IRWD = 3 cycles LA Bank "d" IWRD = 1 cycle UA Bank "a" LA UA LA Bank "b" IRC (Bank"a") IRC (Bank"b") DQS DQS Hi-Z Hi-Z CL = 5 WL = 4 DQ : Hi-Z Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 lRC Rev 1.1 2005-11-08 27/47 TC59LM906AMG-37 TC59LM906AMG-37 (VW) 0 1 2 3 4 5 6 7 WRA LAL UA 8 9 10 11 12 13 14 15 LA=#1 VW=1 CLK CLK BL = 2, SEQUENTIAL MODE Command Address Bank Add. WRA LA=#3 VW=All Bank "a" DESL LAL UA IRC =6 VW=A11 DESL Bank VW=1 "a" VW0 = Low VW1 = don't care VW0 = High VW1 = don't care WL = 4 WL = 4 DQS/ DQS (input) DQ (input) D0 D1 Lower Address D0 #3 #2 #1 (#0) Last one data is masked. BL = 4, SEQUENTIAL MODE Command Address Bank Add. WRA LAL UA DESL LA=#1 VW=1 Bank "a" IRC =6 VW=1 VW0 = High VW1 = High WRA UA DESL LAL LA=#2 VW=2 Bank VW=2 "a" VW0 = Low VW1 = High WL = 4 WL = 4 DQS/ DQS (input) DQ (input) D0 Lower Address D0 D1 #1 (#2)(#3)(#0) #2 #3 (#0)(#1) Last three data are masked. Last two data are masked. : DQS ( DQS ) MRS Rev 1.1 2005-11-08 28/47 TC59LM906AMG-37 TC59LM906AMG-37 (CL = 5, BL = 4) 0 1 2 3 4 5 6 7 8 9 10 n-2 n-1 n n+1 n+2 CLK CLK IPDA RDA Address LAL UA Command DESL LA DESL RDA or WRA UA tIS IPD = 1 cycle tIH PD tQPDH DQS (output) Hi-Z DQS (output) tPDEX lRC(min) , tREFI(max) Hi-Z Hi-Z CL = 5 DQ (output) Hi-Z Q0 Q1 Q2 Q3 Power Down Entry : Hi-Z Power Down Exit PD PD tREFI(max.) PD PD lPDA Rev 1.1 2005-11-08 29/47 TC59LM906AMG-37 TC59LM906AMG-37 (CL = 5, BL = 4) 0 1 2 3 4 5 6 7 8 9 10 n-2 n-1 n n+1 n+2 CLK CLK IPDA Command Address RDA LAL UA DESL LA DESL RDA or WRA UA tIS IPD = 1 cycle tIH PD tQPDH WL = 4 2 clock cycles tPDEX lRC(min) , tREFI(max) DQS (input) DQS (input) WL = 4 DQ (input) D0 D1 D2 D3 : PD LAL WL+2 PD tREFI(max.) PD PD lPDA Rev 1.1 2005-11-08 30/47 TC59LM906AMG-37 TC59LM906AMG-37 (CL = 5, BL = 2) 1 2 4 5 6 7 15 RDA or WRA LAL Valid (opcode) 3 14 UA LA BA0="0" BA1="0" BA2="0" 0 BA 8 9 10 11 12 13 CLK CLK IRSC RDA LAL A13~A0 UA BA0~BA2 DESL LA BA Command RDA MRS DESL CL + BL/2 Hi-Z DQS (output) Hi-Z DQS DQ (output) Q0 Q1 : LAL MRS RDA CL+BL/2() Rev 1.1 2005-11-08 31/47 TC59LM906AMG-37 TC59LM906AMG-37 (CL = 5, BL = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK IRSC WRA LAL A13~A0 UA BA0~BA2 BA LAL UA LA BA0="0" BA1="0" BA2="0" RDA DESL RDA or WRA Valid (opcode) LA Command BA MRS DESL WL+BL/2 DQS (input) DQS (input) DQ (input) D0 D1 D2 D3 : LAL MRS RDA WL+BL/2() Rev 1.1 2005-11-08 32/47 TC59LM906AMG-37 TC59LM906AMG-37 (CL = 5, BL = 2) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDA or WRA LAL Valid (opcode) UA LA BA0="1" BA1="0" BA2="0" BA CLK CLK IRSC RDA LAL A13~A0 UA BA0~BA2 DESL LA BA Command RDA MRS DESL CL + BL/2 DQS (output) Hi-Z Hi-Z DQS DQ (output) : Q0 Q1 LAL EMRS RDA CL+BL/2() DLL EMRS DLL Rev 1.1 2005-11-08 33/47 TC59LM906AMG-37 TC59LM906AMG-37 (CL = 5, BL = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK IRSC WRA LAL A13~A0 UA BA0~BA2 BA LAL UA LA BA0="1" BA1="0" BA2="0" RDA DESL RDA or WRA Valid (opcode) LA Command BA MRS DESL WL+BL/2 DQS (input) DQS (input) DQ (input) D0 D1 D2 D3 : LAL EMRS RDA WL+BL/2() DLL EMRS DLL Rev 1.1 2005-11-08 34/47 TC59LM906AMG-37 TC59LM906AMG-37 (CL = 5, BL = 4) 0 1 2 3 4 5 6 7 n-1 n n+1 n+2 RDA or WRA 8 LAL or MRS or REF CLK CLK IRC = 6 cycles Command RDA LAL Bank, Address Bank, UA IREFC = 18 cycles LA IRCD = 1 cycle DQS/ DQS (output) DESL WRA IRAS = 5 cycles REF IRCD = 1 cycle Hi-Z Hi-Z CL = 5 DQ (output) Hi-Z Hi-Z : Q0 Q1 Q2 Q3 IREFC 18 tREFI tREFI 8 t1 t2 t3 t7 t8 CLK WRA REF WRA REF WRA REF WRA REF WRA REF 8 Refresh cycle tREFI = Total time of 8 Refresh cycle 8 = t1 + t2 + t3 + t4 + t5 + t6 + t7 + t8 8 tREFI Rev 1.1 2005-11-08 35/47 TC59LM906AMG-37 TC59LM906AMG-37 0 1 2 3 4 m-1 5 m+1 m CLK CLK IRCD = 1 cycle WRA Command IREFC REF DESL tFPDL (min) tFPDL (max) Auto Refresh PD Self Refresh Entry IPDV *2 ICKD tQPDH Hi-Z DQS/ DQS (output) DQ (output) Hi-Z Qx : 1. 2. tFPDL(min) tFPDL(max) lPDV PD tFPDL(max) lPDV 3. PD REF lCKD 4. LAL REF WL+3 () 0 1 2 m-1 m+1 m m+2 n-1 n n+1 p-1 p CLK CLK *2 IREFC *3 DESL Command IREFC WRA *4 REF *4 IRCD = 1 cycle Command (1st)*5 Command (2nd)*5 DESL RDA *6 LAL *6 IRCD = 1 cycle PD tPDEX DQS/ DQS (output) Hi-Z DQ (output) ILOCK Hi-Z Self-Refresh Exit : 1. 2. PD 3. PD IREFC DESL 4. 5. IREFC 6. (RDA + LAL) ILOCK Rev 1.1 2005-11-08 36/47 TC59LM906AMG-37 TC59LM906AMG-37 TM Network FCRAM FCRAMTM Fast Cycle Random Access Memory FCRAMTM : CLK & CLK CLK CLK CS FN CLK CLK DQS DQ CLK CLK CLK CLK : PD PD PD SDRAM CKE PD & : CS & FN CS FN FCRAMTM CS FN 2 : BA0~BA2 BA0 ~ BA2 RDA WRA MRS BA0 BA1 BA0 BA1 BA2 Bank #0 0 0 0 Bank #1 1 0 0 Bank #2 0 1 0 Bank #3 1 1 0 Bank #4 0 0 1 Bank #5 1 0 1 Bank #6 0 1 1 Bank #7 1 1 1 BA2 A14 4 : A0~A13 RDA WRA LAL A0~A13 8 A0~A13 A0~A8 4 A0~A13, BA2(A14) A0~A8 Rev 1.1 2005-11-08 37/47 TC59LM906AMG-37 TC59LM906AMG-37 : DQ0~DQ7 DQ15 DQ0~DQ15 DQS / DQ0~DQ15 DQS / : DQS, DQS DQS DQS / DQS DQS TC59LM906AMG TC59LM906AMG DQS DQS DQS DQS DQS DQS DQS DQS DQS VREF DQS : VDDVDDQVSSVSSQ VDD VSS VDDQ VSSQ : VREF VREF Rev 1.1 2005-11-08 38/47 TC59LM906AMG-37 TC59LM906AMG-37 TC59LM906AMG TC59LM906AMG 2 1 2 (1 + 2 = RDA + LAL) / RDA RDA (CLK ) LAL DQS/ DQS /() LAL CAS CAS RDA lRC DQS (1 + 2 = WRA + LAL) / WRA WRA (CLK ) LAL DQS/ DQS /() DQS/ DQS LAL CAS -1 LAL (VW)DQS/ DQS CAS WRA lRC DQS (1 + 2 = WRA + REF) TC59LM906AMG TC59LM906AMG SDRAM WRA REF WRA WRA (CLK ) LAL REF lREFC 3.9 µs 8 400ns 3.2 µs (8 × 400 ns) 8 (1 + 2 = WRA + REF with PD = "L") PD WRA REF tFPDL "Low" 3.9µs lREFC DESL lCKD PD PD DESL "Low""High"DESL lREFC lREFC 1 ( PD = "L") Hi-Z TC59LM906AMG TC59LM906AMG PD "Low" PD PD "High" PD "High" CLK DESL Rev 1.1 2005-11-08 39/47 TC59LM906AMG-37 TC59LM906AMG-37 (MRS) (EMRS) (1 + 2 = RDA + MRS) RDA MRS RDA RDA (CLK ) LAL MRS A0~A13BA0 A13BA0~BA2 MRS BA0 BA1 4 4 (R-1) (R-2) (R-3) CAS (R-4) 4 (E-1) DLL / DLL (E-2) (E-3) OCD (Off-Chip Driver) (E-4) DQS 1 MRS OFF · / (BA0, BA1) MRS MRS BA1 BA0 Mode Register Set 0 0 Regular MRS 0 1 Extended MRS 1 × Reserved (R-1) (A2 A0)(BL) A2 A0 2 4 A2 A1 A0 BURST LENGTH 0 0 0 Reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 Reserved 1 × × Reserved (R-2) (A3)(BT) A3 "0" A3 "1" 2 4 A3 BURST TYPE 0 Sequential 1 Interleave Rev 1.1 2005-11-08 40/47 TC59LM906AMG-37 TC59LM906AMG-37 · (A3) (+1) CLK CLK Command RDA LAL DQS/ DQS Data Data Data Data 0 1 2 3 DQ CAS Latency = 5 Addressing sequence for Sequential mode DATA BURST LENGTH Data 0 n Data 1 n+1 2 ( LA0) LA0 LA1 Data 2 n+2 Data 3 · ACCESS ADDRESS n+3 4 ( LA1, LA0) LA1 LA2 Addressing sequence for Interleave mode DATA ACCESS ADDRESS BURST LENGTH Data 0 Data 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 2 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 3 (R-3) A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 words 4 words CAS (A6 A4) RDA LAL CAS CLK LAL CAS -1 A6 A5 A4 CAS LATENCY 0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 Reserved 1 0 1 5 1 1 0 Reserved 1 1 1 Reserved (R-4) (A7) "0" (R-5) · (A8 A13BA2 A13BA2) "0" Rev 1.1 2005-11-08 41/47 TC59LM906AMG-37 TC59LM906AMG-37 (E-1) DLL (A0) DLL A0 "0" DLL (E-2) (A1/A6)(DIC) 4 EMRS OCD calibration default (A7~A9 = 1 at EMRS) OCD calibration mode exit (A7~A9 = 0) A6 A1 OUTPUT DRIVER IMPEDANCE CONTROL 0 0 Normal Output Driver 0 1 Strong Output Driver 1 0 Weak Output Driver 1 1 Full Strength Output Driver (E-3) Off-Chip Driver (OCD) (Full Strength Output Driver ) (A7~A9) DIC(E-2)Full Strength Output Driver OCD DIC OCD OCD EMRS A1 A6 "1" OCD OCD "OCD calibration mode exit" MRS should be set before entering OCD impedance adjustment. Start EMRS: OCD calibration mode exit EMRS: Drive(1) DQ &DQS High; DQS Low Test EMRS: Drive(0) DQ &DQS Low; DQS High ALL OK ALL OK Need Calibration Test Need Calibration EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: Enter Adjust Mode EMRS: Enter Adjust Mode BL=4 code Input to all DQs Inc, Dec, or NOP BL=4 code Input to all DQs Inc, Dec, or NOP EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit End Rev 1.1 2005-11-08 42/47 TC59LM906AMG-37 TC59LM906AMG-37 OCD OCD EMRS Drive (1) DQ DQS "High" DQS "Low"Drive (0) DQ DQS "Low" DQS "High""Adjust mode"BL4 A9 A8 A7 Operation 0 0 0 OCD calibration mode exit 0 0 1 Drive (1) DQ, DQS high and DQS low 0 1 0 Drive (0) DQ, DQS low and DQS high 1 0 0 Adjust mode 1 1 1 OCD calibration default OCD EMRS "Adjust mode" 4 Burst Length BL=4 DQ 4 DT0DT1DT2DT3 BL=4 DQ 16 "Decrease""Increase" Off-Chip Driver Program 4bit burst code inputs to all DQs Operation DT0 DT1 DT2 DT3 Pull-up driver strength Pull-down driver strength 0 0 0 0 NOP (No operation) NOP (No operation) 0 0 0 1 Increase by 1 step NOP 0 0 1 0 Decrease by 1 step NOP 0 1 0 0 NOP Increase by 1 step 1 0 0 0 NOP Decrease by 1 step 0 1 0 1 Increase by 1 step Increase by 1 step 0 1 1 0 Decrease by 1 step Increase by 1 step 1 0 0 1 Increase by 1 step Decrease by 1 step 1 0 1 0 Decrease by 1 step Decrease by 1 step Other Combinations Reserved DT0~DT3 Driver strength is controlled within the following range by OCD impedance adjustment IOH (DC) IOL (DC) Output Source DC Current for VDDQ = 1.7V~1.9V Full Strength VDDQ = 1.7V VOH = 1.420V Output Driver Output Sink DC Current for VDDQ = 1.7V~1.9V VDDQ = 1.7V VOL = 0.280V -14.0 -18.7 mA 14.0 18.7 Rev 1.1 2005-11-08 43/47 TC59LM906AMG-37 TC59LM906AMG-37 OCD adjust mode Command RDA OCD calibration mode exit EMRS NOP NOP NOP NOP RDA EMRS NOP CLK CLK WL 1clock DQS DQS_in tDS tDH DT0 DQ_in DT1 DT2 DT3 Drive (1) Drive (0) "enter drive mode" tOIT "OCD calibration mode exit" tOIT OCD calibration mode exit Enter Drive mode Command RDA EMRS NOP NOP RDA EMRS NOP CLK CLK DQS, DQS DQS high & DQS low for Drive (1), DQS low & DQS high for Drive (0) DQs high for Drive (1), DQs low for Drive (0) DQ tOIT 012ns (E-4) tOIT 012ns DQS (A10), ( DQS ) DQS A10 DQS Enable 0 Disable 1 Enable (E-5) (A2A5, A11A13 A11A13, BA2) "0" Rev 1.1 2005-11-08 44/47 TC59LM906AMG-37 TC59LM906AMG-37 P-BGA64-1317-1 P-BGA64-1317-1.00AZ 0.2 S B 0.2 S A 16.5 0 13.086 -0.15 12.7 0 10.975 -0.15 0.15 1.20MAX 20MAX 0.2 S S 0.4 0.05 0.15MIN 15MIN 0.1 S 0.5 0.05 0.08 S AB 1.25 B R P N M L K J H G F E D C B A 3.85 INDEX A 1.0 4 5 6 1.5 1.5 1 2 3 3.85 1.85 1.0 2.0 : K, F 4 NC : 0.23g () Rev 1.1 2005-11-08 45/47 TC59LM906AMG-37 TC59LM906AMG-37 - Rev 0.9 (2004 2 24 ) - Rev 0.91 (2004 3 16 ) · Q R (57 ) - Rev 0.92 (2004 4 21 ) · DC, AC (5 ) - VICK(DC): DC Input Voltage - VID(DC): CLK, /CLK (DC) - VID(AC): CLK, /CLK (AC) - VX: CLK, /CLK (AC) - VID(AC) 0.55V 0.5V - VISO(AC): CLK, /CLK (AC) · CLK VTR CLK VCP (6 ) · (10) (6 ) VTR CLKDQS VCP CLK DQS - Rev 0.93 (2004 6 9 ) · tOIT (OCD ) (10, 56 ) · (P-BGA64-1317-1 P-BGA64-1317-1.00AZ) (1 ) - Rev 1.0 (2004 8 20 ) · "-45" version · (4141517 ) · 8 7 (78 ) · 2 (7 ) : : VDD ­ VSS · 10 (911 ) · (0.23g) (57 ) - Rev 1.1 (2005 11 8 ) · "-50" version · 16 I/O · CAS Latency=3,4 · AC Timing spec lPDA=1cycle (11, 29, 30 ) · lPDA=1cycle*4 lPDA (36 ) Rev 1.1 2005-11-08 46/47 TC59LM906AMG-37 TC59LM906AMG-37 030519TBA 030519TBA · · ( ) ( ) ( "" ) · · · · Rev 1.1 2005-11-08 47/47