TAS5100 SLLS419B TAS5000 TAS3001 TAS5100DAP TAS5100IDAP SLAS270 SLAA117 SLAA114 - Datasheet Archive

 

SLLS419B ­ MARCH 2001 ­ REVISED NOVEMBER 2001 TRUE DIGITAL AUDIO AMPLIFIER TAS5100 PWM POWER OUTPUT STAGE D Internet

 

TAS5100 TAS5100 SLLS419B SLLS419B ­ MARCH 2001 ­ REVISED NOVEMBER 2001 TRUE DIGITAL AUDIO AMPLIFIER TAS5100 TAS5100 PWM POWER OUTPUT STAGE D Internet Music Appliance D Mini/Micro Component Systems FEATURES D TAS5000 TAS5000 + TAS5100 TAS5100 TDAA System-High D D D D D D D D Quality Digital Audio Amplification 93-dB Dynamic Range (TDAA System) THD+N < 0.08% (1 kHz, 1 W to 30 W RMS Into 6 ) Power Efficiency > 90% Into 8- Load Low Profile, SMD 32-Pin PowerPAD Package Requires No Heat-Sink When Using Recommended Layout 30-W RMS Continuous Power Into 4 to 8 Self-Protecting Design 3.3-V Digital Interface EMI Compliant When Used With Recommended System Design DESCRIPTION True digital audio amplifier (TDAA) is a new paradigm in digital audio. The TDAA system currently consists of the TAS5000 TAS5000 PCM-PWM modulator device + TAS5100 TAS5100 PWM power output device. This system accepts a serial PCM digital audio stream and converts it to a 3.3-V PWM audio stream (TAS5000 TAS5000). The TAS5100 TAS5100 device then provides a large-signal PWM output. This digital PWM signal is then demodulated providing power output for driving loudspeakers. This patented technology provides low-cost, high-quality, high-efficient digital audio applicable to many audio systems developed for the digital age. The TAS5100 TAS5100 is a single-channel PWM power audio device. It contains integrated gate drivers, four matched and electrically isolated enhancement- mode N-channel power DMOS transistors. Also, included are protection and fault-reporting circuitry. This device is optimized for use with the TAS5000 TAS5000 digital modulator. APPLICATIONS D DVD Receiver D Home Theater D Car Audio Amplifiers and Head Units TYPICAL TDAA STEREO AUDIO SYSTEM Left TAS5100 TAS5100 · · · · · Volume EQ DRC Bass Treble L-C Filter TAS5100 TAS5100 Digital Audio · TAS3001 TAS3001 · DSP · SPDIF · 1394 L-C Filter TAS5000 TAS5000 Right · Serial Audio Input Port · Internal PLL · PCM­PWM Modulator · 2 H-Bridge Power Devices Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD and Equibit are trademarks of Texas Instruments. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com 1 TAS5100 TAS5100 SLLS419B SLLS419B ­ MARCH 2001 ­ REVISED NOVEMBER 2001 terminal assignments The TAS5100 TAS5100 is offered in a thermally enhanced 32-pin HTSSOP surface-mount package (DAP). DAP PACKAGE (TOP VIEW) PWM_AP PWM_AM ERR1 ERR0 SHUTDOWN DVDD DVSS DVSS DVSS VRFILT BIAS_A BIAS_B PWDN RESET PWM_BM PWM_BP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PVDDA2 LDROUTA BOOTSTRAPA PVDDA1 PVDDA1 OUTPUTA OUTPUTA PVSS PVSS OUTPUTB OUTPUTB PVDDB1 PVDDB1 BOOTSTRAPB LDROUTB PVDDB2 ordering information TA 0°C to 70°C TAS5100DAP TAS5100DAP PACKAGE ­40°C to 85°C TAS5100IDAP TAS5100IDAP references TAS5000 TAS5000 Digital Audio PWM Process Data Manual ­ TI Literature Number SLAS270 SLAS270 System Design Considerations for True Digital Audio Power Amplifiers ­ TI Literature Number SLAA117 SLAA117 Digital Audio Measurements ­ TI Literature Number SLAA114 SLAA114 PowerPAD Thermally Enhanced Package ­ TI Literature Number SLMA002 SLMA002 2 www.ti.com TAS5100 TAS5100 SLLS419B SLLS419B ­ MARCH 2001 ­ REVISED NOVEMBER 2001 PVDDA1 PVDDA1 BOOTSTRAPA PVDDA2 LDROUTA functional block diagram 1/2 H-Bridge LDR OUTPUTA PWM_AP PWM_AM DIFF RCVR OUTPUTA Boot Strap Gate Drive PVSS BIAS_A PWDN RESET SHUTDOWN ERR1 ERR0 Control/Sense Circuit Bandgap Reference LDROUTB PVDDB2 VRFILT BOOTSTRAPB PVDDB1 1/2 H-Bridge BIAS_B PVDDB1 LDR DIFF RCVR OUTPUTB Boot Strap Gate Drive OUTPUTB PVSS DVSS PWM_BP DVDD PWM_BM www.ti.com 3 TAS5100 TAS5100 SLLS419B SLLS419B ­ MARCH 2001 ­ REVISED NOVEMBER 2001 suggested system block diagrams See application note SLAA117 SLAA117 for more details. Digital Audio · USB · IEEE 1394 · SPDIF · ADC · Automotive MOST Network Left TAS3001 TAS3001 IIC Audio Control TAS5100 TAS5100 TAS5000 TAS5000 Right TAS5100 TAS5100 · Digital Parametric EQ · Serial Audio Input Port · Volume · Internal PLL · DRC · 2 H-Bridges · Bass · Treble Figure 1. System #1: Stereo Configuration With TAS3001 TAS3001 Digital Audio Processor 4 www.ti.com TAS5100 TAS5100 SLLS419B SLLS419B ­ MARCH 2001 ­ REVISED NOVEMBER 2001 suggested system block diagrams (continued) TAS5000 TAS5000 Home Theater DVD 6-Channel Encoded Digital Audio Source 6 TI DSP · Dolby AC-3 · DTS · Volume · EQ · DRC · Bass · Treble Left Right TAS5100 TAS5100 Surround Left CH2 CH3 TAS5000 TAS5000 TAS5100 TAS5100 TAS5100 TAS5100 CH1 CH4 TAS5100 TAS5100 Surround Right TAS5000 TAS5000 TAS5100 TAS5100 Center TAS5100 TAS5100 CH5 Subwoofer CH6 TAS5100 TAS5100 Figure 2. System #3: 6-Channel Audio Playback www.ti.com 5 TAS5100 TAS5100 SLLS419B SLLS419B ­ MARCH 2001 ­ REVISED NOVEMBER 2001 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION BIAS_A 11 I Connect external resistor to DVSS. See application note SLAA117 SLAA117 BIAS_B 12 I Connect external resistor to DVSS. See application note SLAA117 SLAA117 BOOTSTRAPA 30 O Bootstrap capacitor pin for H-bridge A BOOTSTRAPB 19 O Bootstrap capacitor pin for H-bridge B DVDD 6 I 3.3-V digital voltage supply for logic DVSS 7, 8, 9 I Digital ground for logic is internally connected to PVSS. All three pins must be tied together but not connected externally to PVSS. See Figure 5. ERR1 3 O Error/warning report indicator. This output is open drain with internal pullup resistor. ERR0 4 O Error/warning report indicator. This output is open drain with internal pullup resistor. LDROUTA 31 O Low voltage drop-out regulator output A (not to be used to supply current to external circuitry) LDROUTB 18 O Low voltage drop-out regulator output B (not to be used to supply current to external circuitry) OUTPUTA 26, 27 O H-bridge output A OUTPUTB 22, 23 O H-bridge output B PVDDA1 28, 29 I High voltage power supply, H-bridge A PVDDA2 32 I High voltage power supply for low-dropout voltage regulator A-side PVDDB1 20, 21 I High voltage power supply, H-bridge B PVDDB2 17 I High voltage power supply for low-dropout voltage regulator B-side PVSS 24, 25 I High voltage power supply ground PWDN 13 I Power down = 0, normal mode = 1 PWM_AP 1 I PWM input A(+) PWM_AM 2 I PWM input A(­) PWM_BP 16 I PWM input B(+) PWM_BM 15 I PWM input B(­) RESET 14 I Reset and mute mode = 0, normal mode = 1, when in reset mode, H-bridge MOSFETs are in low-low output state. Asserting the RESET signal low causes all fault conditions to be cleared. SHUTDOWN 5 O Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0, when device is in shutdown mode the H-bridge MOSFETs are in low-low output state. The latched output can be cleared by asserting the RESET signal. This output is open drain with internal pullup resistor. VRFILT 10 O A filter capacitor must be added between VRFILT and DVSS pins. NOTE: The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS5000 TAS5000 output pins, and never left floating. Floating PWM input pins will cause an illegal PWM input state signal to be asserted. Dual pins: OUTPUTA, OUTPUTB, PVDDA1 and PVDDB1 must have both pins connected externally to the same point on the circuit board, respectively. Both PVSS pins must also be connected together externally. These multiple pins are for the high current DMOS output devices. Failure to connect all the multiple pins to the same respective node will result in excessive current flow in the internal bond wires and can cause the device to fail. All electrical characteristics are specified and measured with all of the multiple pins connected to the same node, respectively. 6 www.ti.com TAS5100 TAS5100 SLLS419B SLLS419B ­ MARCH 2001 ­ REVISED NOVEMBER 2001 functional description PWM H-bridge state control The digital interface control signals consists of PWM_AP, PWM_AM, PWM_BP, and PWM_BM. These signals are a complementary differential signal format for the A-side H-bridge and the B-side H-bridge. bootstrapped gate drive The TAS5100 TAS5100 includes 2 dedicated bootstrapped power supplies. A bootstrap capacitor is connected between the individual bootstrap pin and the associated output as described in the application note SLAA117 SLAA117. For example, a capacitor will be connected between the BOOTSTRAPA pin and OUTPUTA pin, and another capacitor will be connected between the BOOTSTRAPB pin and the OUTPUTB pin. The bootstrap power supply minimizes the number of high voltage power supply levels externally supplied to the system while providing a low noise supply level for driving the high-side N-channel DMOS transistors. See application note SLAA117 SLAA117 for details. low-dropout voltage regulator Two on-chip low-dropout voltage regulators (LDO) are provided to minimize the number of external power supplies needed for the system. These voltage regulators are for internal circuits only and cannot be used for external circuitry. Each LDO is dedicated to an H-bridge and its gate driver. An LDO output capacitor is connected between the individual LDO output pin and the associated output return as described in the application note SLAA117 SLAA117. For example, a capacitor will be connected between the LDROUTA pin and PVSS pin, and another capacitor will be connected between the LDROUTB pin and PVSS pin. high-current H-bridge output stage The positive outputs of the H-bridge are the two OUTPUTA pins. The negative outputs of the H-bridge are the two OUTPUTB pins. The logic for the input command to H-bridge outputs is described in the H-bridge output mapping section below. When the TAS5100 TAS5100 is in the normal mode, as seen in the H-bridge output mapping tables, the outputs are decoded from the inputs. However, the TAS5100 TAS5100 is immediately shut down if any of the following error conditions occur: over-current, over-temperature, low regulator output voltage, or an illegal PWM input state is applied. For these conditions, the outputs are set to the appropriate disabled state as specified in the H-bridge output mapping section, and the SHUTDOWN pin is set low. H-bridge output mapping The A-side H-bridge output is designed to the following truth table: INPUTS OUTPUTS DESCRIPTION RESET PWDN PWM_AP PWM_AM SHUTDOWN X X X X 0 OUTPUTA 0 or Hi-Z X 0 X X 1 Hi-Z 0 1 X X 1 0 Reset 1 1 0 0 0 0 Shutdown 1 1 0 1 1 0 Normal 1 1 1 0 1 1 Normal 1 1 1 1 0 0 Output is 0 for low voltage, over temperature, and illegal input. Hi-Z is for over current. www.ti.com Shutdown Powerdown Shutdown 7 TAS5100 TAS5100 SLLS419B SLLS419B ­ MARCH 2001 ­ REVISED NOVEMBER 2001 H-bridge output mapping (continued) The B-side H-bridge output is designed to the following truth table: INPUTS OUTPUTS DESCRIPTION RESET PWDN PWM_BP PWM_BM SHUTDOWN X X X X 0 OUTPUTB 0 or Hi-Z X 0 X X 1 Hi-Z Powerdown 0 1 X X 1 0 Reset 1 1 0 0 0 0 Shutdown 1 1 0 1 1 0 Normal 1 1 1 0 1 1 Normal Shutdown 1 1 1 1 0 0 Output is 0 for low voltage, over temperature, or illegal input. Hi-Z is for over current. Shutdown control/sense circuitry The control/sense circuitry consists of the following 3.3-V logic level pins: PWDN, RESET, ERR0, ERR1, and SHUTDOWN. The active-low PWDN input pin powers down all internal circuitry and forces the H-bridge outputs to the Hi-Z state. When the PWDN pin is low, the open drain ERR0, ERR1, and SHUTDOWN pins are also disabled so that their outputs can be pulled high. The active-low RESET input pin forces the H-bridge outputs to the low-low state and resets the over-current shutdown latch. The PWDN pin overrides the RESET pin. The ERR0, ERR1, and SHUTDOWN outputs indicate the following conditions in the TAS5100 TAS5100 as shown in the table below. These three outputs are open-drain connections with internal pullup resistors so that wire-ORed connections can be made by the user with other external control devices. The short circuit protect error condition will latch the TAS5100 TAS5100 in this shutdown state and force the H-bridge outputs to the Hi-Z state until the device is reset by means of the RESET pin. The illegal PWM input state, over-temperature, and low regulator voltage error conditions will not latch the device in the shutdown condition. Instead the H-bridge outputs are forced to the low-low state and the TAS5100 TAS5100 will return to normal operation as soon as the error condition ends. Loss of clocking PWM signal is also considered an illegal PWM input state. SHUTDOWN ERR0 OUTPUTA OUTPUTB 0 0 Illegal PWM input state Low Low 0 0 1 Short circuit protect (latch) Hi-Z Hi-Z 0 1 0 Over temperature protect Low Low 0 1 1 Low regulator voltage protect Low Low 1 0 0 Reserved - - 1 0 1 Reserved - - 1 1 0 High temperature ­ warning Normal Normal 1 8 ERR1 0 FUNCTION 1 1 Normal operation Normal Normal www.ti.com TAS5100 TAS5100 SLLS419B SLLS419B ­ MARCH 2001 ­ REVISED NOVEMBER 2001 device operation power sequences system power-up/power-down sequencing The recommended power-up/power-down sequence is shown in Figure 3. For proper operation the RESET signal should be kept LOW when both DVDD and output power (PVDDA1, PVDDA2, PVDDB1, and PVDDB2) are being applied. The RESET signal should remain LOW for at least 1 ms after output power is applied. DVDD PWDN > 1 ms > 1 ms PVDDA1 PVDDA2 PVDDB1 PVDDB2 > 100 µs RESET For most applications, it is recommended that pin 13 (PWDN) be connected directly to pin 6 (DVDD). Figure 3. Power-Up/Power-Down Sequence RESET function The device is put into a reset condition when the (active low) RESET signal is asserted. While in the reset state, the input H-bridge control signals consisting of PWM_AP, PWM_AM, PWM_BP, and PWM_BM are ignored, and the H-bridge MOSFETs are placed in a state where OUTPUTA and OUTPUTB are both low. Asserting the RESET signal low also causes the short circuit protection latch to be reset. The RESET signal is normally connected to the VALID signal from the TAS5000 TAS5000. reinitialization sequence Proper initial conditions for this device include asserting the RESET signal until the reset operation has completed (1 ms). Additionally, when using this device with the TAS5000 TAS5000 controller, this function can be accomplished by asserting the reset pin on the TAS5000 TAS5000 during the reset sequence (see Figure 3). audio application considerations power supply decoupling Power supply decoupling and layout optimization information should be obtained by following the detailed information in the application note SLAA117 SLAA117. optimal power transfer for H-bridge The TAS5100 TAS5100 is a power H-bridge that is designed to deliver 30 W/rms into loads of 4 to 8 . Rather than requiring the usual heatsink, the package is designed to deliver this wattage by careful layout as described in the application note SLAA117 SLAA117. Careful attention must be given to the value of the high-voltage power supply level for a given load resistance. See recommended operating conditions. www.ti.com 9 TAS5100 TAS5100 SLLS419B SLLS419B ­ MARCH 2001 ­ REVISED NOVEMBER 2001 audio application considerations (continued) reconstruction output filter An output reconstruction filter is required between the H-bridge outputs and the loudspeaker load. This second order low-pass filter passes the audio information to the loudspeaker, while filtering out the high frequency out-of-band information contained in the H-bridge output PWM pulses. The values of the L and C components selected are dependent on the loudspeaker load impedance. See application note SLAA117 SLAA117. fault indicator usage The TAS5100 TAS5100 is a self-protecting device that provides device fault reporting, including over-temperature protect, under-voltage lockout (low-regulator voltage), and short circuit protection. The short circuit protection protects against short circuits that may occur at the loudspeaker load when configured according to the application note SLAA117 SLAA117. The TAS5100 TAS5100 is not recommended for driving loads less than 4 , since the internal current limit protection might be activated. An under-voltage lockout signal occurs when an insufficient voltage level is present on the LDROUTA or LDROUTB pins. During this condition gate drive levels are not sufficient for driving the power MOSFETs. Normal operation is resumed when the minimum proper LDROUTA or LDROUTB level is obtained, and the low regulator voltage protect signal is de-asserted. See the control/sense circuitry section for error and warning conditions. A high temperature warning signal is asserted on pin ERR0 when the device temperature exceeds 110°C typical. If the internal device temperature exceeds 130°C typical, the over temperature protect signal is asserted and the TAS5100 TAS5100 is shut down. The device will re-enable once the temperature drops to 110°C typical. See the control/sense circuitry section for error and warning conditions. Detection of an illegal PWM input state or the loss of a clocking PWM input signal will cause an illegal PWM input state signal to be asserted on the ERR1and ERR0 pins and will set the SHUTDOWN pin to the low state. absolute maximum ratings over operating free-air temperature (unless otherwise noted) DC supply voltage range: DVDD to DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.3 V to 4.2 V PWM_AP, PWM_AM, PWM_BP, PWM_BM . . . . . . . . . . . . . . . . . ­0.3 V to DVDD + 0.3 V RESET, PWDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.3 V to DVDD + 0.3 V PVDDA1 to PVSS, PVDDB1 to PVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.3 V to 28 V PVDDA2 to PVSS, PVDDB2 to PVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.3 V to 27 V Output DMOS drain-to-source breakdown voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 V Continuous DMOS drain current, each output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A Continuous source-to-drain body diode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­40°C to 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 10 www.ti.com TAS5100 TAS5100 SLLS419B SLLS419B ­ MARCH 2001 ­ REVISED NOVEMBER 2001 recommended operating conditions (nominal output power = 30 W (RMS), TA = 25°C) thermal data PARAMETER MIN NOM MAX UNIT Shutdown junction temperature, TJ(SD) 130 °C Warning junction temperature, TJ(W) 110 °C Operating ambient temperature, TA 0 25 70 °C Thermal resistance junction-to-case, jc 2 oz. trace and copper pad with solder 0.32 °C/W Thermal resistance junction-to-ambient, ja 2 oz. trace and copper pad with solder 23.5 °C/W Thermal resistance junction-to-case, jc 2 oz. trace and copper pad without solder 0.32 °C/W Thermal resistance junction-to-ambient, ja 2 oz. trace and copper pad without solder 44.3 °C/W One of the most influential components on the thermal performance of a package is board design. In order to take full advantage of the heat dissipating abilities of the PowerPAD packages, a board must be used that acts similar to a heat sink and allows for the use of the exposed (and solderable), deep downset pad. See Appendix A of the PowerPAD Thermally Enhanced Package application note, TI literature number SLMA002 SLMA002 and the Thermal Design of the PowerPad PCB Layout section of the System Design Considerations for True Digital Audio Power Amplifiers application note, TI literature number SLAA117 SLAA117. RL = 4 to 8 PARAMETER Digital MIN MAX 3.3 3.6 16.5 22 16.5 22 24 PVDDA2 to PVSS} 10.5 16.5 PVDDB2 to PVSS} 10.5 UNIT 24 PVDDB2 to PVSS Regulator 3 PVDDA2 to PVSS Supply voltage y g DVDD to DVSS NOM V 16.5 V Connect LDROUTA to PVDDA2 and connect LDROUTB to PVDDB2. Under this condition H-Bridge forward on-state resistance is increased. This will increase internal power dissipation. Maximum output power may need to be reduced to meet thermal conditions. RL = 8 PARAMETER MAX 0 26 27 PVDDB1 to PVSS 0 26 27 MIN NOM MAX PVDDA1 to DVSS 0 23 24 PVDDB1 to PVSS 0 23 24 MIN NOM MAX PVDDA1 to DVSS Power NOM PVDDA1 to DVSS Supply voltage MIN 0 20 21 PVDDB1 to PVSS 0 20 21 UNIT V RL = 6 PARAMETER Supply voltage Power UNIT V RL = 4 PARAMETER Supply voltage Power www.ti.com UNIT V 11 TAS5100 TAS5100 SLLS419B SLLS419B ­ MARCH 2001 ­ REVISED NOVEMBER 2001 static digital specifications RESET, PWDN, PWM_AP, PWM_AM, PWM_BP, PWM_BM, TA = 25°C, DVDD = 3.3 V PARAMETERS MIN High-level input voltage, VIH MAX 2 Low-level input voltage, VIL UNIT V 0.8 Input leakage current V 10 µA ­10 ERR0, ERR1, SHUTDOWN, (open drain with internal pullup resistor) TA = 25°C, DVDD = 3.3 V) PARAMETERS MIN Internal pullup resistors from SHUTDOWN, ERR0, ERR1 to DVDD MAX 15 Low-level output voltage (IO = 4 mA), VOL UNIT k 0.4 V TAS5000/TAS5100 TAS5000/TAS5100 system performance measured at the speaker terminals See the TI Literature Number SLAA117 SLAA117 for TAS5000/TAS5100 TAS5000/TAS5100 system performance. electrical characteristics supply, TA = 25°C (Fswitching = 384 kHz, OUTPUTA and OUTPUTB not connected, DVDD = 3.3 V, PVDDA1 = 25 V, PVDDB1 = 25 V, PVDDA2 = 22 V, PVDDB2 = 22 V, 50% input duty cycle) PARAMETER TYP Operating DVDD PVDDA1 PVDDB1 Supply current PVDDA2 PVDDB2 MAX 2 PWDN = 0 Operating mA 500 6.3 PWDN = 0 6.5 PWDN = 0 13-k resistor from BIAS_A (pin 11) to DVSS and 13-k resistor from BIAS_B (pin 12) to DVSS. µA mA 25 Operating UNIT µA mA 250 µA H-Bridge transistors, PVDDA2 = PVDDB2 = 22 V, DVDD = 3.3 V, TA = 25°C (unless otherwise noted) PARAMETER Drain-to-source breakdown voltage TEST CONDITIONS Forward on-state resistance, low side drivers OUTPUTA and OUTPUTB to PVSS ID = 1 mA, PWDN = 0, Hi-Z state ISINK = 2.5 A, PWM_AP = PWM_BP = 0, See Notes 2, 3, and 4, PWM_AM = PWM_BM = 1 Forward on-state resistance, high side drivers PVDDA1 to OUTPUTA, PVDDB1 to OUTPUTB ISOURCE = 2.5 A, See Notes 2, 3, and 5, PWM_AP = PWM_BP = 1, PWM_AM = PWM_BM = 0 MIN TYP 28 MAX UNIT V 0.2 0.2 On-state resistance matching low-side drivers 98% On-state resistance matching high-side drivers 98% NOTES: 1. Test time should be < 1 ms to avoid temperature change. 2. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. 3. Connect PVDDA2 and PVDDB2 to 22-V power supply with respect to PVSS. LDROUTA, LDROUTB, BOOTSTRAPA, and BOOTSTRAPB pins open. 4. Connect PVDDA2 to 22-V power supply with respect to PVSS. LDROUTA, LDROUTB, BOOTSTRAPA and BOOTSTRAPB capacitors are connected respectively. Clock PWM inputs to allow bootstrap capacitors to charge. 93­99% modulation must be used on PWM_AP, PWM_AM, PWM_BP, and PWM_BM inputs to prevent the activity detector from shutting down the device during this measurement. Note that Fswitching = 384 kHz. 12 www.ti.com TAS5100 TAS5100 SLLS419B SLLS419B ­ MARCH 2001 ­ REVISED NOVEMBER 2001 electrical characteristics, voltage regulator, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS IO = 5 mA, See Note 6, Output voltage (LDROUTA, LDROUTB) PVDDA2 = PVDDB2 = 18 V to 27 V, DVDD = 3.3 V MIN TYP MAX 14.5 15.3 16 UNIT V NOTE 5: These voltage regulators are for internal gate drive circuits only and are not to be used under any circumstances to supply current to external circuity. THERMAL INFORMATION The thermally enhanced DAP package is based on the 32-pin HTSSOP, but includes a thermal pad (see Figure 4) to provide an effective thermal contact between the IC and the PWB. Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down TO-220 type packages have leads formed as gull wings to make them applicable for surface-mount applications. These packages, however, have two shortcomings: they do not address the very low profile requirements (