T66H0001A T66H0001A-Y 269-PIN Y1-Y240 PAD240 PAD241 PAD295

TE CH Preliminary T66H0001A T66H0001A 240 output LCD Segment/Common Driver IC DESCRIPTION The T66H0001A is a 240-output

tm TE CH Preliminary T66H0001A T66H0001A T66H0001A T66H0001A 240 output LCD Segment/Common Driver IC DESCRIPTION The T66H0001A T66H0001A is a 240-output segment/common driver IC suitable for driving large/medium scale dot matrix LCD panels, and is used in personal computers/work stations. Through the use of SST (Super Slim TCP) technology, it is ideal for substantially decreasing the size of the frame section of the LCD module. The T66H0001A T66H0001A is good both as a segment driver and a common driver, and it can create a low power consuming, high resolution LCD FEATURES - Number of LCD drive outputs : 240 Supply voltage for LCD drive : +10.0 to +42.0 V Supply voltage for logic system : +2.5 to +5.5 V - Low power consumption Low output impedance Package : 269-pin TCP (Tape Carrier Package) (Segment mode ) 1. Shift clock frequency - 20 MHz (MAX.) : VDD = +5.0 ± 0.5 V - 15 MHz (MAX.) : VDD = +3.0 to +4.5 V - 12 MHz (MAX.) : VDD = +2.5 to +3.0 V 2. Adopts a data bus system 3. 4-bit/8-bit parallel input modes are selectable with a mode (MD) pin 4. Automatic transfer function of an enable signal 5. Automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 240 bits of input data 6. Line latch circuits are reset when /DISPOFF low active Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Publication Date:Aug. 2001 -P 1 T66H0001Av0.B tm TE CH Preliminary T66H0001A T66H0001A (Common mode) - Shift clock frequency: 4 MHz (MAX.) - Built-in 240-bit bi-directional shift register (divisible into 120 bits x 2) - Available in single mode (240-bit shift register) or in dual mode (120-bit shift register x 2) a. Y1 à Y240 Single mode b. Y240 à Y1 Single mode c. Y1à Y120, Y121àY240 Dual mode d. Y240 àY121, Y120 à Y1 Dual mode The above 4 shift directions are pin selectable - Shift register circuits are reset when /DISPOFF low active Ordering Information Part No. Pkg. Description T66H0001A-Y T66H0001A-Y TCP Pitch 0.21mm, refer to Appendix T66H0001A T66H0001A COG Refer to Pads List PIN CONNECTIONS 269-PIN 269-PIN TCP Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Publication Date:Aug. 2001 -P 2 T66H0001Av0.B tm TE CH Preliminary T66H0001A T66H0001A PIN DESCRIPTION PIN NO. SYMBOL I/O DESCRIPTION 1 to 240 241, 269 242, 268 243, 267 244, 266 245 246 247, 259 Y1-Y240 Y1-Y240 V0L, V0R V12L,V12R V43L,V43R V5L,V5R VDD S/C EIO2, EIO1 O I I/O 248 to 254 255 DI0-DI6 DI7 I I 256 257 258 XCK /DISPOFF LP I I I 260 261 FR L/R I I 262 263, 264 265 MD NC VSS I I - LCD drive output Power supply for LCD drive Power supply for LCD drive Power supply for LCD drive Power supply for LCD drive Power supply for logic system (+2.5V to +5.5V) Segment mode/common mode selection Input/output for chip selection at segment mode/ Shift data input/output for shift register at common mode Display data input at segment mode Display data input at segment mode/Dual mode data input at common mode Clock input for taking display data at segment mode Control input for output of non-select level Latch pules input for display data at segment mode Shift clock input for shift register at common mode AC-converting signal input for LCD drive waveform Input for selecting the reading direction of display data at segment mode/Input for selecting the shift direction of shift register at common mode Mode selection input Not Connection Ground(0V) Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Publication Date:Aug. 2001 -P 3 T66H0001Av0.B tm TE CH Preliminary T66H0001A T66H0001A INPUT/OUTPUT CIRCUITS Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Publication Date:Aug. 2001 -P 4 T66H0001Av0.B tm TE CH Preliminary T66H0001A T66H0001A Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Publication Date:Aug. 2001 -P 5 T66H0001Av0.B tm TE CH Preliminary T66H0001A T66H0001A BLOCK DIAGRAM Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Publication Date:Aug. 2001 -P 6 T66H0001Av0.B tm TE CH Preliminary T66H0001A T66H0001A FUNCTIONAL OPERATIONS OF EACH BLOCK BLOCK Active Control SP Conversion & Data Control Data Latch Control Data Latch Line Latch/ Shift Register Level Shifter 4-Level driver Control Logic FUNCTION In case of segment mode, controls the selection or non-selection of the chip. Following and LP signal input, and after the chip selection signal is input, a selection signal is generated internally until 240 bits of data have been read in. Once data input has been completed, a selection signal for cascade connection is output, and the chip is non-selected. In case of common mode, controls the input/output data of bi-directional pins. In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel input mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel input mode in latch circuit, after that they are put on the internal data 8 bits at a time. In case of segment mode, selects the state of the data latch which reads in the data bus signals. The shift direction is controlled by the control logic. For every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit. In case of segment mode, latches the data on the data bus. The latch state of each LCD rive output pin is controlled by the control logic and the data latch control; 240 bits of data are read in 30 sets of 8 bits. In case of segment mode, all 240 bits which have been read into the data latch are simultaneously latched at the falling edge of the LP signal, and are output to the level shifter block. In case of common mode, shifts data from the data input pin at the falling edge of the LP signal. The logic voltage signal is level-shifted to the LCD drive voltage level, and in output to the driver block. Drives the LCD drive output pins from the line latch/shift register data, and selects one of 4 levels (V0, V12, V43, or V5) based on the S/C, FR and /DISPOFF signals. Controls the operation of each block. In case of segment mode, when an LP signal has been input, all blocks are rest and the control logic waits for the selection signal output from the active control block. Once the selection signal has been output, operation of the data latch and data transmission is controlled, 240 bits of data are read in, and the chip in non-selected. In case of common mode, controls the direction of data shift. Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Publication Date:Aug. 2001 -P 7 T66H0001Av0.B tm TE CH Preliminary T66H0001A T66H0001A FUNCTIONAL DESCRIPTION Pin Functions (Segment mode) SYMBOL VDD Vss V0L , V0R V12L , V12R V43L , V43R V5L , V5R DI7 , DI0 XCK LP L/R /DISPOFF FR FUNCTION Logic system power supply pin, connected to +2.5 to +5.5 V. Ground pin, connected to 0 V. Bias power supply pins for LCD drive voltage · Normally use the bias voltages set by a resistor divider. · Ensure that voltages are set such that Vss V5 < V43 < V12 < V0. · ViL and ViR ( i= 0 , 12 , 43 , 5) must connect to an external power supply , and supply regular voltage which is assigned by specification for each power pin. Input pins for display data · In 4-bit parallel input mode, input data into the 4 pins, DI3-DI0. Connect DI7-DI4 to Vss or VDD. · In 8-bit parallel input mode, input data into the 8 pins, DI7- DI0. · Refer to " RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Clock input pin for taking display data · Data is read at the falling edge of the clock pulse. Latch pulse input pin for display data · Data is latched at the falling edge of the clock pulse. Input pin for selecting the reading direction of display data · When set to Vss level "L", data is read sequentially from Y240 to Y1. · When set to VDD level "H", data is read sequentially from Y1 to Y240. · Refer to " RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Control input pin for output of non-select level · The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. · When set to Vss level "L", the LCD drive output pins (Y1-Y240 Y1-Y240) are set to level V5. · When set to "L" ,the contents of the line latch are reset , but the display data are read in the data latch regardless of the condition of /DISPOFF. When the /DISPOFF function is canceled, the driver outputs non-select level (V12 or V43), then outputs the contents of the data latch at the next falling edge of the LP. At that time, if /DISPOFF removal time does not correspond to what is shown in AC characteristics, it can not output the reading data correctly. · Table of truth values is shown in "TRUTH TABLE" in Functional Operations. AC signal input pin for LCD drive waveform · The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. · Normally it inputs a frame inversion signal. · The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal. · Table of truth values is shown in "TRUTH TABLE" in Functional Operations. Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Publication Date:Aug. 2001 -P 8 T66H0001Av0.B tm TE CH SYMBOL MD S/C EIO1 , EIO2 Y1-Y240 Y1-Y240 Preliminary T66H0001A T66H0001A FUNCTION Mode selection pin · When set to Vss level "L" , 8 bit parallel input mode is set. · When set to VDD level "H" , 4 bit parallel input mode is set. · Refer to " RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Segment mode/common mode selection pin · When set to VDD level "H" , segment mode is set. Input/output pins for chip selection · When L/R input is at Vss level "L" , EIO1 is set for output , and EIO2 is set for input. · When L/R input is at V level "H" , EIO1 is set for input , and EIO2 is set for DD output. · During output , set to "H" while LP· /XCK is "H" and after 240 bits of data have been read , set to "L" for one cycle (from falling edge to falling edge of XCK), after which it returns to "H". · During input , the chip is selected while EI is set to "L" after the LP signal is input. The chip is non-selected after 240 bits of data have been read. LCD drive output pins · Corresponding directly to each bit of the data latch , one level (V0 , V12 , V43 , or V5) is selected and output. · Table of truth values is shown in "TRUTH TABLE" in Functional Operations. Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Publication Date:Aug. 2001 -P 9 T66H0001Av0.B tm TE CH (Common mode) SYMBOL VDD Vss V0L , V0R V12L , V12R V43L , V43R V5L , V5R EIO1 EIO2 LP L/R /DISPOFF FR Preliminary T66H0001A T66H0001A FUNCTION Logic system power supply pin, connected to +2.5 to +5.5 V. Ground pin, connected to 0 V. Bias power supply pins for LCD drive voltage · Normally use the bias voltages set by a resistor divider. · Ensure that voltages are set such that Vss V5 < V43 < V12 < V0. · ViL and ViR ( i = 0 , 12 , 43 , 5) must connect to an external power supply , and supply regular voltage which is assigned by specification for each power pin. Shift data input/output pin for bi-directional shift register · Output pin when L/R is at Vss level "L" , input pin when L/R is at VDD level "H". · When L/R = H, EIO1 is used as input pin, it will be pulled down. · When L/R = L, EIO1 is used as output pin, it won't be pulled down. · Refer to " RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Shift data input/output pin for bi-directional shift register · Input pin when L/R is at Vss level "L" , output pin when L/R is at VDD level "H". · When L/R = L, EIO2 is used as input pin, it will be pulled down. · When L/R = H, EIO2 is used as output pin, it won't be pulled down. · Refer to " RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Latch pulse input pin for display data · Data is latched at the falling edge of the clock pulse. Input pin for selecting the shift direction of bi-directional shift register · Data is shifted from Y240 to Y1 when set to Vss level "L" , and data is shifted from Y1 to Y240 when set to VDD level "H". · Refer to " RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Control input pin for output of non-select level · The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. · When set to Vss level "L", the LCD drive output pins (Y1-Y240 Y1-Y240) are set to level V5. · When set to "L", the contents of the shift register are reset to not reading data. When the /DISPOFF function is canceled , the driver outputs non-select level (V12 or V43), and the shift data is read at the next falling edge of the LP. At that time, if DISPOFF removal time does not correspond to what is shown in AC characteristics, the shift data is not read correctly. · Table of truth values is shown in "TRUTH TABLE" in Functional Operations. AC signal input pin for LCD drive waveform · The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. · Normally it inputs a frame inversion signal. · The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal. · Table of truth values is shown in "TRUTH TABLE" in Functional Operations. Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Publication Date:Aug. 2001 -P 10 T66H0001Av0.B tm TE CH Preliminary T66H0001A T66H0001A SYMBOL MD DI7 S/C DI6-DI0 XCK Y1-Y240 Y1-Y240 FUNCTION Mode selection pin · When set to Vss level "L" , single operation is selected ; when set to V DD level "H" , dual mode operation is selected. · Refer to " RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Dual mode data input pin · According to the data shift direction of the data shift register , data can be input starting from the 121st bit. · When the chip is used in dual mode, DI7 will be pulled down. · When the chip is used in single mode, DI7 won't be pulled down. · Refer to " RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Segment mode/common mode selection pin · When set to Vss level "L, common mode is set. Not used · Connect DI6-DI0 to Vss or VDD, avoiding floating. Not used · XCK is pulled down in common mode, so connect to Vss or open. LCD drive output pins · Corresponding directly to each bit of the data latch , one level (V0 , V12 , V43 , or V5) is selected and output. · Table of truth values is shown in "TRUTH TABLE" in Functional Operations. Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Publication Date:Aug. 2001 -P 11 T66H0001Av0.B tm TE CH Preliminary T66H0001A T66H0001A Functional Operations TRUTH TABLE (Segment Mode) FR Latch Data /DISPOFF LCD Drive Output Voltage Level (Y1-Y240 Y1-Y240) L L H V43 L H H V5 H L H V12 H H H V0 X X L V5 R Latch Data /DISPOFF LCD Drive Output Voltage Level (Y1-Y240 Y1-Y240) L L H V43 L H H V0 H L H V12 H H H V5 X X L V5 (Common Mode) NOTES : · Vss