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DP11VN15A15P (3-1879322-6) TE Connectivity (3-1879322-6) DP11 VER 15P NDET 15P M7*5MM visit TE Connectivity
DP11SVN15A15P (6-1879323-5) TE Connectivity (6-1879323-5) DP11S VER 15P NDET 15P M7*5MM visit TE Connectivity
DP11SV2020B20K (2-1879321-8) TE Connectivity (2-1879321-8) DP11S VER 20P 20DET 20K M7*7MM visit TE Connectivity
DP11SV3015A15F (1879324-6) TE Connectivity (1879324-6) DP11S VER 15P 30DET 15F M7*5MM visit TE Connectivity
DP11VN15A30F (3-1879322-1) TE Connectivity (3-1879322-1) DP11 VER 15P NDET 30F M7*5MM visit TE Connectivity
DP11SVN15B20F (9-1879320-9) TE Connectivity (9-1879320-9) DP11S VER 15P NDET 20F M7*7MM visit TE Connectivity

T20 ver 2

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PD45128163

Abstract: uPD45128163G5-A75I-9JF-E µPD45128163G5-A75LI-9JF-E TA = -40 to + 85°C L EO t uc od Pr 2 Data Sheet E0729N10 (Ver. 1.0 , Sheet E0729N10 (Ver. 1.0) µPD45128163-I-E 2. Commands Mode register set command Fig.1 Mode , level, × = High or Low level (Don't care) Data Sheet E0729N10 (Ver. 1.0) t 2. Must be legal , (MIN.) ­2 +tDPL (MIN.) t uc Data Sheet E0729N10 (Ver. 1.0) 25 µPD45128163-I-E 11 , -bit synchronous dynamic random-access memory, organized as 2,097,152 × 16 × 4 (word × bit × bank). The
Elpida Memory
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PD45128163 uPD45128163G5-A75I-9JF-E uPD45128163G5-A75LI-9JF-E 128M- M01E0107

PD45128163

Abstract: uPD45128163G5-A75-9JF-E output buffers. 8 Data Sheet E0728N10 (Ver. 1.0) µPD45128163-E 2. Commands Mode register , L L Op-Code MRS ILLEGAL Data Sheet E0728N10 (Ver. 1.0) µPD45128163-E (2/3 , 2 ­1 +tDPL (MIN.) 3 ­2 +tDPL (MIN.) Data Sheet E0728N10 (Ver. 1.0) 25 , as 2,097,152 × 16 × 4 (word × bit × bank). The synchronous DRAM achieved high-speed data transfer , sequence (Sequential / Interleave) · Programmable burst length (1, 2, 4, 8 and full page) · Programmable
Elpida Memory
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uPD45128163G5-A75-9JF-E

PD45128163

Abstract: uPD45128163G5-A10LT-9JF -9JF TA = -20 to + 85°C 125 100 L EO t uc od Pr 2 Data Sheet E0348N10 (Ver. 1.0 , level, × = High or Low level (Don't care) Data Sheet E0348N10 (Ver. 1.0) t 2. Must be legal , Read Write ­1 +tDPL (MIN.) ­2 +tDPL (MIN.) t uc Data Sheet E0348N10 (Ver. 1.0 , dynamic random-access memory, organized as 2,097,152 × 16 × 4 (word × bit × bank). The synchronous , Programmable burst length (1, 2, 4, 8 and full page) · Programmable /CAS latency (2 and 3) · Ambient
Elpida Memory
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PD45128163-T uPD45128163G5-A10LT-9JF uPD45128163G5-A10T-9JF uPD45128163G5-A75LT-9JF uPD45128163G5-A75T-9JF uPD45128163G5-A80LT-9JF uPD45128163G5-A80T-9JF

uPD45128163G5-A75LT-9JF

Abstract: PD45128163 output buffers. 8 Data Sheet E0348N10 (Ver. 1.0) µPD45128163-T 2. Commands Mode register , , BA0(13), BA1(A12) Mode Register Set 20 Data Sheet E0348N10 (Ver. 1.0) /CAS latency R R 2 , 2 ­1 +tDPL (MIN.) 3 ­2 +tDPL (MIN.) Data Sheet E0348N10 (Ver. 1.0) 25 , dynamic random-access memory, organized as 2,097,152 × 16 × 4 (word × bit × bank). The synchronous DRAM , and UDQM · Programmable Wrap sequence (Sequential / Interleave) · Programmable burst length (1, 2, 4
Elpida Memory
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PD45128163

Abstract: uPD45128163G5-A10I-9JF output buffers. 8 Data Sheet E0346N10 (Ver. 1.0) µPD45128163-I 2. Commands Mode register , , BA0(13), BA1(A12) Mode Register Set 20 Data Sheet E0346N10 (Ver. 1.0) /CAS latency R R 2 , 2 ­1 +tDPL (MIN.) 3 ­2 +tDPL (MIN.) Data Sheet E0346N10 (Ver. 1.0) 25 , dynamic random-access memory, organized as 2,097,152 × 16 × 4 (word × bit × bank). The synchronous DRAM , and UDQM · Programmable Wrap sequence (Sequential / Interleave) · Programmable burst length (1, 2, 4
Elpida Memory
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uPD45128163G5-A10I-9JF uPD45128163G5-A10LI-9JF uPD45128163G5-A75I-9JF uPD45128163G5-A75LI-9JF uPD45128163G5-A80I-9JF uPD45128163G5-A80LI-9JF

PD45128163

Abstract: uPD45128163G5-A75I-9JF-E µPD45128163G5-A75LI-9JF-E 2 TA = -40 to + 85°C Data Sheet E0729N10 (Ver. 1.0) µPD45128163-I-E Part , output buffers. 8 Data Sheet E0729N10 (Ver. 1.0) µPD45128163-I-E 2. Commands Mode register , ­2 +tDPL (MIN.) Data Sheet E0729N10 (Ver. 1.0) 23 µPD45128163-I-E 10. Auto Precharge , dynamic random-access memory, organized as 2,097,152 × 16 × 4 (word × bit × bank). The synchronous DRAM , and UDQM · Programmable Wrap sequence (Sequential / Interleave) · Programmable burst length (1, 2, 4
Elpida Memory
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PD45128441

Abstract: uPD45128441G5-A10T-9JF PD45128841G5-A10LT-9JF 100 L t uc od Pr 2 Data Sheet E0347N10 (Ver. 1.0) PD45128441-T, 45128841 , buffers. Data Sheet E0347N10 (Ver. 1.0) t uc DQ0 - DQ8 9 PD45128441-T, 45128841-T 2 , Write ­1 +tDPL (MIN.) ­2 +tDPL (MIN.) t uc 24 Data Sheet E0347N10 (Ver. 1.0 , (Sequential / Interleave) · Programmable burst length (1, 2, 4, 8 and full page) · Programmable /CAS latency (2 and 3) · Ambient temperature (TA): -20 to + 85°C · Automatic precharge and controlled
Elpida Memory
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PD45128441 uPD45128441G5-A10T-9JF uPD45128841G5-A10T-9JF uPD45128841G5-A75T-9JF uPD45128841G5-A80T-9JF uPD45128441G5-A75T-9JF

PD45128441

Abstract: PD45128441G5-A10-9JF od Pr 2 Data Sheet E0343N10 (Ver. 1.0) PD45128441, 45128841 Part Number [ x4, x8 , E0343N10 (Ver. 1.0) t uc DQ0 - DQ8 9 PD45128441, 45128841 2. Commands Mode register set , E0343N10 (Ver. 1.0) t uc PRE/PALL REF/SELF 15 PD45128441, 45128841 (2/3) Current state , Read Write ­1 +tDPL (MIN.) ­2 +tDPL (MIN.) t uc 24 Data Sheet E0343N10 (Ver , /CAS latency = 2, 3 DQ od T0 CLK Burst length = X Data Sheet E0343N10 (Ver. 1.0
Elpida Memory
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PD45128441G5-A10-9JF PD45128441G5-A75-9JF uPD45128441G5-A75A-9JF PD45128441G5-A80-9JF PD45128841G5-A10-9JF PD45128841G5-A75-9JF

uPD45128841G5-A80LT-9JF

Abstract: PD45128441 µPD45128841G5-A10LT-9JF 100 2 Data Sheet E0347N10 (Ver. 1.0) Package Note 54-pin Plastic TSOP (II , ILLEGAL Data Sheet E0347N10 (Ver. 1.0) 3 15 µPD45128441-T, 45128841-T (2/3) Current state , ­1 +tDPL (MIN.) 3 26 Read ­2 +tDPL (MIN.) Data Sheet E0347N10 (Ver. 1.0 , length (1, 2, 4, 8 and full page) · Programmable /CAS latency (2 and 3) · Ambient temperature (TA): -20 , local Elpida Memory, Inc. for availability and additional information. Document No. E0347N10 (Ver. 1.0
Elpida Memory
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uPD45128841G5-A80LT-9JF uPD45128441G5-A80T-9JF

PD45128163

Abstract: uPD45128163G5-A75-9JF-E 2 Data Sheet E0728N10 (Ver. 1.0) PD45128163-E Part Number [ x16 ] PD45128163G5 - A75L , Sheet E0728N10 (Ver. 1.0) t uc 14 3 PD45128163-E (2/3) Current state /CS /RAS /CAS , Read Write ­1 +tDPL (MIN.) ­2 +tDPL (MIN.) t uc Data Sheet E0728N10 (Ver. 1.0 , , organized as 2,097,152 × 16 × 4 (word × bit × bank). The synchronous DRAM achieved high-speed data , and UDQM · Programmable Wrap sequence (Sequential / Interleave) · Programmable burst length (1, 2
Elpida Memory
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PD45128163

Abstract: PD45128163G5-A10-9JF µPD45128163G5-A80L-9JF 125 2 Data Sheet E0344N10 (Ver. 1.0) µPD45128163 Part Number [ x16 , output buffers. 8 Data Sheet E0344N10 (Ver. 1.0) µPD45128163 2. Commands Mode register set , L Op-Code MRS ILLEGAL Data Sheet E0344N10 (Ver. 1.0) µPD45128163 (2/3) Current , , BA0(13), BA1(A12) Mode Register Set 20 Data Sheet E0344N10 (Ver. 1.0) /CAS latency R R 2 , 2 ­1 +tDPL (MIN.) 3 ­2 +tDPL (MIN.) Data Sheet E0344N10 (Ver. 1.0) 23
Elpida Memory
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PD45128163G5-A10-9JF PD45128163G5-A75-9JF PD45128163G5-A75A-9JF PD45128163G5-A75L-9JF PD45128163G5-A80-9JF

PD45128163

Abstract: PD45128163G5-A10-9JF -9JF 133 PD45128163G5-A80L-9JF 125 L EO t uc od Pr 2 Data Sheet E0344N10 (Ver. 1.0 , Read Write ­1 +tDPL (MIN.) ­2 +tDPL (MIN.) t uc Data Sheet E0344N10 (Ver. 1.0 , , organized as 2,097,152 × 16 × 4 (word × bit × bank). The synchronous DRAM achieved high-speed data , and UDQM · Programmable Wrap sequence (Sequential / Interleave) · Programmable burst length (1, 2, 4, 8 and full page) · Programmable /CAS latency (2 and 3) · Automatic precharge and controlled
Elpida Memory
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uPD45128163G5-A75A-9JF uPD45128163G5-A75L-9JF uPD45128163G5-A80L-9JF

PD45128441

Abstract: uPD45128441G5-A10I-9JF µPD45128841G5-A10LI-9JF 100 2 Data Sheet E0345N10 (Ver. 1.0) Package Note 54-pin Plastic TSOP (II , ILLEGAL Data Sheet E0345N10 (Ver. 1.0) 3 15 µPD45128441-I, 45128841-I (2/3) Current state , ­1 +tDPL (MIN.) 3 26 Read ­2 +tDPL (MIN.) Data Sheet E0345N10 (Ver. 1.0 , length (1, 2, 4, 8 and full page) · Programmable /CAS latency (2 and 3) · Ambient temperature (TA): -40 , local Elpida Memory, Inc. for availability and additional information. Document No. E0345N10 (Ver. 1.0
Elpida Memory
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uPD45128441G5-A10I-9JF uPD45128441G5-A75I-9JF uPD45128441G5-A80I-9JF uPD45128841G5-A10I-9JF uPD45128841G5-A75I-9JF uPD45128841G5-A80I-9JF

PD45128441

Abstract: PD45128441G5-A10-9JF -9JF 125 4M × 8 × 4 µPD45128841G5-A80L-9JF 2 133 133 125 Data Sheet E0343N10 (Ver. 1.0 , ­1 +tDPL (MIN.) 3 24 Read ­2 +tDPL (MIN.) Data Sheet E0343N10 (Ver. 1.0 , (1, 2, 4, 8 and full page) · Programmable /CAS latency (2 and 3) · Automatic precharge and , and additional information. Document No. E0343N10 (Ver. 1.0) Date Published February 2003 (K) Japan , Minimum cycle time 4 : x4 8 : x8 75A 75 80 10 : 7.5 ns (133 MHz @CL=2) : 7.5 ns (133 MHz
Elpida Memory
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uPD45128841G5-A75A-9JF PD45128841G5-A80-9JF

PD45128163

Abstract: uPD45128163G5-A10I-9JF L EO t uc od Pr 2 Data Sheet E0346N10 (Ver. 1.0) µPD45128163-I Part Number , Sheet E0346N10 (Ver. 1.0) µPD45128163-I 2. Commands Mode register set command Fig.1 Mode , level, × = High or Low level (Don't care) Data Sheet E0346N10 (Ver. 1.0) t 2. Must be legal , (MIN.) ­2 +tDPL (MIN.) t uc Data Sheet E0346N10 (Ver. 1.0) 25 µPD45128163-I 11 , -bit synchronous dynamic random-access memory, organized as 2,097,152 × 16 × 4 (word × bit × bank). The
Elpida Memory
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PD45128441

Abstract: uPD45128441G5-A10I-9JF PD45128841G5-A10LI-9JF 100 L t uc od Pr 2 Data Sheet E0345N10 (Ver. 1.0) PD45128441-I, 45128841 , buffers. Data Sheet E0345N10 (Ver. 1.0) t uc DQ0 - DQ8 9 PD45128441-I, 45128841-I 2 , Write ­1 +tDPL (MIN.) ­2 +tDPL (MIN.) t uc 24 Data Sheet E0345N10 (Ver. 1.0 , (Sequential / Interleave) · Programmable burst length (1, 2, 4, 8 and full page) · Programmable /CAS latency (2 and 3) · Ambient temperature (TA): -40 to + 85°C · Automatic precharge and controlled
Elpida Memory
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Abstract: EDL1216CASA-10 8M × 16 4 100 3 54-ball FBGA Data Sheet E0195E20 (Ver. 2.0) 2 , VDDQ + 1.5V (pulse width 5ns). 2. VIL (min.) = ­1.5V (pulse width 5ns). Data Sheet E0195E20 (Ver , 2 -1 +tDPL(min.) 3 -2 +tDPL(min.) Data Sheet E0195E20 (Ver. 2.0) 25 , Q2 D1 Hi-Z is necessary Read to Write Command Interval 2 Data Sheet E0195E20 (Ver. 2.0 , Configurations The EDL1216CA is a 128M bits Mobile RAM organized as 2,097,152 words × 16 bits × 4 banks. The Elpida Memory
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EDL1216CASA
Abstract: : VDD = 2.5V, VDDQ = 2.5V, LVCMOS Die Rev. Data Sheet E0255E20 (Ver. 2.0) 2 EDL1216BASA , 1.5V (pulse width 5ns). 2. VIL (min.) = ­1.5V (pulse width 5ns). Data Sheet E0255E20 (Ver. 2.0 , Interval 2 Data Sheet E0255E20 (Ver. 2.0) 29 EDL1216BASA Burst Termination There are two , Configurations The EDL1216BA is a 128M bits Mobile RAM organized as 2,097,152 words × 16 bits × 4 banks. The , packaged in 54-ball FBGA (µBGA). /xxx indicates active low signal. 54-ball FBGA ( BGA) 1 2 3 Elpida Memory
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EDL6416BABH-75-E

Abstract: edl6416 Rev. Preliminary Data Sheet E0421E30 (Ver. 3.0) 2 EDL6416BABH CONTENTS Description , 2. VIL (min.) = ­1.0V (pulse width 5ns). Preliminary Data Sheet E0421E30 (Ver. 3.0) 4 , (Ver. 3.0) 5 EDL6416BABH DC Characteristics 2 (TA = ­25 to +85°C, VDD = 2.5V ± 0.2V, VDDQ = , Sheet E0421E30 (Ver. 3.0) WT = 1 1 2 4 8 R R R R A0 Partial Array Self Refresh , 2 -1 +tDPL(min.) 3 -2 +tDPL(min.) Preliminary Data Sheet E0421E30 (Ver. 3.0) 24
Elpida Memory
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EDL6416BABH-75-E edl6416
Abstract: , VDDQ = 1.8V, LVCMOS Preliminary Data Sheet E0490E20 (Ver. 2.0) 2 EDL5132CBMA CONTENTS , (pulse width 5ns) 2. VIL (min.) = ­1.0V (pulse width 5ns) Preliminary Data Sheet E0490E20 (Ver. 2.0 , . Preliminary Data Sheet E0490E20 (Ver. 2.0) 5 EDL5132CBMA DC Characteristics 2 (TA = ­25 to +85°C, VDD , ACT PRE/PALL REF MRS/EMRS 2 2 2 2 2 2 2 2 2 2, 8 2 Preliminary Data Sheet E0490E20 (Ver , . /CAS latency 2 3 Read -1 -2 Write +tDPL(min.) +tDPL(min.) Preliminary Data Sheet E0490E20 (Ver. 2.0 Elpida Memory
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