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Part Manufacturer Description Datasheet BUY
SN74163N Texas Instruments Synchronous 4-bit binary counters 16-PDIP 0 to 70 visit Texas Instruments
SN74163N3 Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16 visit Texas Instruments
SN74163N-00 Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16, CERAMIC, DIP-16 visit Texas Instruments
SN74163J-00 Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERAMIC, DIP-16 visit Texas Instruments
SN74163J Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERAMIC, DIP-16 visit Texas Instruments
SN74163N-10 Texas Instruments TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16 visit Texas Instruments

Synchronous 74163

Catalog Datasheet MFG & Type PDF Document Tags

74163 four bit binary counter

Abstract: LS162A S ig n e tic s 74160, 74161, 74163, LS160A, LS161A, LS162A, LS163A Counters Logic Products FEATURES · Synchronous counting and loading · Two Count Enable Inputs for nbit cascading · Positive edge-triggered clock · Asynchronous reset ('160, '161) · Synchronous reset ('162, '163) · Hysteresis on Clock , , 74LS162A) and 4-bit (74161, 74LS161A, 74163, 74LS163A) counters feature an internal carry lookahead and can be used for high-speed counting. Synchronous operation is pro vided by having all flip-flops clocked
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74163 four bit binary counter 74163 pin configuration 74160 function table 162 bcd pin diagram of 74163 counter diagram 74161 74LS160A N74160N N74LS160AN N74161N N74LS161AN N74LS162AN

pin diagram of 74160

Abstract: 74160 function table Signetics 74160, 74161, 74163, LS160A, LS161A, LS162A, LS163A Counters Logic Products FEATURES â'¢ Synchronous counting and loading â'¢ Two Count Enable inputs for n-bit cascading â'¢ Positive edge-triggered clock â'¢ Asynchronous reset ('160, '161) â'¢ Synchronous reset ('162, '163) â'¢ Hysteresis on Clock input (LS only) DESCRIPTION Synchronous presettable decade (74160, 74LS160A, 74LS162A) and 4-bit (74161, 74LS161 A, 74163, 74LS163A) counters feature an internal carry look-ahead and can be
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pin diagram of 74160 74160 pin 74ls161 counter pin configuration 74160 logic diagram of 74160 logic diagram 74160 N74163N N74LS163AN N74LS161

74160 pin description

Abstract: 74160 Signetics Logic Products FEATURES â'¢ Synchronous counting and loading â'¢ Two Count Enable , '¢ Synchronous reset ('162, '163) â'¢ Hysteresis on Clock input (LS only) DESCRIPTION Synchronous presettable decade (74160, 74LS160A, 74LS162A) and 4-bit (74161, 74LS161A, 74163, 74LS163A) counters feature an internal carry look-ahead and can be used for high-speed counting. Synchronous operation is provided by , . PIN CONFIGURATION 74160, 74161, 74163, LS160A, LS161A, LS 162A, LS163A Counters '160, '162 BCD
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74160 pin description 74161 74163 LS161 Ls 74160 Synchronous 74160 N74LS161AD

ic 74160

Abstract: IC 74160 decade counter diagram Signetics 74160, 74161, 74163, LS160A, LS161A, LS162A, LS163A Counters Logic Products '160 , Synchronous counting and loading · Two Count Enable inputs for nbit cascading · Positive edge-triggered clock · Asynchronous reset ('160, '161) · Synchronous reset ('162, ' 163) · Hysteresis on Clock input (LS , -bit (74161, 74LS161 A, 74163, 74LS163A) counters feature an internal carry look ahead and can be used for high-speed counting. Synchronous operation is pro vided by having all flip-flops clocked simultaneously on
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ic 74160 IC 74160 decade counter diagram ic 74163 IC 74161 pin diagram of ic 74163 diagram of IC 74160 54LS/74LS S4LS/74LS F08270S

IC 74161

Abstract: lm 74161 S ignetics Logic Products Counters FEATURES · Synchronous counting and loading · Two Count , Synchronous reset ('162, '163) · Hysteresis on Clock input (LS only) DESCRIPTION S y n c h ro n o u s p re s e tta b le d e ca de (74160, 74LS160A, 74LS162A) and 4-bit (74161, 74LS161A, 74163, 74LS163A) counters feature an internal carry look ahead and can be used for high-speed counting. Synchronous , (CEP, CET) inputs. Plastic SO NOTE: 74160, 74161, 74163, LS160A, LS161A, LS162A, LS163A '160
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lm 74161 74161/74160 function table IC 74160 for decade counter of 74160 ic LM 74160 N74-LS161AN
Abstract: 1 74160, 74161, 74163, LS160A, LS161A, LS162A, LS163A S ig n e lic s Counters Logic Products FEATURES â'¢ Synchronous counting and loading â'¢ Two Count Enable inputs for nbit cascading â'¢ Positive edge-triggered clock â'¢ Asynchronous reset ('160, â'™161) â'¢ Synchronous reset , Counter TYPE DELAY '161, '163 4-Bit Binary Counter Product 74160 - 74163 Specification 32MHz , s e tta b le d e c a d e (74160, 74LS160A, 74LS162A) and 4-bit (74161, 74LS161A, 74163, 74LS163A -
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N74S163AD

74LS160

Abstract: Synchronous 74163 1 2 3 4 Synchronous \/ Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Up/D own U p/D own Up/Down U p/D own Up/Down Up/Down U p/D own U p/D own , /74163 54LS/74LS163 54LS/74LS168 54LS/74LS169 54/74192 54LS/74LS192 54/74193 54LS/74LS193 54/74190 , 14 15 16 17 18 19 20 A A A A A A A A _r _r _r s `A = asynchronous, S = synchronous 9-16 , , 54LS/74LS162, 54/74163, 54LS/74LS163 D129 54/74192, 54LS/74LS192, 54/74193, 54LS/74LS193 i 7
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93S16 93S05 74LS160 Synchronous 74163 74192 74LS190 pins 74LS193 74LS191 pins 93L16 54LS/74LS160 54LS/74LS161 74LS190 74LS191

74LS190 pins

Abstract: 74LS192 PIN diagram Presettable s s 45 15 95 D128 4L,7B,9B 9 Synchronous 54/74163 16 Presettable s s 32 17 315 D128 4L,7B,9B 10 , /74LS162, 54/74163, 54LS/74LS163 9 3 4 5 6 Alili 7-10-2- PE Po Pi P2 P3 CEP CET TC CP sn Oo Qi 02 , Package(s) 1 Synchronous 93L16 16 Presettable S J" 23 26 85 D127 4L,7B,9B 2 Synchronous 93S16 16 Presettable S _r 90 9.0 410 D127 4L,7B,9B 3 Synchronous 54/74160 10 Presettable S s 32 17 315 D127 4L,7B,9B 4 Synchronous 54LS/74L.S160 10 Presettable s s 45 15 95 D127 4L,7B,9B 5 Synchronous 54/74161 16
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74LS192 PIN diagram 74LS183 TTL 74ls163 74LS192 pins 74LS162 74LS192 54/7490A 54LS/74LS90 74LS92 S4/74293 54LS/74LS293 S4/7493A

counter 74162

Abstract: 74162 â'" 128 â'" 74162 Synchronous Presettable BCD Counter with Clear rippie outputs carry ,. enable vcc output °a ub qc qp t loao I I I I I I , 74163 3» X X X X H HLLH A - SIGNE TI D HF DF D DF DF DF JRS D D DF - 130- 74162, 74163 Synchronous Presettable Binary Counter with Clear
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counter 74162 74162 74162 LOAD BCD counter 0-0106462

NS486SXF

Abstract: EPM7032LC44-6 , 13NOV96 Release of Rev. D PCB -Remove UART frequency divider INCLUDE "rdy"; INCLUDE "74163"; - , CS16/ Synchronous sysclk for PC/104 Flash chip select out Lower 1 meg memory strobes PC/104 16 , Declaration evb_rdy : clk_ctr : NODE; NODE; NODE; NODE; NODE; rdy; 74163; - Register , / smemr/ smemw/ sysclk uarten/ w10 w11 * FILE HIERARCHY * |rdy:evb_rdy| |74163:clk_ctr| |74163:clk_ctr|p74163:sub| * Logic for device 'evb' compiled without errors. Device: EPM7032LC44
National Semiconductor
Original
NS486SXF PC104 EPM7032LC44-6 not gate Altera PCMCIA 74163 8 bit COUNTER 07NOV96 PC104SEL/ PIN001 PIN002

74160 pin layout

Abstract: am7416 .-'74162 and Am54 74163 have a synchronous clear. A LOW level a! the clear input sets the Q outputs LOW after , . Am64rt4160 Synchronous D*cade Countar LOAD1-®â'"- LOGIC DIAGRAMS Am54/74163 Synchronous Binary Counter , shown for the Am54/74163 binary counters. Am54/74161 Synchronous »nary counters a»e *.m. clear is , /74163 the clear is synchronous. A LOW on the clear sets all four Nip-flops LOW after the next , '¢ Am54/74163^^5 Synchronous Four-Bit Counters r4 % pKtwa Characteristics Wit synchronous counters
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74160 pin layout am7416 IC 74160 DATA SHEET AM-7416 pins and their function in ic 74163 7416l 21850E/0-I

74162 LOAD

Abstract: counter 74162 129 74163 Synchronous Presettable Binary Counter with Clear RIPPLE outputs CARRY ,-'-. enable VCC OUTPUT °a ub QC °D t load 1 1 1 1 1 1 r RIPPLE Oa 0B Qc Oq f NABl. 6 CARRY T OUTPUT CLIAR 1040 â if a . c UENT£ ! 1 1 1 1 1 m M) I» art OUT N LS ALS ALSK F S AS AC ACT HC HCU HCT BC BCT mi m n j n , , 74163 Synchronous Presettable Binary Counter with Clear
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74LS191

Abstract: D129 Synchronous 54/74163 16 Presettable s s 32 17 315 D128 4L,7B,9B 10 Synchronous 54LS/74LS163 16 Presettable s , ) Power Dissipation mW (Typ) Logic/Connection Diagram Package(s) 1 Synchronous 93L16 16 Presettable S J" 23 26 85 D127 4L,7B,9B 2 Synchronous 93S16 16 Presettable S _r 90 9.0 410 D127 4L,7B,9B 3 Synchronous 54/74160 10 Presettable S s 32 17 315 D127 4L,7B,9B 4 Synchronous 54LS/74L.S160 10 Presettable s s 45 15 95 D127 4L,7B,9B 5 Synchronous 54/74161 16 Presettable s s 32 17 315 D127 4L,7B,9B 6
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D129 TTL 93S16 74LS78 74190 74191, 74193 presettable digital clock 54LS/74LS541 54LS/74LS78 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256

74LS163D

Abstract: 74LS161 161 â'¢ 163 54/74161 â'¢MLS/74LS161 ^6^4/74163 â'¢ ^54LS/74LS1 63 " 7 } ^ SYNCHRONOUS PRESETTABLE BINARY COUNTERS DESCRIPTION â'"The '161 and '163 are high speed synchronous moduio-16 binary , Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage , outputs LOW. The '163 has a Synchronous Reset input that overrides counting and parallel loading and , â'¢ SYNCHRONOUS COUNTING AND LOADING â'¢ HIGH SPEED SYNCHRONOUS EXPANSION â'¢ LS VERSIONS FULLY
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74163PC 74LS163PC 74163DC 74LS163DC 74163FC 74LS163FC 74LS163D 74LS163 pinout LS16-1

74LS163 pinout

Abstract: 74161 161 â'¢ 163 »/OiT/ 54/74161 »MkSmLSiei 5?/0S?^4/74163 *^LS/74LS163 SYNCHRONOUS PRESETTABLE BINARY COUNTERS DESCRIPTION â'"The '161 and '163 are high speed synchronous modulo-16 binary counters , Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters , LOW. The '163 has a Synchronous Reset input that overrides counting and parallel loading and allows , 9316 data sheet. â'¢ SYNCHRONOUS COUNTING AND LOADING â'¢ HIGH SPEED SYNCHRONOUS EXPANSION â'¢ LS
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54LS161 74LS161 data sheet 74LS161DC 4-221 74161 data sheet 74ls161 counter 54163DM 54LS163DM 54163FM 54LS163FM LS163

74LS190 PIN diagram

Abstract: presettable digital clock 95 D128 4L,7B,9B 9 Synchronous 54/74163 16 Presettable s s 32 17 315 D128 4L,7B,9B 10 Synchronous , Output Delay-ns (Typ) Power Dissipation mW (Typ) Logic/Connection Diagram Package(s) 1 Synchronous 93L16 16 Presettable S J" 23 26 85 D127 4L,7B,9B 2 Synchronous 93S16 16 Presettable S _r 90 9.0 410 D127 4L,7B,9B 3 Synchronous 54/74160 10 Presettable S s 32 17 315 D127 4L,7B,9B 4 Synchronous 54LS/74L.S160 10 Presettable s s 45 15 95 D127 4L,7B,9B 5 Synchronous 54/74161 16 Presettable s s 32 17 315 D127
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74LS190 PIN diagram ttl 74191 Fairchild 74190 74155 74191 D130 93L21 54/74S139 54LS/74LS139 54LS/74LS155 54LS/74LS156 93L01

74257

Abstract: 74160 74692 BCD Synchronous Counters â'" 299 â'" jsu^nrjyu^fforj? us; .v;. xmiiirtininiioiimi^f ClIAR CLOCK N O 74160 ~74163(" 74175, 74257£*l^"£*b ¿ttzf^-r 74690 BCD 4mm r 74691 16 m 4mw?>i -r 74692 BCD MM?liT 74693 16 ¡ft HJBI CLEAR -t> CLOCK m Mi IN mil OUT » LS ALS ALSK F S AS AC ACT HC HCU HCT BC BCT »fit faax n 20 MHz tw n 25 ns tsu n 0 30 t IIS tsu B n CCIR 40 t ns tsu a n RCLR 20! ns thold n 0
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74257 74690 74691 counter 74692 ax8aa bcd 74160

asynchronous 4bit up down counter using jk flip flop

Abstract: counter 74168 Counters 15 4CU Synchronous 4-bit binary counter with synchronous reset 45 74163 16 4CU1 Synchronous 4-bit binary counter with synchronous reset (without data load) 38 17 4CD Synchronous 4-bit binary up/down counter with down/up mode control 66 74191 18 4CD1 Synchronous 4-bit binary up/down counter with , WITH SYNCHRONOUS CLEAR 74163 65 â'¢ 21 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER 74164 73 22 , SYNCHRONOUS 4-BIT BINARY COUNTER WITH SYNCHRONOUS CLEAR (WITHOUT DATA LOAD) (74163) 50 * 83
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asynchronous 4bit up down counter using jk flip flop counter 74168 Multiplexer 74152 3-8 decoder 74138 synchronous counter using 4 flip flip 74183 alu MSM70V000 MSM-71V000 MSM72V000 MSM73V000 MSM74V000 MSM79V000

74139 for bcd to excess 3 code

Abstract: design a bcd counter using jk flip flop flip flops with reset ! 23 Cou nters 15 4CU ; Synchronous 4-bit binary counter with , ^ synchronous reset 74163 16 4CU1 Synchronous 4-bit binary counter with ^g synchronous reset (without data load) 17 ; 4CD Synchronous 4-bit binary up/down counter with down/up mode control 66 74191 , WITH SYNCHRONOUS CLEAR 74163 65 -* 21 < 0164 > 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER 74164 73 22 , SYNCHRONOUS CLEAR (WITHOUT DATA LOAD) (74163) 50 * 83 OCTAL D-TYPE LATCHES WITH 3-STATE 74373 77 84
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74139 for bcd to excess 3 code design a bcd counter using jk flip flop ttl 74118 priority encoder 74148 alu 74381 jk flip flop to d flip flop conversion MSM70H000 MSM-71H000 MSM72H000 MSM73H000 MSM74H000 MSM79H000

CMOS 4000B series 4161

Abstract: timing diagram of 74160 4160B R&E INTERNATIONAL, INC. CMOS SYNCHRONOUS 4-BIT COUNTERS FEATURES ♦ BCD Decade (4160B , ™¦ Clear Input - Asynchronous ( 4160B, 4161B) or Synchronous (4162B, 4163B) ♦ Static Operation - DC to 5MHz Q 10Vdc DESCRIPTION The 4160B - 4163B are Synchronous Programmable Counters constructed , structure. These counters are functionally equivalent to the 74160 - 74163 TTL counters. Two are synchronous programmable decade counters with asynchronous and synchronous Clear inputs respectively ( 4160
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CMOS 4000B series 4161 timing diagram of 74160 74160 4-bit Decade Counter Asynchronous reset 4000B BCD Decade logic diagram 74160 74160 counter 4160B/4161B
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