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Slot 2 bus termination card design guidelines

Catalog Datasheet MFG & Type PDF Document Tags

intel 915 MOTHERBOARD pcb CIRCUIT diagram

Abstract: B1370 6.4.6 Combination PCI-X 133 MHz Slot and Embedded Topology 2 . 58 6.4.7 , . 75 PCI Express Layout Guidelines for an 80332 on a Motherboard-Adapter Card Topology . 78 Clock , . 62 PCI-X 100 MHz Slot and Embedded Topology 2 . , /Command/Control Routing Guidelines . 132 DDR Signal Termination , .141 9.1.5 Layout Guidelines for the Peripheral Bus
Intel
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b1370

Abstract: PCI x1 express PCB dimensions artwork 6.4.6 Combination PCI-X 133 MHz Slot and Embedded Topology 2 .58 6.4.7 , /Command/Control Routing Guidelines . 134 DDR Signal Termination , . 75 PCI Express Layout Guidelines for an 80333 on a Motherboard-Adapter Card Topology . 78 Clock , . 83 8.1 8.2 8.3 9 PCI-X 100 MHz Slot and Embedded Topology 2 , .143 9.1.5 Layout Guidelines for the Peripheral Bus
Intel
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B1370

Abstract: . Copyright© Intel Corporation 2002 2 Order Number: 273824-001 Intel® 80332 I/O Processor Design , 6.4.6 Combination PCI-X 133 MHz Slot and Embedded Topology 2 .56 6.4.7 , /Command/Control Routing Guidelines . 130 DDR Signal Termination , : . 73 PCI Express Layout Guidelines for an 80332 on a Motherboard-Adapter Card Topology . 76 Clock , . 60 PCI-X 100 MHz Slot and Embedded Topology 2 .
Intel
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rpack

Abstract: rpack8 E Slot 1 Bus Termination Card Design Guidelines August 1997 Order Number: 243409-002 8 , a 2-way multiprocessor system. Note that there are other ways to implement a bus termination card , termination circuitry for the microprocessor's GTL+ bus. In a 2-way multiprocessor system each end of the bus , processors installed. This document describes design considerations for a termination card to occupy the , 24340901.DOC INTEL CONFIDENTIAL (until publication date) 2. TERMINATION CARD REFERENCE SCHEMATICS
Intel
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rpack7

Abstract: rpack E Slot 1 Bus Termination Card Design Guidelines May 1997 Order Number: 243409-001 6/13 , a 2-way multiprocessor system. Note that there are other ways to implement a bus termination card , card edge must mate properly with the Slot 1 connector (see Slot 1 Connector Design Guidelines). For , termination circuitry for the microprocessor's GTL+ bus. In a 2-way multiprocessor system each end of the bus , processors installed. This document describes design considerations for a termination card to occupy the
Intel
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rpack8 56

Abstract: rpack ® SC242 Termination Card Design Guidelines November, 1999 Order Number: 245336-001 , owners SC242 Termination Card Design Guidelines TABLE OF CONTENTS 1. INTRODUCTION , . 12 3 SC242 Termination Card Design Guidelines 1. INTRODUCTION The Pentium® II and Pentium , distribution plane (or trace) to the termination resistors. 4 SC242 Termination Card Design Guidelines , Connector (A1-73, B1-73) 5 SC242 Termination Card Design Guidelines RESET_N BREQ_N[1] REQ_N[0
Intel
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rpack8 56 rpack rpack 10 k 9 rpack-8 rpack7 rpack 4 1 66/100/133MH

pentium II SLOT PINOUT

Abstract: 82450NX plane. 2 7 Intel Pentium ® II XeonTM Processor Bus Terminator Design Guidelines · , Processor Bus Terminator Design Guidelines Appendix: Indicating Presence of Processor or Terminator Card , Intel® Pentium® II XeonTM Processor Bus Terminator Design Guidelines Release Date: July 1998 Order Number: 243774-001 Intel Pentium ® II XeonTM Processor Bus Terminator Design Guidelines , Bus Terminator Design Guidelines CONTENTS 1.0 OVERVIEW
Intel
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pentium II SLOT PINOUT 82450NX 150 ohms resistor xeon intel microprocessor pin diagram Pentium II Xeon 8080 intel microprocessor pin diagram

82450NX

Abstract: B137 plane. 2 7 Intel Pentium ® II XeonTM Processor Bus Terminator Design Guidelines · , Processor Bus Terminator Design Guidelines Appendix: Indicating Presence of Processor or Terminator Card , Intel® Pentium® II XeonTM Processor Bus Terminator Design Guidelines Release Date: July 1998 Order Number: 243774-001 Intel Pentium ® II XeonTM Processor Bus Terminator Design Guidelines , Bus Terminator Design Guidelines CONTENTS 1.0 OVERVIEW
Intel
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B137 440GX 450NX A111 A112 A113

intel 965 motherboard circuit diagram

Abstract: CK408B ® M Processor and the Intel® Pentium® M Processor on the 90 nm process with 2-MB L2 cache Design , others. Copyright © 2007, Intel Corporation. All rights reserved. 2 Design Guide Intel , . 55 System Bus Routing Guidelines . 57 5.1 Intel® Pentium® M Processor System Bus Design Recommendations , . 57 5.1.2 Processor System Bus Termination
Intel
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E7501 P64H2 intel 965 motherboard circuit diagram CK408B 8279 intel microcontroller architecture 82555 intel 965 motherboard schematic diagram HP 3070 calibrate CK-408B

resistor 150 ohm

Abstract: 150 ohms resistor fingers 1.5V ± 3% when bus is idle Maximum 3.2 Card Layout Guidelines The design should follow AGTL , III XeonTM Processor Bus Terminator Design Guidelines Table 2. Interface Connector Pin-out Signal , ® Intel® Pentium® III XeonTM Processor Bus Terminator Design Guidelines November, 1999 , Terminator Design Guidelines 1. Overview The Intel Pentium® III XeonTM processor includes termination , locations have processors installed. This document describes design considerations for a termination card
Intel
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resistor 150 ohm transistor A144 transistor B123 a105 transistor A135 A101

fr-4 dielectric constant 4.4

Abstract: 535043-4 limitations can affect the bus design. A 20-slot BLVDS backplane SPICE model including the backplane half of , card in slot 2 is the driver. Both the single-ended and differential receiver input waveforms are , the card in slot 7 drives the bus. The singleended waveforms at the top of the plot are at the , with the card in slot 1 driving the bus. Voltage (V) NESA Technical White Paper Time (s , the card in slot 5 driving the bus. The differential waveforms shown are at the inputs to the
National Semiconductor
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fr-4 dielectric constant 4.4 535043-4 FR4 microstrip stub DS92LV010 SYSTEMS ASSOCIATES

HP G61 Motherboard schematic

Abstract: intel g41 MOTHERBOARD pcb CIRCUIT diagram -1 F.2 Intel 440LX Single Ended Termination Design Guidelines . F-1 APPENDIX , PLATFORM REFERENCE DESIGN DP-4 This page shows the Slot 1 Connector (part 2). This page shows the , . 1-2 CHAPTER 2 DESIGN FEATURES 2. Design Features , . 5-9 5.4.1 Host Bus Layout and Routing Guidelines . 5-9 , 440LX Memory Subsystem Layout and Routing Guidelines . 5-13 5.4.4 PCI Bus Routing
Intel
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82371AB HP G61 Motherboard schematic intel g41 MOTHERBOARD pcb CIRCUIT diagram g41 MOTHERBOARD CIRCUIT diagram gigabyte g41 MOTHERBOARD pcb CIRCUIT diagram PC MOTHERBOARD GIGABYTE CIRCUIT diagram SCHEMATIC gigabyte g41 mt SCHEMATIC 82443LX 69-12-21326-TW10 69-12-21325-TW10

SLLA067

Abstract: EIA-899 19-slot backplane bus. The differential voltage drops at slot 10 Figure 2. Simulated 200-Mbps eye , development guidelines for aiding the design of a high-performance system. Backplane signaling technologies , active-low condition of only 0.4 V. The bus termination voltage is reduced to 1.2 V, providing a total , system was constructed with 8-, 19-, and 30-slot bus lengths to demonstrate the capabilities of M-LVDS , 21-slot backplane (2 slots are reserved for power and 19 are used for test cards) that fits into a
Texas Instruments
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SLLA067 EIA-899 TIA/EIA-899 SLYT203

PRBS-15

Abstract: AN-1115 technologies. This paper provides tips and practical design guidelines for Bus LVDS backplanes. Concepts are , distribution. Point-to-Point, Multi-drop, and Multi-point bus configurations are shown in figure 2. Multi-drop , receivers. If the driver is located at the start of the bus, termination is only required at the far end. Multi-point allows the source to be located at any location on the bus, thus it requires termination at both , R T R T T Figure 2 - Common Bus configurations: (A) Point-toPoint, (B) Multi-drop
National Semiconductor
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PRBS-15 AN-1115 DS92LV010A DS92LV090A TR30 DSA0046046.txt RS-232

MOTHERBOARD CIRCUIT diagram explained

Abstract: PI6C304 PI7C8150 Figure 2. Four Port Ethernet Network Card VIDEO CAMERA TV /Monitor VIDEO CODEC , Bit D e s cription S_clk_o 1:0 Device 0 / slot 0 PRSNT# 0 3:2 Device 1 / slot 1 PRSNT# 1 5:4 Input clocks: The input clock frequency comes through signal P_CLK , and output at 1x or 1/2x primary input clock frequency according to: Device 2 / slot 2 PRSNT# 2 P_M 66EN Primary bus clock S_M 66EN Se condary Clock CFG66 7:6 Device 3
Pericom Semiconductor
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PI74SSTV16857 PI6CV857 MOTHERBOARD CIRCUIT diagram explained PI6C304 motherboard block diagram MOTHERBOARD pcb CIRCUIT diagram AN55 M66EN

PC intel 945 MOTHERBOARD CIRCUIT diagram

Abstract: 945 MOTHERBOARD CIRCUIT diagram .5-1 Intel® 440BX AGPset Design Guide v 5.2 5.3 5.1.3 GTL+ Bus Slot 1 Terminator Cards , placement guidelines for the motherboard and memory subsystem. Design guidelines for each bus (Host GTL , .1-1 1.1 1.2 1.3 1.4 2 About This Design Guide , PCI Bus Routing Guidelines .2-37 2.9.6 , Design Slot 1
Intel
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PC intel 945 MOTHERBOARD CIRCUIT diagram 945 MOTHERBOARD CIRCUIT diagram PC MOTHERBOARD SERVICE MANUAL BIOS Writers Guide 440BX PCIset CPUID 82443BX UP-28/29 DP-34/35 UP-30/31 DP-36-37 UP-32

LAYOUT PCB UPS 12V

Abstract: pci slot pcb layout High-Speed Board Design" 2) PCI Local Bus specification 2.2 section 4.4 "Expansion Board Specification , that can be used either within an add-in card or on a motherboard. Schematic and Layout Guidelines This section has guidelines for hardware implementation of the Pericom PI7C8152 PCI-to-PCI Bridge , secondary bus when in external arbiter mode. Finally, route the S_REQ_L[3:0] traces from the PCI slot , . Currently the PCI interface is used mainly as an expansion bus to add PCI slots on the system motherboards
Pericom Semiconductor
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LAYOUT PCB UPS 12V pci slot pcb layout PICMG 2.0 R3.0 clock SECTION OF MOTHERBOARD MOTHERBOARD schematic pci slot pinout

10kohm resistor

Abstract: motherboard at t21 card designed for 66 MHz operation is placed into a 33 MHz slot or the normally 66 MHz primary bus , High-Speed Board Design" 2) PCI Local Bus specification 2.2 section 4.4 "Expansion Board Specification , guidelines for hardware implementation of the PI7C8154 PCI-to-PCI Bridge into a motherboard or add-in card , available loads per PCI bus (2 PCI connectors or 4 embedded devices at 66MHz) · The trace length of the bus is decreased · A 66MHz PCI bus will drop to 33MHz speed when an older style 33MHz add-in card is
Pericom Semiconductor
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10kohm resistor motherboard at t21 Motherboard t21 UPS schematics 8154/8154/A AB14

USER GUIDE FW82443BX MOTHERBOARD

Abstract: PC intel 945 MOTHERBOARD CIRCUIT diagram memory subsystem. Design guidelines for each bus (Host GTL+, PCI, DRAM, and AGP) are covered. This , Design Motherboard Layout and Routing Guidelines Motherboard Layout and Routing Guidelines 2 , .1-1 1.1 1.2 1.3 1.4 2 About This Design Guide , PCI Bus Routing Guidelines .2-30 2.9.5 , .5-1 GTL+ Bus Slot 1 Terminator Cards
Intel
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USER GUIDE FW82443BX MOTHERBOARD intel 775 motherboard diagram intel pentium 4 motherboard schematic diagram AGPset FW82443BX fw82443bx 82443GX

pci card schematic

Abstract: AN-72 8140A doesn't have a PME# pin, so if your design plans to use power management events, bus the PME , Design" PCI Local Bus specification 2.2 section 4.4 "Expansion Board Specification" [decoupling through , interface is generally used as an expansion bus to add PCI slots onto system motherboards that have wide , used either within an addin card or on a motherboard. Miscellaneous Signal Connections For PI7C8140: Pin name location Requested value This section has guidelines for hardware implementation of the
Pericom Semiconductor
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PI7C8140A REQ64 pci card schematic AN-72 DISPLAY CHIP NAME FOR MOTHERBOARD motherboard schematic pci AN72 ACK64
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