NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: DS04-21336-1E DS04-21336-1E DATA SHEET ASSP Single Serial Input PLL Frequency Synthesizer On-Chip 2.5 GHz Prescaler MB15E06 MB15E06 s DESCRIPTION A RY The Fujitsu MB15E06 MB15E06 is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.5 GHz prescaler. A 64/65 or a 128/129 can be selected for the , bit low. VCO Output Frequency PLL LPF VCO y LPF Input Voltage Power Saving Mode , input 14-bit programmable reference divider: R = 5 to 16,383 Serial input 18-bit programmable divider ... | Original |
20 pages, |
programmable counter ic MB15E06PFV1 MB15E06 FPT-16P-M05 DS04-21336-1E DS04-21336-1E abstract |
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| Abstract: FUJITSU SEMICONDUCTOR DATA SHEET 2003.Sep Edition 1.1 ASSP Single Serial Input PLL Frequency Synthesizer On-chip 2.5 GHz Prescaler MB15E07SR MB15E07SR DESCRIPTION The Fujitsu MB15E07SR MB15E07SR is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.5 GHz prescaler. The 2.5 GHz , are similar to (2), set FC bit low. VCO Output Frequency PLL LPF (2) VCO LPF Input , MB15E07SR MB15E07SR was drastically improved comparing with the former single PLL, MB15E07SL MB15E07SL. The data format of ... | Original |
19 pages, |
datasheet abstract |
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| Abstract: Single Serial Input PLL Frequency Synthesizer On-chip 3.0 GHz Prescaler y ASSP DESCRIPTION The Fujitsu MB15E06SR MB15E06SR is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 3.0 GHz , phase noise MB15E06SR MB15E06SR was drastically improved comparing with the former single PLL, MB15E06 MB15E06. A refined , 128/129 Serial input 14-bit programmable reference divider: R = 3 to 16,383 Serial input , ) 10 9 Data I Serial data input using binary code. The last bit of the data is a control ... | Original |
19 pages, |
datasheet abstract |
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| Abstract: FUJITSU MICROELECTRONICS DATA SHEET DS04-21377-1Ea ASSP Single Serial Input PLL Frequency , serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.0 GHz prescaler. The 2.0 GHz , MB15E05SR MB15E05SR was drastically improved comparing wuth the former single PLL, MB15E05SL MB15E05SL. The data format of , or 128/129 · Serial input 14-bit programmable reference divider: R = 3 to 16,383 · Serial input , clock. (Open is prohibited.) 10 9 Data I Serial data input using binary code. The last ... | Original |
28 pages, |
TSSOP-16 MB15E05SRPV1 MB15E05SRPFT MB15E05SR MB15E05SL F-1602 F-16020 datasheet abstract |
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| Abstract: FUJITSU SEMICONDUCTOR DATA SHEET DS04-21377-1E DS04-21377-1E ASSP Single Serial Input PLL Frequency Synthesizer On-chip 2.0 GHz Prescaler MB15E05SR MB15E05SR s DESCRIPTION The Fujitsu MB15E05SR MB15E05SR is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.0 GHz prescaler. The 2.0 GHz prescaler has a , was drastically improved comparing wuth the former single PLL, MB15E05SL MB15E05SL. The data format of serial , modulus prescaler: 64/65 or 128/129 · Serial input 14-bit programmable reference divider: R = 3 to 16,383 ... | Original |
25 pages, |
TSSOP-16 MB15E05SRPV1 MB15E05SRPFT MB15E05SR MB15E05SL DS04-21377-1E DS04-21377-1E abstract |
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| Abstract: FUJITSU MICROELECTRONICS DATA SHEET DS04-21379-1Ea ASSP Single Serial Input PLL Frequency , serial input Phase Locked Loop (PLL) frequency synthesizer with a 3.0 GHz prescaler. The 3.0 GHz , PLL, MB15E06 MB15E06. The data format of serial data and the pin assignments except for P and R pins are same , (Continued) · Dual modulus prescaler: 64/65 or 128/129 · Serial input 14-bit programmable reference divider: R = 3 to 16,383 · Serial input programmable divider consisting of: - Binary 7-bit swallow counter ... | Original |
28 pages, |
TSSOP-16 MB15E06SRPV1 MB15E06SRPFT MB15E06SR MB15E06 datasheet abstract |
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| Abstract: FUJITSU SEMICONDUCTOR DATA SHEET DS04-21379-1E DS04-21379-1E ASSP Single Serial Input PLL Frequency Synthesizer On-chip 3.0 GHz Prescaler MB15E06SR MB15E06SR s DESCRIPTION The Fujitsu MB15E06SR MB15E06SR is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 3.0 GHz prescaler. The 3.0 GHz prescaler has a , 4.0 mA. The phase noise of MB15E06SR MB15E06SR was drastically improved comparing with the former single PLL , (Continued) · Dual modulus prescaler: 64/65 or 128/129 · Serial input 14-bit programmable reference divider ... | Original |
25 pages, |
TSSOP-16 MB15E06SRPV1 MB15E06SRPFT MB15E06SR MB15E06 DS04-21379-1E DS04-21379-1E abstract |
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| Abstract: FUJITSU MICROELECTRONICS DATA SHEET DS04�348�a ASSP Single Serial Input PLL Frequency Synthesizer On-Chip prescaler MB15C02 MB15C02 DESCRIPTION The Fujitsu Microelectronics MB15C02 MB15C02 is a serial input Phase Locked Loop (PLL) frequency synthesizer with a prescaler. A 64/65 division is available for , swallow function: 64/65 � Serial input 14-bit programmable reference divider: R = 5 to 16,383 � Serial , NC � No connection 3 4 Data I Serial data input using binary code.(Schmitt ... | Original |
28 pages, |
SSOP-20 SSOP-16 Programmable Divider MB15C02PFV2 MB15C02PFV1 MB15C02 FPT-16P-M05 datasheet abstract |
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| Abstract: To Top / Lineup / Index FUJITSU SEMICONDUCTOR DATA SHEET DS04�348� ASSP Single Serial Input PLL Frequency Synthesizer On-Chip prescaler MB15C02 MB15C02 s DESCRIPTION The Fujitsu MB15C02 MB15C02 is a serial input Phase Locked Loop (PLL) frequency synthesizer with a prescaler. A 64/65 division is , Pulse swallow function: 64/65 � Serial input 14-bit programmable reference divider: R = 5 to 16,383 � Serial input 18-bit programmable divider consisting of: - Binary 6-bit swallow counter: 0 to 63 - ... | Original |
25 pages, |
SSOP-20 SSOP-16 programmable counter ic MB15C02PFV2 MB15C02PFV1 MB15C02 FPT-16P-M05 datasheet abstract |
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| Abstract: FUJITSU SEMICONDUCTOR DATA SHEET DS04�348� ASSP Single Serial Input PLL Frequency Synthesizer On-Chip prescaler MB15C02 MB15C02 s DESCRIPTION The Fujitsu MB15C02 MB15C02 is a serial input Phase Locked Loop (PLL) frequency synthesizer with a prescaler. A 64/65 division is available for the prescaler , Serial input 14-bit programmable reference divider: R = 5 to 16,383 � Serial input 18-bit programmable , � 3 NC � No connection 3 4 Data I Serial data input using binary code. ... | Original |
25 pages, |
Programmable Divider datasheet abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| The TSA5055T TSA5055T TSA5055T TSA5055T is a single-chip PLL frequency synthesizer designed for satellite TV tuning systems. It CHANNEL CHANNEL Category DESCRIPTION TSA5055T/C3 TSA5055T/C3 TSA5055T/C3 TSA5055T/C3 PLL frequency synthesizer PLL frequency synthesizer 5 5 5 satellite PLL frequency synthesizer PLL frequency synthesizer PLL frequency synthesizer satellite satellite ICs for terrestrial and satellite TV tuners PLL frequency synthesizer www.datasheetarchive.com/files/philips/pip/tsa5055t_3-v1.html |
Philips | 14/02/2002 | 9.15 Kb | HTML | tsa5055t_3-v1.html |
| Reference Clock Outputs All Output Clock Frequencies Derived From Single 14.31818-MHz Crystal Input a crystal input. Two phase-locked loops (PLLs) are used to generate the host clockfrequency and the -clock frequency and USB frequency,respectively. The PLL circuit can be bypassed in the test mode (i.e.,SEL0 = SEL1 Data Sheet Abstract: CDC9843 CDC9843 CDC9843 CDC9843:PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS CDC9843 CDC9843 CDC9843 CDC9843 PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS SCAS559C SCAS559C SCAS559C SCAS559C - DECEMBER 1995 www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/datasht/scas559c.htm |
Texas Instruments | 01/06/1998 | 7.04 Kb | HTM | scas559c.htm |
| MHz) Six PCI Clock Outputs at Half-CPU Frequency One 48-MHz Universal Serial Bus (USB From a Single 14.31818-MHz Crystal Input LVTTL-Compatible Inputs and Outputs Internal X1 input instead of acrystal input. Two phase-locked loops (PLLs) are used to generate the host external components. ThePCI-clock frequency is derived directly from the host-clockfrequency. The PLL required following power up and application ofa fixed-frequency, fixed-phase signal at the X1 input, as www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/datasht/scas546b.htm |
Texas Instruments | 01/06/1998 | 6.66 Kb | HTM | scas546b.htm |
| at 1/2 AUDIO Clock Frequency All Output Clock Frequencies Derived From a Single 14.31818-MHz Crystal Input Internal Loop Filters for Phase-Lock Loops (PLL) Packaged in frequency, while two integrated PLLs generate a 48-MHz clock, a 24-MHz clock, and a selectable AUDIO and 1/2 AUDIO clock frequency from a 14.31818-MHz crystal input. The CDC9449 CDC9449 CDC9449 CDC9449 provides two copies of the 48 CDC9449 CDC9449 CDC9449 CDC9449 PC CLOCK SYNTHESIZER/DRIVER WITH SDRAM CLOCK www.datasheetarchive.com/files/texas-instruments/data/html/scas577.htm |
Texas Instruments | 18/08/1997 | 1.79 Kb | HTM | scas577.htm |
| Three 3.3-V 14.318-MHz Reference Clocks All Output Clock Frequencies Derived From a Single 14.31818-MHz Crystal Input Internal Loop Filters for Phase-Lock Loops (PLLs the SEL control inputs. The eight PCI clock (PCLKn) outputs are one-half the HCLK frequency, and are generate the host clock and serial bus clock frequencies. On-chip loop filters and internal feedback frequency; FCCLK is derived from the serial bus clock frequency. The host and PCI clock outputs www.datasheetarchive.com/files/texas-instruments/data/html/scas573-v1.htm |
Texas Instruments | 18/08/1997 | 3.72 Kb | HTM | scas573-v1.htm |
| Frequencies Derived From a Single 14.31818-MHz Crystal Input Internal Loop Filters for Phase IOAPIC clock at 14.318 MHz. All output frequencies are generated from a 14.31818-MHz crystal input. A test clock can be driven over the XIN input in the test mode. The oscillator and PLLs are bypassed when operating in the test mode. PLLs are used to generate the host clock and serial bus derived from the serial bus clock frequency. The host and PCI clock outputs provide low www.datasheetarchive.com/files/texas-instruments/data/html/scas547b.htm |
Texas Instruments | 19/08/1997 | 3.51 Kb | HTM | scas547b.htm |
| Three 3.3-V 14.318-MHz Reference Clocks All Output Clock Frequencies Derived From a Single 14.31818-MHz Crystal Input Internal Loop Filters for Phase-Lock Loops (PLLs the SEL control inputs. The eight PCI clock (PCLKn) outputs are one-half the HCLK frequency, and are generate the host clock and serial bus clock frequencies. On-chip loop filters and internal feedback frequency; FCCLK is derived from the serial bus clock frequency. The host and PCI clock outputs www.datasheetarchive.com/files/texas-instruments/data/html/scas573.htm |
Texas Instruments | 17/11/1997 | 3.72 Kb | HTM | scas573.htm |
| Frequencies Derived From a Single 14.31818-MHz Crystal Input Internal Loop Filters for Phase output frequencies are generated from a 14.31818-MHz crystal or oscillator input. PLLs are used to generate the host clock and serial bus clock frequencies. On-chip loop filters and internal feedback Frequency Six PCI Clock Outputs One Serial Bus 48-MHz Clock One Floppy control input. All PCI clocks operate at one-half the host clock frequency, and are offset 1 ns to 4 ns www.datasheetarchive.com/files/texas-instruments/data/html/scas574-v1.htm |
Texas Instruments | 18/08/1997 | 4.22 Kb | HTM | scas574-v1.htm |
| Frequencies Derived From a Single 14.31818-MHz Crystal Input Internal Loop Filters for Phase output frequencies are generated from a 14.31818-MHz crystal or oscillator input. PLLs are used to generate the host clock and serial bus clock frequencies. On-chip loop filters and internal feedback Frequency Six PCI Clock Outputs One Serial Bus 48-MHz Clock One Floppy control input. All PCI clocks operate at one-half the host clock frequency, and are offset 1 ns to 4 ns www.datasheetarchive.com/files/texas-instruments/data/html/scas574.htm |
Texas Instruments | 17/11/1997 | 4.22 Kb | HTM | scas574.htm |
| -bus controlled low phase noise frequency synthesizer General info The TSA5059A TSA5059A TSA5059A TSA5059A is a single chip PLL frequency synthesizer designed for satellite tuning systems up to 2.7 GHz. The RF preamplifier drives the 17-bit main divider enabling a step size equal to the comparison frequency, for an input Low noise PLL frequency synthesizer 3.3 / 5 V bus -20~85 SOT369-1 (SSOP16 SSOP16 SSOP16 SSOP16) 3 I/O + 1O N pin to drive the reference input of another synthesizer or the clock input of a digital demodulation www.datasheetarchive.com/files/philips/pip/tsa5059a_4.html |
Philips | 23/04/2003 | 6.42 Kb | HTML | tsa5059a_4.html |