85C501/502/503 SiS85C501 SiS85C502 SiS85C503 85C502 85C503 256K/1M/4M/16M - Datasheet Archive

 

1 85C501/502/503 Overview SiS85C501 SiS85C502 SiS85C503 PCI/ISA Cache Memory Controller (PCMC) PCI Local Data Buffer (PLDB) PCI

 

Pentium/P54C PCI/ISA Chipset 1 85C501/502/503 85C501/502/503 Overview SiS85C501 SiS85C501 SiS85C502 SiS85C502 SiS85C503 SiS85C503 PCI/ISA Cache Memory Controller (PCMC) PCI Local Data Buffer (PLDB) PCI System I/O (PSIO) A whole set of the SiS85C501 SiS85C501, 85C502 85C502, and 85C503 85C503 provides fully integrated support for the Pentium/P54C PCI/ISA system. The chipset is developed by using a very high level of function integration and system partitioning. With the SiS85C501 SiS85C501, SiS85C502 SiS85C502, and SiS85C503 SiS85C503 chipset, only 13 TTLs (include 3 DRAM address buffer) are required to implement a low cost, high performance, Pentium/P54C PCI/ISA system. Figure 1 shows the system block diagram. SRAM CPU Pentium , P54C 373 HOST BUS Address Data PCMC DRAM 244 501 PLDB 502 PCI BUS Address/Data PSIO PCI Local Device #1 PCI Local Device #2 * * * ISA Device #1 503 ISA Device #2 * * * XD BUS 245 ISA BUS Address Data Figure 1.1 System Block Diagram Preliminary V2.0 January 9, 1995 1 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 2. SiS85C501 SiS85C501 2.1 Features · · · · Supports the Pentium Processor at 60 MHz or 66 MHz Bus Speed Supports the P54C Processor at 50 MHz, 60 MHz or 66 MHz Bus Speed Supports the Pipelined Address Mode of the Pentium or the P54C Processor Integrated Second Level ( L2 ) Cache Controller - Write Through and Write Back Cache Modes - 8 bits or 7 bits Tag with Direct Mapped Organization - Supports Standard and Burst SRAMs - Supports 64 KBytes to 2 MBytes Cache Sizes - Cache Read/Write Cycle of 3-2-2-2 or 4-2-2-2 Using Standard SRAMs at 66 MHz - Cache Read/Write Cycle of 3-1-1-1 Using Burst SRAMs at 66 MHz · Integrated DRAM Controller - Supports 2 MBytes to 128 MBytes of Cacheable Main Memory - Concurrent Write Back - CAS#-before-RAS# Transparent DRAM Refresh - 256K/1M/4M/16M 256K/1M/4M/16M xN 70ns Fast Page Mode DRAM Support - Programmable DRAM Speed - Programmable CAS# driving Current · Two Programmable Non-Cacheable Regions · Option to Disable Local Memory in Non-Cacheable Regions · Shadow RAM in Increments of 16 KBytes · Supports Pentium/P54C SMM Mode · Supports CPU Stop Clock · Provides High Performance PCI Arbiter - Supports Four PCI Masters - Supports Rotating Priority Mechanism - Hidden Arbitration Scheme Minimizes Arbitration Overhead · Integrated PCI Bridge - Translates the CPU Cycles into the PCI Bus Cycles - Provides CPU-to-PCI Read Assembly and Write Disassembly Mechanism - Translates Sequential CPU-to-PCI Memory Write Cycles into PCI Burst Cycles - PCI Burst Write in the Pace of X-2-2-2-. - PCI Burst Read L2 Cache in X-2-2-2-. - PCI Burst Read DRAM in X-3-2-3-2-. - Cache Snoop Filters Ensure Data Coherency and Minimize Snoop Frequency · 208-Pin PQFP Package · 0.6µm CMOS Technology Preliminary V2.0 January 9, 1995 2 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 2.2 Functional Block Diagram HA[31:3] HBE[7:0]# ADS# M/IO# W/R# D/C# CACHE# BRDY# CPUHOLD CPUHLDA HITM# A20M# KEN# EADS# NA# CPURST INIT TAG[7:0] ALT ALTWE# TAGWE# KA4X KA3/KA4Y KREX#/ COE0# KREY#/ COE1# KWEX# KWEY# CALE ADSC#/ CPU PCI INTERFACE INTERFACE 502 BUFFER CONTROL CACHE CONTROL FLUSH# ADSV# KCE[7:0]#/ CWE[7:0]# RAS[3:0] CAS[7:0] RAMW# MA[11:0] PMU & MISC. DRAM CONTROL C/BE[3:0]# AD[31:0] FRAME# IRDY# TRDY# DEVSEL# STOP# PAR SERR# REQ[3:0]# GNT[3:0] PLOCK# PCICLKO PCICLKI PCIRST# HCR[1:0] ADLE# ADOE MDLE CMPSH CMPOP CPPSH CPPOP PRDLE HGDW PARITY# SMOUT WAKEUP[1:0] SMI# SMIACT# STPCLK# SIOREQ# SIOGNT# KBRST#/BREAK# TURBO# OSC ACLK CLK PWRGD SiS85C501 SiS85C501 Functional Block Diagram Preliminary V2.0 January 9, 1995 3 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 2.3 General Description The SiS85C501 SiS85C501(PCMC) bridges between the host bus and the PCI local bus. The SiS85C501 SiS85C501 (PCMC) monitors each cycle initiated by the CPU, and forwards it to the PCI bus if the CPU cycle does not target the local memory. For the CPU or the PCI bus to the local memory cycles, the built-in Cache and DRAM Controller assume control to the secondary cache, DRAMs, and the SiS85C502 SiS85C502 (PLDB). The SiS85C501 SiS85C501 (PCMC) also guides the SiS85C502 SiS85C502 (PLDB) for correct data flow. All of the Green PC functions are provided. 2.4 CPU Interface The SiS85C501 SiS85C501 is designed to support Pentium/P54C CPU host 66.667/60/50MHz. The host data bus and the DRAM bus are 64-bit wide. interface at The SiS85C501 SiS85C501 supports the pipelined addressing mode of the Pentium/P54C CPU by issuing the next address signal, NA#. NA# is only generated in two cases:a) burst read L2 cache or DRAM, and b) single read DRAM. The PCMC supports the CPU L1 write back(WB) or write through(WT) cache and the PCMC L2 WB or WT cache. The L1 cache is snooped by the assertion of EADS# when the CPU is put in the HOLD state. The PCMC issues CPUHOLD to the Pentium/P54C CPU in response to the assertion of PCI master reguests(REQ[3:0]#, and SIOREQ#). Upon receiving the CPUHLDA from the CPU, it does not immediately assert GNT[3:0]# or SIOGNT# until both the CPU to PCI posted write buffer and the Memmory write buffer are empty. During inquire cycles, the CPUHOLD may be negated temporarily to allow the CPU to write back the inquired hit modified line to L2 or DRAM. 2.5 Cache Controller The built-in L2 Cache Controller uses a direct-mapped, bank-interleaved/non-interleaved scheme, which can be configured as either in the write through or write back mode. Both standard and burst SRAMs are supported. Table 1 shows the cache sizes that are supported by the SiS85C501 SiS85C501, with the corresponding TAG RAM sizes, data RAM sizes, and cacheable memory sizes. Tables 2 and 3 summarize the performance and options when either the standard SRAMs or the Burst SRAMs are used. Preliminary V2.0 January 9, 1995 4 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Table 1 Cache Size 64K 128K 256K 512K 512K 1M 1M 2M Data RAM 8Kx8x8 8Kx8x16 32Kx8x8 32Kx8x16 64Kx8x8 128Kx8x8 64Kx8x16 128Kx8x16 Tag RAM 2Kx8 4Kx8 8Kx8 16Kx8 16Kx8 32Kx8 32Kx8 64Kx8 Alter RAM 2Kx1 4Kx1 8Kx1 16Kx1 16Kx1 32Kx1 32Kx1 64Kx1 Cacheable Size 16M 32M 64M 128M 128M 128M 128M 128M Interleaved No Yes No Yes No No Yes Yes The PCMC also provides an alternative to save the dirty SRAM chip. This is accomplished by sharing the alter bit with tag address bits in the same 8-bit wide TAG RAM. System uses this implementation supports 7 tag address bits and 1 dirty bit. By doing so, the cacheable local memory sizes are reduced to half of the original sizes as indicated in Table 1. In reality, the L2 Cacheable DRAM Size is determined by: 1) Max. L2 Cacheable Size as described in table 1. 2) Noncacheable Area defined in register 57h, 58h, 59h and 5Ah and 3) C, D, E, F Segment Cachability defined in register 53h, 54h, 55h, and 56h. But, the L1 Cacheable size is only determined by 2), 3), and the maximum DRAM size, i.e., 128 M bytes. Thus, the cycles with address ranging over the L2 Cacheable Size but within the 128M bytes can also be cacheable to L1. The behavior of KEN# is ruled by the L1 Cacheability. Note that only code of C, D, E, F segment is cacheable to L1/L2, and the data portion of C, D, E, F segment is not cacheable to L1/L2. Table 2 Standard SRAM Cycle Type 66,60 MHz Burst read 3/4/5-2-2-2 3/4/5-3-3-3 Burst write 3/4/5-2-2-2 3/4/5-3-3-3 Single read 3/4/5 Single write 3/4/5 50MHz 3/4/5-2-2-2 3/4/5-3-3-3 3/4/5-2-2-2 3/4/5-3-3-3 3/4/5 3/4/5 Note : 1: The standard SRAM speed for 66/60MHz is 15ns. For 50MHz, it is 20ns. 2: X-Y-Y-Y is the recommended setting. For example, 4-2-2-2 is the recommended cycle setting for 66MHz burst read. Preliminary V2.0 January 9, 1995 5 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Table 3 Burst SRAM Cycle type 66,60 MHz Burst read 3/4-1-1-1 3/4-2-2-2 Burst write 3/4-1-1-1 3/4-2-2-2 Single read 3/4 Single write 3/4 50MHz 3/4-1-1-1 3/4-2-2-2 3/4-1-1-1 3/4-2-2-2 3/4 3/4 Note : 1: The burst SRAM speed for 66/60MHz is 9 ns. For 50MHz, it is 12ns. 2: X-Y-Y-Y is the recommended setting. Table 4 Asynchronous SRAM speed setting (apply to read and write cycle) 66MHz 60MHz 50MHz cache configuration Tag Data Tag Data Tag 3-1-1-1 interleave -15ns 3-1-1-1 non-interleave -3-2-2-2 interleave -20ns 3-2-2-2 non-interleave -20ns 3-3-3-3 interleave -20ns 3-3-3-3 non-interleave -20ns 4-1-1-1 interleave 15ns 12ns 15ns 12ns 20ns 4-1-1-1 non-interleave -4-2-2-2 interleave 15ns 15ns 20ns 20ns 20ns 4-2-2-2 non-interleave 15ns 15ns 20ns 20ns 20ns 4-3-3-3 interleave 15ns 20ns 20ns 20ns 20ns 4-3-3-3 non-interleave 15ns 20ns 20ns 20ns 20ns 5-1-1-1 interleave 20ns 12ns 20ns 12ns 20ns 5-1-1-1 non-interleave -5-2-2-2 interleave 20ns 15ns 20ns 20ns 20ns 5-2-2-2 non-interleave 20ns 15ns 20ns 20ns 20ns 5-3-3-3 interleave 20ns 20ns 20ns 20ns 20ns 5-3-3-3 non-interleave 20ns 20ns 20ns 20ns 20ns Data 15ns -20ns 20ns 20ns 20ns 15ns -20ns 20ns 20ns 20ns 15ns -20ns 20ns 20ns 20ns 2.6 DRAM Controller The SiS85C501 SiS85C501 supports a 64-bit memory array ranging in size from 2 MBytes up to 128 MBytes. Both single-sided and double-sided 9/36-bit wide SIMM modules are supported. The DRAM controller of 85C501 85C501 can support up to 4 banks (8 SIMMS) of single-sided SIMM module, or 2 banks (4 SIMMs) of double-sided SIMM module. The 12-bit multiplexed row/column Preliminary V2.0 January 9, 1995 6 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset address MA[11:0] allows the PCMC to support 256K, 1M, 4M, and 16M 70ns fast page mode DRAMs. Table 5. shows the corresponding request address bits used in column address and row address for the DRAM. Table 5. MA Generation Table Body 256K 1M Type MA CAS RAS CAS A3 MA0 A3 A12 MA1 A4 A13 A4 A5 A14 A5 MA2 A15 A6 MA3 A6 MA4 A7 A16 A7 A8 A17 A8 MA5 A9 A18 A9 MA6 A19 A10 MA7 A10 A11 MA8 A11 A20 NA NA A12 MA9 NA NA MA10 NA NA NA MA11 NA 4M RAS A22 A13 A14 A15 A16 A17 A18 A19 A20 A21 NA NA CAS A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 NA 16M RAS A22 A24 A14 A15 A16 A17 A18 A19 A20 A21 A23 NA CAS A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 RAS A22 A24 A26 A15 A16 A17 A18 A19 A20 A21 A23 A25 To improve the CPU write DRAMs performance, there is a one level built-in CPU-to-Memory posted write buffer with 4 QWs deep (CTMPB). All the single writes and the burst writes are buffered. In the CPU read miss/line fill cycle, the write-back data from the L2 cache are also buffered into the CTMPB. At the same time, the PCMC starts reading from the DRAMs. The buffered data are written to the DRAMs when the read cycle completes. With this concurrent write back policy, many wait states are eliminated. However, any other cycle targeting the DRAMs will be suspended until the CTMPB is empty. Typically, it takes about 30 CPUCLK to complete a read miss/line fill cycle in 60/66 MHz system, and about 25 CPUCLK for 50 MHz system. Table 6 outlines the read and write DRAM cycle performance based on 70ns DRAMs. Table 6 DRAM Performance Cycle type read (page hit/row miss/page miss) posted write write retire rate Preliminary V2.0 January 9, 1995 66,60 MHz 7/11/14-4-4-4 8/12/15-5-5-5 9/13/16-6-6-6 3/4/5-1-1-1 3/4/5-2-2-2 3/4/5-3-3-3 3/4/5 7 50MHz 7/11/14-4-4-4 8/12/15-5-5-5 9/13/16-6-6-6 3/4/5-1-1-1 3/4/5-2-2-2 3/4/5-3-3-3 3/4/5 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Note: 1: X-Y-Y-Y is the recommended setting. 2: In read cycles, the CAS# precharge time is 2T. Table 7 DRAM speed setting based on 70ns DRAM (apply to read and write cycle) register 66MHz 60MHz 50MHz read CAS pulse width 50h bit 7-6 2T 2T 2T write CAS pulse width 50h bit 5 2T 2T 2T CAS precharge time 53h bit 7 2T 2T 1T RAS precharge time 53h bit 1 4T 4T 4T RAS to CAS delay time 53h bit 2 4T 4T 3T refresh RAS active time 52h bit 0 5T 5T 4T DRAM write push to CAS 5Bh bit 3 2T 2T 2T delay 2.7 PCI Arbiter The SiS85C501 SiS85C501 contains a high performance hidden arbitration scheme that allows efficient bus sharing among five PCI Masters and the CPU. Note that one PCI master is reserved for the PSIO chip. The SiS85C501 SiS85C501 employs the priority rotation scheme that is done at two different layers. The first layer is shared between PSIO and four PCI Masters as a group. The second layer consists of four PCI masters with equal priority. Arbitration is done at both layers. The winner of arbitration among the four PCI masters arbitrates the PCI bus against PSIO. Fair rotation scheme applies only at layer level. The arbitration scheme assures that ISA master or DMA channels (represented by PSIO) access the bus with minimal latency. The PSIO is given a high level of priority to assure compatibility with traditional ISA expansion boards that require short bus latency. This implementation together with PCI Programmable Bursting Address Counter guarantees ISA device will not be starved during PCI master long bursting cycle. For example, When the maximum bursting length is 512 bytes, the maximum arbitration latency for PSIO, and PCI master is about 12us, and 40us respectively. The following two figures detail the rotation arbitration structure and its corresponding timing diagram. Preliminary V2.0 January 9, 1995 8 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Rotation Arbitration Scheme: BUS GRANT PRIORITY SW1 G4 G0123 G0123 SW2 G23 G01 SW3 G0 SW4 G2 G1 G3 Notation: SW1: is the switch for path from node G4 or G0123 G0123 to BUS GRANT PRIORITY SW2: is the switch for path from node G01 or G23 to node G0123 G0123 SW3: is the switch for path from node G0 or G1 to node G01 SW4: is the switch for path from node G2 or G3 to node G23 G01, G23, G0123 G0123: are intermediate nodes G4: is the bus request from PSIO G0, G1, G2, G3: are the bus requests from PCI device 0, device 1, device 2, device 3 respectively. Initial Path Parking: SW1 : BUS GRANT PRIORITY-G4 SW2 : G0123-G01 G0123-G01 SW3 : G01-G0 G01-G0 SW4 : G23-G2 G23-G2 Rule of Rotating Priority for Bus Arbitration: · BUS GRANT PRIORITY will choose a path whenever it encounters an optional path. · PCI bus will be granted as Daisy Chain · Path switches will be toggled from BUS GRANT PRIORITY to any request node (G4, G0, G1, G2, G3) if any of them have been utilized Example: Initial Priority:G4, G01, G0, G2 1. PSIO(G4) Request Bus SIOGNT# is asserted SW1 is toggled to G0123 G0123 (since it has been utilized) Priority change to G0, G1, G2, G3, G4 Preliminary V2.0 January 9, 1995 9 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 2. PSIO, REQ3, REQ2, REQ1, REQ0 are requesting bus GNT0# is asserted SW1, SW2 and SW3 are toggled to G4, G23 and G1 respectively (since they have been utilized) Priority change to G4, G2, G3, G1, G0 3. REQ3, REQ2, REQ1, REQ0 are active GNT2# is asserted SW2, SW4 are toggled to G01 and G3 respectively (since they have been utilized) Priority change to G4, G1, G0, G3, G2 4. REQ3, REQ2, REQ1, REQ0 are active GNT1# is asserted SW2, SW3 are toggled to G23 and G0 respectively (since they have been utilized) Priority change to G4, G3, G2, G0, G1 5. REQ3, REQ2, REQ1, REQ0 are active GNT3# is asserted SW2, SW4 are toggled to G01 and G2 respectively (since they have been utilized) Priority change to G4, G0, G1, G2, G3 6. During 3-5 if there is a request comes from PSIO, the Arbiter will grant bus to PSIO. PCI Arbiter - Rotation Arbitration scheme CPUCLK PCICLK REQ[3:0]# F 0 SIOREQ# GNT[3:0]# F E B D 7 E SIOGNT# HOLD CPUHOLD CPUHLDA HLDA FRAME# IRDY# 501arbi Note : HOLD is internal signal A PCI master can burst so long as the target can source/sink the data, and no other agent requests the bus. However, PCI specifies two mechanisms that cap a master's tenure in the presence of other requests, so that predictable bus acquisition latency can be achieved. One is Preliminary V2.0 January 9, 1995 10 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset the Master Latency Timer(LT) that is not implemented into the PCMC, the other is the Target Initiated Termination. In the SiS85C501 SiS85C501, a Programmable Bursting Address Counter(PBAC) is implemented to disconnect the PCI master during the long bursting cycle. In this way, high throughput is maintained, and the bus latency is still kept reasonably small. Note that the bursting length is naturally applied to PCI master to local memory accessing. When PCI master accesses non-local memory target, the master and target should together have the responsibility of maintaining reasonable latency, but not the system arbiter does. The PCI arbiter asserts only one GNT# at any time. The 85C501 85C501 has also implemented a timeout counter to prevent faulty device hugging the bus. If the PCI bus is granted to a PCI device and the bus is currently idle, 16 PCI clocks is the limitation that device should assert FRAME# during the period of time. If time-out occurs, the arbiter will mask request line, therefore desserts GNT#. When this happens, all PCI devices start arbitration again. Note that PSIO is free to this constraint. The 85C501 85C501 PCI master will also mask the PSIO request to the arbiter if the PCI LOCK# is asserted to keep ISA master or DMA channels target latency within specification. The 85C501 85C501 PCI arbiter is also allowed to force system back to CPU each time after SIOREQ# is serviced. This function is disabled by default, and can be enabled by set bit 7 of register 6F in the PCMC Configuration space. 2.8 PCI Bridge 2.8.1 PCI Master Controller The PCI Master Controller forwards the CPU cycles not targeting the local memory to the PCI bus. In the case of a 64-bit CPU request or a misaligned 32-bit CPU request, the PCMC assumes the read assembly and write disassembly control. A 4 level posted write buffer (CTPPB) is implemented to improve the CPU to PCI memory write performance. Except for on-board memory write cycles, any cycles forwarded to the PCI bus will be suspended until the CTPPB is empty. For PCI bus memory write cycles, the CPU data are pushed into the CTPPB if it is not full. The pushed data are, at later time, written to the PCI bus. If the consecutive written data are in DW incremental sequence, they will be transferred to the PCI bus in a burst manner. The burst transfer rate is always X-2-2-2-. until 128 DWs are exhausted. The PCI master interface can read data from or write data to the PCI bus at the utmost speed of 1 wait state. This is due to the fact that the PCMC drives the PCI bus address and the PLDB drives the PCI bus data. That necessitates a turn around cycle between the address and the data phases. The PCMC provides a mechanism for converting standard I/O cycles on the CPU bus to Configuration cycles on the PCI bus. Configuration Mechanism #1 in PCI Specification 2.0 page 61 is used to do the cycle conversion. The PCMC always intercepts the first interrupt acknowledge cycle from CPU bus, and forwards the second interrupt acknowledge cycle onto the PCI bus. Preliminary V2.0 January 9, 1995 11 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 2.8.2 PCI Slave Controller The SiS85C501 SiS85C501 operates as a slave on the PCI bus whenever a PCI master requests an access to the SiS85C501 SiS85C501 resource such as Cache, DRAM and the SiS85C501 SiS85C501 Internal registers. Note that the internal registers can only be accessed by the SiS85C501 SiS85C501 itself when in CPU cycle. In the SiS85C500 SiS85C500 PCI/ISA system, the CPU is placed in HOLD state before granting the PCI bus to a PCI master. The following figure shows the behavior of CPUHOLD/CPUHLDA in response to PCI masters requests. Only linear ordered PCI cycles are supported by the PCMC PCI slave interface. CPUCLK PCICLK REQ# HOLD CPUHOLD CPUHLDA HLDA GNT# FRAME# IRDY# CIP# HA AD 501 drives HA PCI master drives AD 501 park 501 park 501req Note : HOLD,CIP# (current in progress) are internal signal A PCI master to the local memory access is not conducted until the snoop cycle has completed. The snoop cycle is used to inquire the first level cache to maintain coherency between first level and second level caches and main memory. Snoop cycles are performed by driving the PCI master address onto the CPU bus and asserting EADS#. Depending on the status of HITM# two clocks after the assertion of EADS#, PCMC conducts the PCI master cycles as table 8 outlines. Preliminary V2.0 January 9, 1995 12 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Table 8 PCI Master Read Cycle L1 Miss (or Unmodified) Miss (or Unmodified) HitM HitM L2 Miss Hit (Dirty or !Dirty) Miss Hit (Dirty or !Dirty) PCI Master write Cycle L1 L2 Miss (or Unmodified) Miss Miss (or Unmodified) Hit (Dirty or !Dirty) HitM Miss HitM Hit (Dirty or !Dirty) Data Transfer Data transfer from DRAM to PCI Data transfer from L2 to PCI Data is first written back from L1 to DRAM. Then, PCI master gets data from DRAM. Data is first written back from L1 to L2. Then, PCI master gets data from L2. The line is marked dirty in the L2. Data Transfer Data transfer from PCI to DRAM Data transfer from PCI to DRAM and L2. The Dirty bit is not changed. Data is first written back from L1 to DRAM. Then, PCI master writes data to DRAM. Data is first written back from L1 to L2. Then, PCI master writes data to L2 and DRAM. The Line is marked dirty in the L2. A snoop filter is implemented to prevent the need of multiple inquires to the same line if the line was inquired previously. To support snoop filter, a Snoop Address Latch (SAL) and a Line Comparator are implemented. The line comparator is used to determine if the New Address (NA) is the same as the content of the SAL. If it is not, the NA is loaded into the SAL, and a snoop cycle is issued. In addition, a Valid bit in association with the SAL is used to ensure the snoop filtering is effective only when HLDA is asserted. The simplified filter algorithm is: 1) Write Back Mode a) if NA=SAL in a PCI master write cycle, the PCMC only issues EADS#. It does not wait for the status of HITM#. b) if NA=SAL in a PCI master read cycle, no snoop cycle nor EADS# is issued. c) if NASAL in a PCI master cycle, the PCMC issues a snoop cycle by EADS#, and then monitors the status of HITM#. d) During a burst transaction, the PCMC automatically generates a snoop cycle when the address advances across a new line. 2) Write Through Mode In the following two cases, the PCMC only generates EADS#. It ignores the logic of HITM#. a) if NA=SAL in a PCI master write cycle, and b) During a burst transaction, the address advances across a new line. Preliminary V2.0 January 9, 1995 13 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset In the SiS85C500 SiS85C500, the INV signal of P54C should be connected to W/R# that is driven by the SiS85C501 SiS85C501 in the PCI master cycle. In this way, the SiS85C501 SiS85C501 can invalidate the line that is currently inquired via the assertion of EADS# in the PCI master write cycles. The PCMC slave interface supports PCI burst transfers. A burst transfer will be disconnected (retry) if the transfer goes across the 512 bytes(or 1 KBytes selected by Register 5Dh, bit 5) address boundary. This is due to the fact that the address generator, to support the burst transfer, can only address 512 or 1K bytes. In this way, at most 32 cache lines can be uninterruptedly transferred if they are in I, S, or E state in the L1 cache. Another reason for the constraint is that page miss may occur only once during the entire bursting transaction since the maximum bursting length is always within the page size in any of the used DRAM . The PCI master writes are buffered in the one QW deep PCI to Memory posted write buffer (PTMPB). The PCMC always packs an aligned QW PCI write data into the write buffer, and then retires it into the DRAM array or the L2 cache. The PCI master write performance, to the utmost, is X-2-2-2- . The PCI master reads are through a QW read buffer with which the burst transfers can perform in the pace of X-2-2-2-. (from the L2 cache), or X-3-2-3-2-. (from the DRAMs). Concurrent refresh will still be performed when CPU is put into Hold state. If the DRAM is idle, refresh can be conducted at any time. If refresh request occurs at the same time that a PCI master wants to access DRAM, an arbitration scheme is employed to resolve the conflict. The refresh request may thus get service while the PCI master accessing is suspended until refresh cycle is completed. Although refresh may win the DRAM bus, at most one refresh cycle may be conducted for each individual PCI transaction, i.e. for each Frame# initiating. On the other hand, refresh may be also deferred until the DRAM is idle. In SiS85C500 SiS85C500 system, the refresh may be postponed for no more than 24 us in the worst case when a PCI master is reading the whole 32 lines through one burst transaction. 2.8.3 PCI Bus Speed Setting The following settings apply to all system environment, even though the system is running at 66MHz while the PCI bus is running at 33MHz. Preliminary V2.0 January 9, 1995 14 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Table 9 PCI bus setting latency from ADS# to monitor local memory status CAS# pulse width in PCI master write cycle latency from the disarming of "full" to the assertion of BRDY# for the pending CPU to PCI write cycle latency from reading L2/DRAM to the assertion of TRDY# in PCI master read cycles latency from packing one Qword into PTMPB to the assertion of CAS#(or KWE#) latency from TRDY# to BRDY# in CPU read/write PCI slave cycles Register 5Ch bit 7 Setting 2T Unit CPUCLK 5Ch bit 4 5Ch bit 3 1T 1T PCICLK CPUCLK 5Dh bit 4 1T PCICLK 5Dh bit 3 1T PCICLK 5Dh bit 2 2T CPUCLK 2.9 Green PC Function The following paragraphs are the PMU ( Power Management Unit ) features description: 2.9.1 Power States The PMU provides different power management states, which are described in the following sections. (i) Monitor Standby State The Monitor will be blanked and the external devices are turned off through SMOUT when the Monitor standby timer expires. Monitor Standby monitors the following events: IRQ 1-15 HOLD NMI Each IRQ has two sets of mask bits, one for wake up mask, and the other for standby mask. The HOLD includes the PCI local masters and the ISA master request. Each event is maskable. If no event happens during the monitored period and the timer expires, an SMI is generated and the monitor enters the standby state. Once the Monitor is in the standby state, any event from IRQ1-15 IRQ1-15, NMI or HOLD will cause an SMI which brings the Monitor back to the normal state. The time slot of the Monitor standby timer is programmable to 6.6sec, 0.84sec, 13.3ms, 1.6ms. (ii) System Standby State Preliminary V2.0 January 9, 1995 15 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset If the system standby timer expires, an SMI is generated for the system to enter the system standby state. The following events happen: STPCLK# is asserted to stop the CPU clock The hard disk drives spindle motors can be turned off The serial, parallel ports or the programmable I/O port can be turned off Once the STPCLK# is asserted, any events from IRQ1-15 IRQ1-15, NMI, HOLD, INIT will cause the STPCLK# be de-asserted. If any of the Hard disk motors, serial, parallel or programmable I/O ports were turned off, they will be back to the normal state only when they are accessed. System Standby monitored events (each event is maskable) Programmable I/O ports (one is a 10-bit I/O port, another is a16-bit I/O port) IRQ 1-15 (each has 2 sets of mask bits as for Monitor Standby State) HOLD NMI Hard Disk ports ( 1F0-1F7h, 3F6-3F7h, 170-17Fh, 320-32Fh) Serial ports ( 2F8-2FFh, 3F8-3FFh, 2E8-2EFh, 3E8-3EFh) Parallel ports ( 278-27Fh, 378-37Fh, 3BC-3BEh) A0000-AFFFFh or B0000-BFFFFh Address trap (Video RAM) C0000-C7FFFh Address trap (Video BIOS) 3Bx-3Dxh (Video I/O port) The time slot of the System standby timer is programmable to 9 sec, 1.1 sec, 70ms, and 8.85ms. (iii) Throttling state In throttling state, STPCLK# is asserted and de-asserted periodically. This function is maskable. The throttling timer (Registers 61h and 62h) is programmable and the time slot is 35us. 2.9.2 Break Switch SMI If the break switch is pressed, it will cause an SMI. The SMI can not be used to wake up any standby state. Instead, it is used to enter the standby state. The signal from the break switch is a level trigger signal which lasts for more than 3 CPU clocks. 2.9.3 Software SMI If the software SMI enable bit is set and a '1' is written to bit 1 of Register 60h, an SMI# is generated and the software SMI service routine is invoked. The bit 1 of Register 60h should be cleared at the end of the SMI handler. Preliminary V2.0 January 9, 1995 16 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 2.10 Configuration Registers The PCMC contains two sets of registers: the I/O mapped registers and the PCI configuration space mapped registers. 2.10.1 I/O Mapped Registers The SiS85C501 SiS85C501 uses PCI configuration space access mechanism #1. This mechanism defines two DWORD registers. The first register(CF8h) references a read/write register that is named CONFIG_ADDRESS. The second register (CFCh) references a register named CONFIG_DATA. The mechanism in accessing configuration space is to write a value into CONFIG_ADDRESS that specifies the PCI bus, device on that bus, and the configuration register in that device being accessed. A read or write to CONFIG_DATA will then cause the bridge to translate that CONFIG_ADDRESS value to the requested configuration cycle on the PCI bus. The definition of CONFIG_ADDRESS register is described below: Register 0CF8h CONFIG_ADDRESS Register 31 30 24 23 16 15 11 10 8 7 2 1 0 Device Function Register Number 0 0 Reserved Bus Number Number Number Enable bit ('1' = enabled, '0' = disabled) Bit 31 is an enable flag for determining if the accesses to CONFIG_DATA should be translated to configuration cycles on the PCI bus. Bits 30:24 Reserved, read only, and must return 0's when read. Bits 23:16 Choose a specific PCI bus in the system. Bits 15:11 Choose a specific device on the bus. Bits 10:8 Choose a specific function in a device. Bits 7:2 Choose a DWORD in the device's configuration space. Bits 1:0 read only and must return 0's when read. A full Dword I/O writes to 0CF8h address will load the CONFIG_ADDRESS register . Also, a full DWord I/O Read to 0CF8h gets the data from CONFIG_ADDRESS register . Writes or Reads to any other length other than a DWORD are passed to PCI I/O cycles. When the SiS85C501 SiS85C501 sees an I/O access that falls inside the Dword beginning at CONFIG_DATA address, it checks the enable bit in the CONFIG_ADDRESS register. If the bit is 0, the I/O cycle is passed to PCI unchanged. If the bit is 1, the I/O cycle is translated into a configuration cycle. Preliminary V2.0 January 9, 1995 17 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset If the Bus Number field of the CONFIG_ADDRESS register is zero, the I/O cycle is translated into a Type 0 configuration cycle; if the Bus Number field is non-zero, the I/O cycle is translated into a Type 1 configuration cycle. The PCMC is considered device 0 on bus 0. Thus, a configuration cycle to device 0 on bus 0 is translated as a PCI configuration cycle that is responded by PCMC via the assertion of DEVSEL#. A type 0 configuration cycle is indicated on the PCI bus by driving AD[1:0]=00 during the address phase of the cycle. The device number in CONFIG_ADDRESS is decoded and ensures one of the AD[31:11] to be driven high during the address phase of the configuration cycle. For instance, AD11 is high when the device number is 0. The AD[31:12] lines is used as the IDSEL signal of the target service. Never use AD11 as the IDSEL line for any other PCI target device since it is reserved for PCMC. CONFIG_ADDRESS bit 10 to 2 are copied directly to AD[10:2]. A type 1 configuration cycle is translated on the PCI bus by driving AD[1:0]=01 during the address phase of the cycle. CONFIG_ADDRESS bits 31 to 2 are copied directly to AD[31:2] during the address phase of the cycle. The byte-enables for the data phase of the either types of configuration cycle are copied from the HBE[7:4]#. The following programming sequences is an example of writing register 51h in PCMC and of reading register 5Ch, 5Dh, 5Eh and 5Fh in PCMC. write 51h: MOV EAX, 80000050h OUT 0CF8h, EAX MOV AL, DATA OUT 0CFDh, AL read 5Ch, 5Dh, 5Eh and 5Fh: MOV EAX, 8000005Ch OUT 0CF8h, EAX IN 0CFCh Register 0CF9h Turbo and Reset Control Register . Bits 7:5 Reserved Bit 4 INIT Enable When this bit is set to 1 ,the PCMC drives INIT during software reset. When this bit is cleared to 0, the PCMC drives CPURST during software reset, and INIT is inactive. Bit 3 CPU BIST Enable. When this bit is set to 1 and bit 4 as well as bit 1 are enabled, a subsequent initiation of the CPU hard reset through bit 2 of this register enables the Built Preliminary V2.0 January 9, 1995 18 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset In Self Test(BIST) mode of the CPU. The PCMC also drives the INIT during the hard reset. Bit 2 Reset CPU. There are two types of resets to the CPU: a hard reset using the CPURST signal and a soft reset using the INIT signal. If bit 1 of this register is set to 1 and bit 2 transitions from 0 to 1, the PCMC initiates a hard reset. A hard reset through this register thus requires two write operations to this register: the first write operation writes a 1 to bit 1 and a 0 to bit 2. The second write operation writes a 1 to bit 1 and a 1 to bit 2. When bit 1 of this register is 0 and bit 2 transitions from 0 to 1, the PCMC initiates a soft reset. The sequence to initiate a soft reset through this register is identical to that of a hard reset except a 0 is written to bit 1 in the first write operation. Bit 1 Enable System Hard Reset. When this bit is set to 1 and bit 2 transitions from 0 to 1, the PCMC initiates a hard reset to the CPU . When this bit is 0 and bit 2 transitions from 0 to 1, the PCMC initiates a soft reset to the CPU. Bit 0 Select Turbo /DeTurbo Mode. There are two ways to enter Deturbo mode. One is through software; another is hardware. · Software Deturbo: Set Reg. 5Bh bit 1 to 1, and Reg. 65h bit 3 to 1,then set Reg. CF9h bit 0 to 1. · Hardware Deturbo: Set Reg. 5Bh bit 1 to 1, and Reg. 65h bit 3 to 1, then press deturbo switch. 2.10.2 PCI Configuration Space Mapped Registers Register 00h Bits 7:0 Vendor ID - low byte 39h Register 01h Bits 7:0 Vendor ID - high byte 10h Register 02h Bits 7:0 Device ID - low byte 06h Register 03h Bits 7:0 Device ID - high byte 04h Register 04h Command - low byte Bit 7 Reserved Bit 6 Respond to parity. This bit is always 0 since the PCMC does not support parity checking on the PCI bus Preliminary V2.0 January 9, 1995 19 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Bits 5:4 Reserved Bit 3 Enable special cycle. This bit is always 0 since the PCMC does not issue special cycle. Bit 2 Enable bus master. This bit is always 1, allowing the PCMC to serve as a PCI bus master. Bit 1 Enable response to memory access. 0: Disables PCI master's accesses to local memory 1: Enables PCI master's accesses to local memory Bit 0 Enable response to I/O access. This bit is always 0 since the PCMC does not respond to any PCI I/O cycles. The PCMC only responds to CPU initiated I/O cycles. Register 05h Bits 7:0 Register 06h Bits 7:0 Register 07h Bit 7 Command - high byte Reserved Status - low byte Reserved Status - high byte Detected parity error. This bit is always 0 since the PCMC does not support parity checking on the PCI bus. Bit 6 Signaled system error. This bit is set when the PCMC asserts SERR#. This bit is cleared by writing a 1 to it. Bit 5 Received master abort. This bit is set by the PCMC whenever it terminates a transaction with master abort. This bit is cleared by writing a 1 to it. Bit 4 Received target abort. This bit is set when a CPU to PCI transaction is terminated with target abort. This bit is cleared by writing a 1 to it. Bit 3 Signaled target abort. This bit is always 0 since the PCMC will not terminate a transaction with target abort. Preliminary V2.0 January 9, 1995 20 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Bits 2:1 DEVSEL# Timing DEVT. The two bits define the timing to assert DEVSEL#. The PCMC asserts the DEVSEL# signal within three clocks after the assertion of FRAME#. The default value is DEVT=10. In fact, the PCMC always asserts DEVSEL# in medium timing except in CPU writes to I/O port 64h or 60h. Reserved Bit 0 Register 08h Bits 7:0 Revision Identification. 00h. Register 0B~09h Class Code Bits 23:0 060000h Register 50h Bits 7:6 DRAM Read CAS Pulse Width 00 : 4T 01 : 3T 10 : 2T 11 : Reserved Bit 5 Bits 4:0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 DRAM Write CAS Pulse Width 0 : 3T 1 : 2T DRAM configuration SIMM 1 256K-S 256K-S 256K-S 256K-S 256K-S 256K-S 512K-D 512K-D 256K-S 256K-S 256K-S 256K-S 512K-D 512K-D 512K-D 512K-D 512K-D 512K-D 512K-D 512K-D 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S SIMM 2 256K-S 256K-S 256K-S 256K-S 256K-S 256K-S 512K-D 512K-D 256K-S 256K-S 256K-S 256K-S 512K-D 512K-D 512K-D 512K-D 512K-D 512K-D 512K-D 512K-D 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S 1M-S SIMM3 SIMM 4 256K-S 256K-S 256K-S 256K-S 1M-S 256K-S 256K-S 256K-S 256K-S 256K-S 256K-S 256K-S 256K-S 1M-S 256K-S 256K-S 256K-S 256K-S 512K-D 512K-D 2M-D 4M-S 512K-D 512K-D 2M-D 4M-S 1M-S 1M-S 2M-D 1M-S 1M-S 2M-D 4M-S 1M-S 4M-S 1M-S 1M-S 2M-D 1M-S 1M-S 2M-D 4M-S 1M-S 4M-S Preliminary V2.0 January 9, 1995 21 SIMM 5 SIMM 6 1M-S 1M-S 1M-S 4M-S 1M-S 4M-S 1M-S 1M-S 1M-S 2M-D 1M-S 1M-S 2M-D 1M-S 4M-S 4M-S 4M-S 4M-S SIMM 7 SIMM 8 1M-S 1M-S 1M-S 1M-S Total 2MB 4MB 12MB 12MB 20MB 36MB 4MB 8MB 20MB 36MB 8MB 16MB 24MB 24MB 32MB 40MB 48MB 72MB Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 1M-S 1M-S 1M-S 2M-D 2M-D 2M-D 2M-D 2M-D 4M-S 4M-S 4M-S 4M-S 4M-S 8M-D 8M-D 16M-S 16M-S 1M-S 1M-S 1M-S 2M-D 2M-D 2M-D 2M-D 2M-D 4M-S 4M-S 4M-S 4M-S 4M-S 8M-D 8M-D 16M-S 16M-S 8M-D 1M-S 1M-S 8M-D 1M-S 1M-S 2M-D 4M-S 4M-S 8M-D 2M-D 4M-S 4M-S 8M-D 4M-S 4M-S 8M-D 4M-S 4M-S 4M-S 8M-D 4M-S 8M-D 8M-D 4M-S 2M-D 4M-S 8M-D 4M-S 4M-S 4M-S 4M-S 4M-S 4M-S 4M-S 4M-S 4M-S 4M-S 72MB 80MB 16MB 32MB 48MB 80MB 80MB 32MB 64MB 96MB 96MB 128MB 128MB 64MB 128MB 128MB 128MB 128MB Register 51h Bit 7 L2 Cache Exist or not 0 : Not Exist 1 : Exist Bit 6 L2 Cache Enable 0 : Disable 1 : Enable Bit 5 SRAM type ( Standard or Burst ) 0 : Standard SRAM 1 : Burst SRAM Bit 4 L2 Cache WT/WB Policy 0 : Write-Through mode 1 : Write-Back mode Bits 3:1 L2 Cache Size 000 : 64KB 001 : 128KB 128KB 010 : 256KB 256KB 011 : 512KB 512KB 100 : 1MB 101 : 2MB 11x : Reserved Preliminary V2.0 January 9, 1995 22 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Bit 0 CPU L1 Cache Write-Back Enable 0 : Disable 1 : Enable Register 52h Bits 7:6 Standard SRAM Cache speed (Read/Write) 00 : 5-x-x-x Slower 01 : 4-x-x-x Faster 10 : 3-x-x-x Fastest 11 : Reserved Bits 5:4 Standard/Burst SRAM x Setting (Burst Read/Write cycle ) 00 : 3T x1 : 1T 10 : 2T Bit 3 Cache Interleave Enable 0 : Disable 1 : Enable Bit 2 Burst SRAM Cache Burst Cycle 0 : 4-x-x-x 1 : 3-x-x-x Bit 1 Cache Sizing Enable 0: Normal Operation 1: Always Cache hit to enable Cache Sizing for BIOS Bit 0 Refresh RAS Active time 0 : 6T 1 : 5T Register 53h Bit 7 DRAM CAS precharge time 0 : 2T 1 : 1T Bit 6 Shadow RAM Read Enable 0 : Disable Preliminary V2.0 January 9, 1995 23 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 1 : Enable When this bit is enabled, the F segment is shadowed by default. Before shadowing, BIOS should not turn on the bit so that reading F segment is always forwarded to PCI bus. Bit 5 Shadow RAM Write Protection Enable 0 : Disable 1 : Enable After porting the shadowed segment into DRAM, this bit can be set so that the corresponding shadowed segment is not writable. Under such circumstances, the cycle which intends to write the segment is treated as non-local memory cycle, and is forwarded to PCI bus. Bit 4 Shadow RAM Enable for PCI Master Accesses 0 : Disable 1 : Enable Bit 3 F0000h - FFFFFh Shadow RAM Cacheable 0 : Non-Cacheable 1 : Cacheable Note that only code is cacheable to L2/L1 when this bit is set. Bit 2 RAS to CAS delay time 0 : 4T 1 : 3T Bit 1 RAS precharge time 0 : 5T 1 : 4T Bit 0 Enable host to CTMPB push rate to be X-1-1-1 0 : Enable 1 : Disable. When this bit is disabled, the push rate is defined by bit [5:4] of register 52h. Register 54h E Segment Setting Bit 7 E0000h - E3FFFh Shadow RAM Enable Bit 6 E4000h - E7FFFh Shadow RAM Enable Bit 5 E8000h - EBFFFh Shadow RAM Enable Bit 4 EC000h - EFFFFh Shadow RAM Enable Preliminary V2.0 January 9, 1995 24 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Bit 3 E0000h - E3FFFh Shadow RAM Cacheable Bit 2 E4000h - E7FFFh Shadow RAM Cacheable Bit 1 E8000h - EBFFFh Shadow RAM Cacheable Bit 0 EC000h - EFFFFh Shadow RAM Cacheable Register 55h D Segment Setting Bit 7 D0000h - D3FFFh Shadow RAM Enable Bit 6 D4000h - D7FFFh Shadow RAM Enable Bit 5 D8000h - DBFFFh Shadow RAM Enable Bit 4 DC000h - DFFFFh Shadow RAM Enable Bit 3 D0000h - D3FFFh Shadow RAM Cacheable Bit 2 D4000h - D7FFFh Shadow RAM Cacheable Bit 1 D8000h - DBFFFh Shadow RAM Cacheable Bit 0 DC000h - DFFFFh Shadow RAM Cacheable Register 56h C Segment Setting Bit 7 C0000h - C3FFFh Shadow RAM Enable Bit 6 C4000h - C7FFFh Shadow RAM Enable Bit 5 C8000h - CBFFFh Shadow RAM Enable Bit 4 CC000h - CFFFFh Shadow RAM Enable Bit 3 C0000h - C3FFFh Shadow RAM Cacheable Bit 2 C4000h - C7FFFh Shadow RAM Cacheable Bit 1 C8000h - CBFFFh Shadow RAM Cacheable Bit 0 CC000h - CFFFFh Shadow RAM Cacheable Register 57h Bit 7 Allocation of Non-cacheable Area #1 0 : Local DRAM 1 : AT Bus. The local DRAM is disabled. Bit 6 Non-cacheable Area #1 Enable 0 : Disable Preliminary V2.0 January 9, 1995 25 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 1 : Enable Bits 5:3 Size of Non-Cacheable Area #1 (within 128 MBytes) 000 : 64KB 001 : 128KB 128KB 010 : 256KB 256KB 011 : 512KB 512KB 100 : 1MB 101 : 2MB 110 : 4MB 111 : 8MB Bits 2:0 A26 ~ A24 of Non-Cacheable Area #1 (within 128MBytes) Register 58h Bits 7~0 A23 ~ A16 of Non-Cacheable Area #1 (within 128MBytes) Register 59h Bit 7 Allocation of Non-cacheable Area #2 0 : Local DRAM 1 : AT Bus. The local DRAM is disabled. Bit 6 Non-cacheable Area #2 Enable 0 : Disable 1 : Enable Bits 5:3 Size of Non-Cacheable Area #2 (within 128MBytes) 000 : 64KB 001 : 128KB 128KB 010 : 256KB 256KB 011 : 512KB 512KB 100 : 1MB 101 : 2MB 110 : 4MB 111 : 8MB Bits 2:0 A26 ~ A24 of Non-Cacheable Area #2 (within 128MBytes) Preliminary V2.0 January 9, 1995 26 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Register 5Ah Bits 7:0 A23 ~ A16 of Non-Cacheable Area #2 (within 128MBytes) Register 5Bh Bit 7 Fast Gate A20 Emulation Enable 0 : Disable 1 : Enable The sequence to generate A20M# is: write D1h to I/O port 64h followed by I/O write to port 60h with data 00h. When this bit is enabled, the SiS85C501 SiS85C501 responds the cycle by asserting DEVSEL# in slowest timing. Otherwise, the cycle is subtractively decoded by SiS 85C503 85C503, and then is passed to 8042 on the ISA bus. Bit 6 Fast Reset Emulation Enable 0 : Disable 1 : Enable The Fast reset command is I/O write to port 64h with data 1111XXX0b. After the command is issued, the assertion of INIT or CPURST is delayed by 2us or 6us which can be programmed in bit 5, and is held for 25 CPUCLK. Bit 5 Fast Reset Latency Control 0 : 2us 1 : 6us Bit 4 Slow Refresh Enable (1:4) 0 : Normal Refresh 1 : Slow Refresh Bit 3 DRAM Write Push to CAS delay 0 : 2T 1 : 1T Bit 2 De-turbo Hold time 0 : Hold 4 us 1 : Hold 8 us (Every 12 us) Bit 1 De-turbo Switch Enable 0 : Always turbo, ignore the status of De-turbo Switch 1 : De-turbo Switch Enable Bit 0 CAS Driving Current Control Bit 0 ( Please refer to Reg. 5Eh Bit 0 for details) Preliminary V2.0 January 9, 1995 27 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Register 5Ch Bit 7 Latency from ADS# to Monitor Local Memory Status 0 : 3T 1 : 2T Depending on the setting of this bit, the PCI master bridge in the SiS85C501 SiS85C501 may monitor the local memory status from the inside local memory decoder either by the end of T2 or T3. If the CPU initiates a PCI cycle, it is determined to be converted to PCI side from this point. Specifically, BRDY# is always returned to CPU one CPUCLK later if the CTPPB is not full, for post memory write cycles. Thus, this bit also affects the CPU to PCI Post write speed. When it is set to 0, the Post write rate is 5T for each double word. When it is set to 1, the rate is 4T per double word. For a Qword PCI memory write, the post write rate is 7T(bit7=1), or 8T(bit7=0). Bit 6 Enable Refresh Cycle when CPU is hold 0 : Disable 1 : Enable Bit 5 Enable Snoop Filter 0 : Disable 1 : Enable Bit 4 CAS# Pulse Width in PCI master write cycle 0 : 1T 1 : 2T Bit 3 Latency from the disarming of "Full" to the assertion of BRDY# for the pending CPU to PCI write cycle 0 : 1T 1 : 2T Bit 2 Selection of KWE# synchronization 0 : KWE# is synchronized with ACLK (Recommended) 1 : KWE# is synchronized with CPUCLK Bit 1 L2 Tag Length 0 : 8 bits 1 : 7 bits Bit 0 Memory Parity Enable/Disable 0: Enable parity error detection (default value) 1: Disable parity error detection Preliminary V2.0 January 9, 1995 28 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Register 5Dh PCI Control Register Bits 7:6 PCI Clock Frequency Selection 00 : PCICLK=CPUCLK/2 01 : PCICLK=CPUCLK/1.5 10 : Reserved 11 : PCICLK=14MHz Bit 5 Maximum Burstable Address Range in PCI master cycles 0 : 512 Bytes 1 : 1 KBytes This bit defines the maximum bursting length for each FRAME# asserting. Bit 4 Latency from Reading L2/DRAM to the assertion of TRDY# in PCI master read cycles 0 : 1T 1 : 2T Bit 3 Latency from Packing one Qword into PTMPB to the assertion of CAS#(or KWE#) 0 : 1T 1 : 2T This latency is reserved for the Post write data propagating onto MD bus, and also for the parity generation so that minimum set up time for MD data to CAS# will not be violated. Bit 2 Latency from TRDY# to BRDY# in CPU read/write PCI slave cycles 0 : 2 CPUCLKs 1 : 3 CPUCLKs Bit 1 CPU-to-PCI burst memory write Enable 0 : Disable 1 : Enable Bit 0 CPU-to-PCI post memory write Enable 0 : Disable 1 : Enable Preliminary V2.0 January 9, 1995 29 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Register 5Eh This register mainly defines the enable bits for the events monitored by System Standby timer. If any monitored event occurs during the programmed time, the System standby timer will be reloaded and starts to count down again. Bit 7 Programmable 10-bit I/O port When set, any I/O access to the address will cause the timer be reloaded. The address is defined in Registers 66h and 67h. Bit 6 Programmable 16-bit I/O port When set, any I/O access to the address will cause the timer be reloaded. The address is defined in Registers 6Dh and 6Eh. Bit 5 Hard Disk port When set, any I/O access to the Hard Disk ports ( 1F0-1F7h or 3F6h) will cause the timer be reloaded. Bit 4 Serial port When set, any I/O access to the Serial Ports ( 2F8-2FFh, 3F8-3FFh, 2E8-2EFh or 3E8-3EFh) will cause the timer be reloaded. Bit 3 Parallel port When set, any I/O access to the Parallel ports ( 278-27Fh, 378-37Fh or 3BC3BEh) will cause the timer be reloaded. Bit 2 HOLD When set, any event from the ISA master or the PCI Local Master will cause the timer be reloaded. Bit 1 IRQ1-15 IRQ1-15, NMI When set, any event from the IRQ1-15 IRQ1-15 or NMI will cause the timer be reloaded. Bit 0 CAS Driving Current Control Bit 1 Register 5B bit 0 and 5E bit 0 are used to control CAS driving current. Register 5B bit 0 Register 5E bit 0 Minimum Current 0 0 8mA (default) 1 0 4mA 0 1 12mA 1 1 8mA Register 5Fh Bits 7:6 Bits 5:0 Bit 7 Define the events monitored by the Monitor standby timer Define the events to break the Monitor and System standby state. IRQ 1-15, NMI Preliminary V2.0 January 9, 1995 30 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset When set, any event from the IRQ1-15 IRQ1-15 or NMI will cause the Monitor standby timer be reloaded. Bit 6 HOLD When set, any event from the ISA master or the PCI local master will cause the Monitor standby timer be reloaded. Bit 5 IRQ 1-15, NMI When enabled, any event from the IRQ1-15 IRQ1-15 or NMI will bring the Monitor back to the Normal state from the Standby state. Bit 4 HOLD When enabled, any event from the ISA master or the PCI local master will bring the Monitor back to the Normal state from the Standby state. Bit 3 IRQ 1-15, NMI When enabled, any event from the IRQ1-15 IRQ1-15 or NMI will de-assert the STPCLK#. Bit 2 HOLD When enabled, any event from the ISA master or the PCI local master will deassert the STPCLK#. Bit 1 INIT When enabled, an event from the INIT will de-assert the STPCLK#. Bit 0 Reserved (must be '0') Register 60h Bit 7 Reserved. It should be written with 0. Bit 6 Reserved. It should be written with 0. Bit 5 STPCLK# Enable When set, writing a '1' to bit 3 of Register 60h will cause the STPCLK# to become active. This bit can be cleared. Bit 4 Throttling Enable When set, writing a '1' to bit 3 of Register 60h will cause the STPCLK# throttling state to become active. The throttling function can be disabled by clearing this bit. Bit 3 STPCLK# Control When this bit is set, the STPCLK# will be asserted or the Throttling function will be enabled depending on bits 5 and 4. If both bits 5 and 4 are enabled, the system will do the throttling function. Preliminary V2.0 January 9, 1995 31 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Bit 2 Break Switch Enable When set, the break switch can be used to force the system to enter the Standby state. Bit 1 APM SMI When Register 68h bit 0 is enabled, and a '1' is written to this bit, an SMI is generated. It is used by the software controlled SMI function like APM. This bit should be cleared at the end of the SMI handler. Bit 0 Register 61h Reserved. STPCLK# Assertion Timer Bits 7:0 Bits 7-0 define the period of the STPCLK# assertion time when the STPCLK# enable bit is set. The timer will not start to count until the Stop Grant Special Cycle is received. The timer slot is 35 us. Register 62h STPCLK# De-assertion Timer Bits 7:0 Bits 7-0 define the period of the STPCLK# de-assertion time when the STPCLK# enable bit is set. The timer starts to count when the STPCLK# assertion timer expires. When these two registers are read, the current values are returned. Register 63h Bits 7:0 System Standby Timer The register defines the duration of the System Standby Timer. When the System Standby Timer expires, the system enters System Standby State. If any non-masked event occurs before the timer expires, the timer is reloaded with programmed number and the timer starts counting down again. Register 64h Bits 7:0 SMRAM mapping address. Correspond to Host address A[27:20]. This register together with register 65h define SMRAM location. SMRAM location can either be set to a non-shadow, non-cacheable location by selecting E segment as defined in register 65h or be implemented through logical address remap scheme. Logical address remap is done through comparing the upper 11 bits of access address with the address bits defined in register 64h and 65h. If addresses are compared equal and SRAM area selection has been set to either A Preliminary V2.0 January 9, 1995 32 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset or B segment, then access is remapped into an A or B segment access. The SMRAM mapping address should be set up by BIOS during the POST process and the SMI service routine is also moved into the SMRAM area during this process. When the system is in the SMM mode or the SMRAM access control bit is enabled, any access to SMRAM area will be redirected as defined by these two registers. Note: The SMRAM mapping address defines 1MB granularity and the logical address must not set to the first 1MB memory area. Register 65h Bits 7:5 SMRAM area selection 000 : E0000h-E7FFFh 100 : A0000h-A7FFFh 010 : A0000h-AFFFFh 110 : B0000h-B7FFFh 001 : B0000h-BFFFFh others : reserved The SMRAM area is non-cacheable, and non-shadowed. E0000h-E7FFFh is a physical and logical address space. The other selections can be used to relocate the SMRAM from the pre-defined area (as defined in registers 64h and 65h) during SMM. Bit 4 SMRAM access control 1: When set, the SMRAM area can be used. This bit can be set whenever it is necessary to access the SMRAM area. It is cleared after the access is finished. 0: The SMRAM area can only be accessed during the SMI handler. Bit 3 FLUSH# (De-turbo mode), ADSC# selection (pin 13) 0: ADSC# 1: FLUSH# (De-turbo mode) Bits 2:0 Bits 2-0 correspond to Host Address A[30:28]. Register 66h Bit 7 Reserved (must be '0') Bits 6:5 Define the time slot of the Monitor Standby timer 00 : 6.6 seconds 01 : 0.84 seconds 10 : 13.3 milli-seconds 11 : 1.6 milli-seconds Preliminary V2.0 January 9, 1995 33 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Bits 4:2 Programmable 10-bit I/O port address mask bits 000 : No mask 001 : A0 masked 010 : A1-A0 masked 011 : A2-A0 masked 100 : A3-A0 masked 101 : A4-A0 masked 110 : A5-A0 masked 111 : A6-A0 masked Bits 1:0 Programmable 10-bit I/O port address bits A1, A0. Bits 1:0 correspond to the address bits A1 and A0. Register 67h Bits 7:0 Bits 7:0 define the programmable 10-bit I/O port address bits A[9:2]. Register 68h This register defines the enable status of the devices in SMM. The bits 6:2 are set when the devices are in standby state and cleared when the respective devices are in normal state. Bit 7 System Standby SMI enable When no non-masked event occurs during the programmed duration of the system standby timer, the timer expires. If this bit is enabled, the SMI# is generated and the system enters the System Standby state. Bit 6 Programmable 10-bit I/O port wake up SMI enable When set, any I/O access to this port will be monitored to generate the SMI# to wake up this I/O port from the standby state to the Normal state. This bit is enabled only when the I/O port is in the Standby state. Bit 5 Programmable 16-bit I/O port wake up SMI enable When set, any I/O access to this port will be monitored to generate the SMI# to wake up this I/O port from the standby state to the Normal state. This bit is enabled only when the I/O port is in the Standby state. Preliminary V2.0 January 9, 1995 34 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Bit 4 Serial ports wake up SMI enable When set, any I/O access to the serial ports will be monitored to generate the SMI# to wake up the serial ports from the standby state to the Normal state. This bit is enabled only when the serial ports are in the Standby state. Bit 3 Parallel ports wake up SMI enable When set, any I/O access to the parallel ports will be monitored to generate the SMI# to wake up the parallel ports from the standby state to the Normal state. This bit is enabled only when the parallel ports are in the Standby state. Bit 2 Hard Disk port SMI enable When set, any I/O access to the hard disk port will be monitored to generate the SMI# to wake up the hard disk from the standby state to the Normal state. This bit is enabled only when the hard disk port is in the Standby state. Bit 1 Break Switch SMI enable When set, the break switch can be pressed to generate the SMI# for the system to enter the Standby state. Bit 0 Software SMI enable When set, an I/O write to register 60h bit 1 will generate an SMI. Register 69h This register defines the SMI request status. If the respective SMI enable bit is set, each specific event will cause the respective bit to be set. The asserted bit should be cleared at the end of the SMI handler. Bit 7 System standby SMI request This bit is set when the system standby timer expires. Bit 6 Programmable 10-bit I/O port wake up request This bit is set when there is an I/O access to the port. Bit 5 Programmable 16-bit I/O port wake up request This bit is set when there is an I/O access to the port. Bit 4 Serial ports wake up request This bit is set when the serial ports are accessed. Bit 3 Parallel ports wake up request This bit is set when the parallel ports are accessed. Bit 2 Hard Disk port wake up request This bit is set when the hard disk port is accessed. Bit 1 Break Switch SMI request Preliminary V2.0 January 9, 1995 35 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset This bit is set when the break switch is pressed. Bit 0 Software SMI request This bit is set when an I/O write to the bit 1 of register 60h. Register 6Ah Bit 7 Monitor Standby SMI enable 0 : Disable 1 : Enable When there is no access from the IRQ1-15 IRQ1-15, HOLD and NMI during the programmed time of the Monitor Standby Timer, the timer expires. If this bit is set, an SMI is generated to bring the Monitor to the standby state. Bit 6 Monitor Standby SMI request This bit is set when the Monitor Standby Timer expires. This bit should be cleared at the end of the SMI handler. Bit 5 Monitor wake up SMI enable When set, any event from the IRQ1-15 IRQ1-15, HOLD or NMI will be monitored to generate the SMI# to wake up the monitor from the standby state to the normal state. Bit 4 Monitor wake up request This bit is set when there is an event from the IRQ1-15 IRQ1-15, HOLD or NMI, and the Monitor is in the standby state. Bit 3 Throttling wake up SMI request This bit is set when there is any unmasked event from the NMI, INIT, IRQ1-15 IRQ1-15, or HOLD when the system is in the throttling state. Bit 2 Throttling wake up SMI enable When set, any unmasked event from the NMI, INIT, IRQ1-15 IRQ1-15, or HOLD will cause an SMI to be generated to bring the system back to the Normal state from the throttling state. Bit 1 System wake up SMI enable When set, any unmasked event from the NMI, INIT, IRQ1-15 IRQ1-15, or HOLD will cause an SMI to be generated to bring the system back to the Normal state from the standby state. Preliminary V2.0 January 9, 1995 36 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Bit 0 System wake up SMI request This bit is set when there is any unmasked event from the NMI, INIT, IRQ1-15 IRQ1-15, or HOLD when the system is in the standby state. Register 6Bh Monitor Standby timer - Low byte Bits 7:0 Bits 7:0 define the low byte of the Monitor standby timer. It is a count-down timer and the time slot is programmable for 6.6s, 0.84s, 13.3 ms or 1.6ms. The value programmed to this register is loaded when the timer is enabled and the timer starts counting down. The timer is reloaded when an event from the IRQ1-15 IRQ1-15, HOLD or NMI occurs before the timer expires. When this register is read, the current value is returned. Register 6Ch Monitor Standby timer - High byte Bits 7:0 Bits 7:0 define the high byte of the Monitor standby timer. Register 6Dh Programmable 16-bit I/O port - Low byte Bits 7:0 Bits 7:0 define the low byte of the Programmable 16-bit I/O port. Register 6Eh Programmable 16-bit I/O port - High byte Bits 7:0 Bits 7:0 define the high byte of the Programmable 16-bit I/O port. Register 6Fh This register except bit 7 mainly defines the events monitored by the System Standby timer. If any unmasked event occurs before the timer expires, the System Standby Timer will be reloaded and the timer starts to count down again. Bit 7 Return Bus to CPU after SIOREQ# is Serviced 0 : Disable 1 : Enable Bit 6 SMOUT It is reserved for the application circuit. Bit 5 A0000h - AFFFFh or B0000 B0000 - BFFFFh Address trap When set, any memory access to the address range will cause the timer to be reloaded. Bit 4 C0000h - C7FFFh Address trap When set, any memory access to the address range will cause the timer to be reloaded. Preliminary V2.0 January 9, 1995 37 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Bit 3 3B0-3BFh, 3C0-3CFh, 3D0-3DFh Address trap When set, any I/O access to the I/O addresses will cause the timer to be reloaded. Bit 2 Secondary Drive port When set, any I/O access to the secondary drive port (170-17Fh, 320-32Fh, 3F7h) will reload the system standby timer. Bits 1:0 System Standby Timer Slot 11 : 8.85 milli seconds 10 : 70 milli seconds 01 : 1.1 seconds 00 : 9 seconds Preliminary V2.0 January 9, 1995 38 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 2.11 Pin Assignment and Description 2.11.1 Pin Assignment CALE KA3/KA4Y KA4X KWY1# KWY0# VSS KWX1# KWX0# KREY#/COE1# KREX#/COE0# VSS ADSV# ADSC#/FLUSH# VDD3 TA0 TA1 TA2 TA3 TA4 TA5 TA6 TA7 ALTWE# ALT TAGWE# CAS0# CAS1# CAS2# CAS3# CPUCLK VSS CAS4# CAS5# CAS6# CAS7# ACLK VSS RAS0# RAS1# VDD RAS2# RAS3# VSS RAMW# MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 1 156 155 5 10 145 15 135 25 35 85C501 85C501 130 125 120 40 45 Preliminary V2.0 January 9, 1995 110 105 39 HA3 HA30 HA29 HA31 HA28 HA25 HA26 HA27 HA22 HA24 HA21 HA23 SMI# INIT STPCLK# VDD3 OSC VSS KBRST#/BREAK# TURBO VDD W AKEUP0 W AKEUP1 SMOUT PCIRST# SIOREQ# SIOGNT# PCICLKI VSS SERR# PAR PLCOK# FRAME# IRDY# TRDY# DEVSEL# STOP# GNT3# GNT2# GNT1# GNT0# REQ3# REQ2# REQ1# REQ0# C/BE3# C/BE2# VSS C/BE1# C/BE0# AD31 AD30 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 2.11.2 Pin Listing ( # means active low) 1=CALE 2=KA3/KA4Y 3=KA4X 4=KWY1# 5=KWY0# 6=VSS 7=KWX1# 8=KWX0# 9=KREY#/COE1# 10=KREX#/COE0# 11=VSS 12=ADSV# 13=ADSC#/FLUSH# 14=VDD3 15=TA0 16=TA1 17=TA2 18=TA3 19=TA4 20=TA5 21=TA6 22=TA7 23=ALTWE# 24=ALT 25=TAGWE# 26=CAS0# 27=CAS1# 28=CAS2# 29=CAS3# 30=CPUCLK 31=VSS 32=CAS4# 33=CAS5# 34=CAS6# 35=CAS7# 36=ACLK 37=VSS 38=RAS0# 39=RAS1# 40=VDD 41=RAS2# 42=RAS3# 43=VSS 44=RAMW# 45=MA0 46=MA1 47=MA2 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V Preliminary V2.0 January 9, 1995 48=MA3 49=MA4 50=MA5 51=MA6 52=MA7 53=MA8 54=MA9 55=MA10 56=MA11 57=HGDW 58=ADLE# 59=CPPOP 60=CPPSH 61=CMPOP 62=CMPSH 63=MDLE 64=PRDLE 65=ADOE 66=PARITY# 67=HCR0 68=VSS 69=HCR1 70=HLDA 71=PCICLKO 72=AD0 73=AD1 74=AD2 75=AD3 76=AD4 77=AD5 78=AD6 79=AD7 80=VDD 81=AD8 82=AD9 83=PWRGD 84=VSS 85=AD10 86=AD11 87=AD12 88=AD13 89=AD14 90=AD15 91=AD16 92=AD17 93=AD18 94=AD19 40 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 95=AD20 96=AD21 97=AD22 98=AD23 99=AD24 100=AD25 101=AD26 102=AD27 103=AD28 104=AD29 105=AD30 106=AD31 107=C/BE0# 108=C/BE1# 109=VSS 110=C/BE2# 111=C/BE3# 112=REQ0# 113=REQ1# 114=REQ2# 115=REQ3# 116=GNT0# 117=GNT1# 118=GNT2# 119=GNT3# 120=STOP# 121=DEVSEL# 122=TRDY# 123=IRDY# 124=FRAME# 125=PLOCK# 126=PAR 127=SERR# 128=VSS 129=PCICLKI 130=SIOGNT# 131=SIOREQ# 132=PCIRST# 133=SMOUT 134=WAKEUP1 135=WAKEUP0 136=VDD 137=TURBO 138=KBRST#/BREAK# 139=VSS 140=OSC 141=VDD3 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V/3.3V Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 142=STPCLK# 143=INIT 144=SMI# 145=HA23 146=HA21 147=HA24 148=HA22 149=HA27 150=HA26 151=HA25 152=HA28 153=HA31 154=HA29 155=HA30 156=HA3 157=HA4 158=HA6 159=HA7 160=HA8 161=HA10 162=HA5 163=HA11 164=HA9 165=HA12 166=HA13 167=HA14 168=HA15 169=HA16 170=HA17 171=HA18 172=HA19 173=HA20 174=CPURST 175=HBE7# Preliminary V2.0 January 9, 1995 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 176=HBE6# 177=HBE5# 178=HBE4# 179=HBE3# 180=HBE2# 181=HBE1# 182=HBE0# 183=VSS 184=A20M# 185=W/R# 186=HITM# 187=EADS# 188=D/C# 189=ADS# 190=CPUHLDA 191=SMIACT# 192=CPUHOLD 193=NA# 194=BRDY# 195=VSS 196=KEN# 197=CACHE# 198=M/IO# 199=VDD3 200=KCE0#/CWE0# 201=KCE1#/CWE1# 202=KCE2#/CWE2# 203=KCE3#/CWE3# 204=VSS 205=KCE4#/CWE4# 206=KCE5#/CWE5# 207=KCE6#/CWE6# 208=KCE7#/CWE7# 41 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 2.11.3 Pin Description Host Interface Pin No. 145-173 Symbol HA[31:3] Type I/O 175-182 HBE[7:0]# I 189 ADS# I 198 M/IO# I 185 W/R# I/O 188 D/C# I 194 BRDY# O 192 CPUHOLD O 190 CPUHLDA I 186 HITM# I 184 A20M# O Preliminary V2.0 January 9, 1995 42 Function The CPU Address is driven by the CPU during CPU bus cycles. The 85C501 85C501 forwards it to either the DRAM or the PCI bus depending on the address range. The address bus is driven by the 85C501 85C501 during bus master cycles. CPU Byte Enables indicate which byte lanes on the CPU data bus carry valid data during the current bus cycle. HBE7# indicates that the most significant byte of the data bus is valid while HBE0# indicates that the least significant byte of the data bus is valid. Address Status is driven by the CPU to indicate the start of a CPU bus cycle. Memory I/O definition is an input to indicate an I/O cycle when low, or a memory cycle when high. Write/Read from the CPU indicates whether the current cycle is a write or read access. It is an output during the PCI master cycles. Data/Code is used to indicate whether the current cycle is a data or code access. Burst Ready indicates that data presented are valid during a burst cycle. CPU Hold Request is used to request the control of the CPU bus. CPUHLDA will be asserted by the CPU after completing the current bus cycle. CPU Hold Acknowledge comes from the CPU in response to a CPUHOLD request. It is active high and remains driven during bus hold period. CPUHLDA indicates that the CPU has given the bus to another bus master. Hit Modified indicates the snoop cycle hits a modified line in the L1 cache of the CPU. A20 Mask is the fast A20GATE A20GATE output to the CPU. It remains high during power up and CPU reset period. It forces A20 to go low when active. Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 196 KEN# O 197 CACHE# I 187 EADS# O 193 NA# O 174 CPURST O 143 INIT O 144 SMI# O 191 SMIACT# I 142 STPCLK# The CPU Cache Enable pin is used when the current cycle is cacheable to the L1 cache of the CPU. It is an active low signal asserted by the 85C501 85C501 during cacheable cycles. The Cache pin indicates an internally cacheable read cycle or a burst write-back cycle. If this pin is driven inactive during a read cycle, the CPU will not cache the returned data, regardless of the state of the KEN# pin. The EADS# is driven to indicate that a valid external address has been driven to the CPU address pins to be used for an inquire cycle. Next Address is driven for one clock to the CPU to indicate that the memory system is ready to accept a new bus cycle. Although the data transfer for the current cycle has not yet completed, the CPU may drive a internally pending cycle out to the address bus two clocks after NA# is asserted. Reset CPU is an active high output to reset the CPU. The Initialization output forces the CPU to begin execution in a known state. The CPU state after INIT is the same as the state after CPURST except that the internal caches, model specific registers, and floating point registers retain the values they had prior to INIT. System Management Interrupt is used to indicate the occurrence of system management events. It is connected directly to the CPU SMI# input. The SMIACT# pin is used as the SMI acknowledgment input from the CPU to indicate that the SMI is being acknowledged and the processor is operating in System Management Mode(SMM). Stop Clock indicates a stop clock request to the CPU. O Cache & DRAM Interface Preliminary V2.0 January 9, 1995 43 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Pin No. 22-15 24 Symbol TA[7:0] ALT Type I/O I/O 3 KA4X O 2 KA3/KA4Y O 10 KREX#/COE0# O 9 KREY#/COE1# O 8,7 KWX0/1# O 5,4 KWY0/1# O 23 ALTWE# O 25 208-205 203-200 TAGWE# KCE[7:0]# / CWE[7:0]# O O 1 CALE O 13 ADSC#/FLUSH# O Preliminary V2.0 January 9, 1995 44 Function TAG RAM data bus lines. The ALT bit indicates the particular line in the 2nd level cache contains modified data. Cache address bit 4 for even bank in an interleaved cache configuration. Cache address bit 4 for odd bank, or Cache address bit 3 in non-interleaved mode. Cache Read Enable for even bank of standard SRAM, or Cache Output Enable for burst SRAM. Cache Read Enable for odd bank of standard SRAM, or Cache Output Enable for burst SRAM. When used as COE1#, it is a copy of COE0# for loading consideration. Cache Write Enable for standard SRAM, even bank. Cache Write Enable for standard SRAM, odd bank. The ALTWE# is the write strobe to the ALT RAM. This signal is active low when cache read miss or cache write hit occurs. It is used to update the ALT bit. TAG RAM write enable output. Cache Enable pins for standard SRAM indicate that the corresponding byte is accessed. Cache Write Enable pins for burst SRAM to allow cache data RAM update on a byte-by-byte basis. The CALE controls the external latch between the host address lines and the cache address lines. When high, it allows the CPU address lines to propagate through external latches and onto cache address lines. When low, it is used to latch cache address lines. This pin that can be used as ADSC#, or FLUSH# depends on the BIOS programming. Cache Address Strobe Control causes the burst SRAM to latch the cache address. FLUSH# is asserted during deturbo mode. It is used to force CPU to writeback all modified lines in the data cache and invalidate CPU internal cache. Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 12 ADSV# O Cache Advance is driven to burst SRAM to advance the internal two-bit address counter to the next address of burst sequence. The RAS[3:0]# are used to latch the row address on the MA bus. Each RAS[3:0]# corresponds to one DRAM row. The CAS[7:0]# are used to latch the column address on the MA bus. Each CAS[7:0]# corresponds to one byte of the eight-byte wide array. RAM Write is an active low output signal to enable local DRAM writes. The MA[11:0] provide the row and column address to the DRAM. 42,41 39,38 RAS[3:0]# O 35-32 29-26 CAS[7:0]# O 44 RAMW# O 56-45 MA[11:0] O Pin No. 111,110 108,107 Symbol C/BE[3:0]# Type I/O 106-85 82,81 79-72 AD[31:0] I/O PCI Interface Preliminary V2.0 January 9, 1995 45 Function PCI Bus Command and Byte Enables define the PCI command during the address phase of a PCI cycle, and the PCI byte enables during the data phases. C/BE[3:0]# are outputs when the 85C501 85C501 is a PCI bus master and inputs when it is a PCI slave. PCI Address /Data Bus In address phase: 1. When the 85C501 85C501 is a PCI bus master, AD[31:0] are output signals. 2. When the 85C501 85C501 is a PCI target, AD[31:0] are input signals. In data phase: 1. When the 85C501 85C501 is a bus master of a memory read/write cycle, AD[31:0] are floating. 2. When the 85C501 85C501 is a bus master of a configuration or an I/O cycle, AD[31:0] are input signals in a read cycle, and output signals in a write cycle. 3. When the 85C501 85C501 is a target of a memory read/write cycle, AD[31:0] are floating. 4. When the 85C501 85C501 is a target of a configuration or an I/O cycle, AD[31:0] are output signals in a read cycle, and input signals in a write cycle. Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 124 FRAME# I/O 123 IRDY# I/O 122 TRDY# I/O 121 DEVSEL# I/O 120 STOP# I/O 126 PAR O 127 SERR# O 115-112 REQ[3:0]# I 119-116 GNT[3:0]# O Preliminary V2.0 January 9, 1995 FRAME# is an output when the 85C501 85C501 is a PCI bus master. The 85C501 85C501 drives FRAME# to indicate the beginning and duration of an access. When the 85C501 85C501 is a PCI slave, FRAME# is an input signal. IRDY# is an output when the 85C501 85C501 is a PCI bus master. The assertion of IRDY# indicates the current PCI bus master's ability to complete the current data phase of the transaction. For a read cycle, IRDY# indicates that the PCI bus master is prepared to accept the read data on the following rising edge of the PCI clock. For a write cycle, IRDY# indicates that the bus master has driven valid data on the PCI bus. When the 85C501 85C501 is a PCI slave, IRDY# is an input. TRDY# is an output when the 85C501 85C501 is a PCI slave. The assertion of TRDY# indicates the target agent's ability to complete the current data phase of the transaction. For a read cycle, TRDY# indicates that the target has driven valid data onto the PCI bus. For a write cycle, TRDY# indicates that the target is prepared to accept data from the PCI bus. When the 85C501 85C501 is a PCI master, it is an input. The 85C501 85C501 drives DEVSEL# based on the DRAM address range being accessed by a PCI bus master or if the current configuration cycle is to the 85C501 85C501. As an input it indicates if any device has responded to current PCI bus cycle initiated by the 85C501 85C501. STOP# indicates that the bus master must start terminating its current PCI bus cycle at the next clock edge and release control of the PCI bus. STOP# is used for disconnect, retry, and targetabort sequences on the PCI bus. Parity is an even parity generated across AD[31:0] and C/BE[3:0]#. System error is an open drain output for reporting errors. PCI Bus Request is used to indicate to the PCI bus arbiter that an agent requires use of the PCI bus. PCI Bus Grant indicates to an agent that access to the PCI bus has been granted. 46 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 125 PLOCK# I 71 PCICLKO O 129 PCICLKI I 132 PCIRST# PCI Lock indicates an exclusive bus operation that may require multiple transactions to complete. When PLOCK# is sampled asserted at the beginning of a PCI cycle, the 85C501 85C501 considers itself a locked resource and remains in the locked state until PLOCK# is sampled negated on a new PCI cycle. The PCICLKO provides the clock for the 85C501/502/503 85C501/502/503 and PCI devices of the system. The PCICLKI input provides the fundamental timing and the internal operating frequency for the 85C501 85C501. It runs at the same frequency and skew of the PCI local bus. It should be generated from the PCICLKO signal through a clock distribution buffer. The PCI Reset forces the PCI devices to a known state. O Data Buffer Control Interface Pin No. 69,67 Symbol HCR[1:0] Type O 58 ADLE# O 65 ADOE O 63 MDLE O Preliminary V2.0 January 9, 1995 47 Function Host Data Bus Controls. These signals are driven by the 85C501 85C501 and are used to control the 85C502 85C502 HD[63:0] bus. They are defined as: 00: 502 floats HD bus 01: 502 drives FFFFFFFF to HD bus 10: 502 drives data from AD bus to HD bus 11: 502 drives data from MD bus to HD bus AD Bus Data Latch Enable. This signal has the following functions: 1. Latch HD or MD data into the PCI read buffer (PRMB) 2. Latch AD data into CPU read PCI buffer on the rising edge of PCICLKI. 3. Latch AD data into PCI posted write buffer (PTMPB) on the rising edge of PCICLKI. AD Bus Output Enable. This signal is used to enable the 85C502 85C502 to drive PCI AD bus. It is asserted in CPU writes PCI or PCI master reads local memory cycles. Memory Data Read Latch Enable. This signal latches the data on the MD bus when negated. Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 60 CPPSH O Push CPU to PCI Posted Write Data into the 85C502 85C502. The data on the HD bus is latched into the 85C502 85C502 CPU to PCI Posted Write Buffer on CPPSH rising edge. The edge also increases the write pointer to the next available loading entry in the buffer. On the rising edge of CPPOP, the read pointer is changed to address the next available reading location. When this signal is asserted, the data on the HD bus is written into the CPU to memory posted write buffer (CTMPB) on the rising edge of CPUCLK, and the write pointer is also changed to address the next available location. Pop CPU to Memory Posted Write Buffer Data. When this signal is asserted, the read pointer of the CPU to Memory Posted Write Buffer is increased on the rising edge of CPUCLK. This signal latches the current output entry in the CPU to PCI Posted Write Buffer into the prelatch in the 85C502 85C502. The output of the prelatch is driven onto the PCI AD bus. In a PCI master cycle, PRDLE is asserted when PCI master is reading data from the secondary cache, or when PCI master is writing data to the local memory. High Double Word Indicator. The signal is driven high when: (1) a high DW from the HD bus is written into CPU to PCI Posted Write Buffer, (2) the CPU reads a high DW from PCI bus, (3) PCI master writes a high DW to local memory, (4) PCI master reads a high DW from local memory. Parity Bit, from the 85C502 85C502. 59 CPPOP O 62 CMPSH O 61 CMPOP O 64 PRDLE O 57 HGDW O 66 PARITY# I Pin No. 70 133 Symbol HLDA SMOUT Type O O 131 SIOREQ# I Others Preliminary V2.0 January 9, 1995 48 Function Hold Acknowledge. System Management Output control pin. It is used to control peripheral's power, clock.etc. SIO Request from the 85C503 85C503 to request the PCI bus. Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 130 SIOGNT# O 138 KBRST#/BREA K# I 137 TURBO I 134 WAKEUP1 I 135 WAKEUP0 I 140 OSC I 36 ACLK I 30 CPUCLK I 83 PWRGD SIO Grant. When asserted, SIOGNT# indicates that the PCI arbiter has granted use of the bus to the 85C503 85C503. When the break switch enable bit is set, the KBRST# will be disabled. A signal from the break switch will cause the system enters the standby state. The pulse width of the BREAK# must greater than 4 CPUCLK. Turbo input pin. The system is in De-turbo mode when this pin is low. When this input is activated, the 85C501 85C501 will reload the system standby timer. If it is inactive and the system standby timer expires, the system will enter system standby state. During the system standby state, if this input becomes active, the system will wake up from standby state and return back to normal state. When this input is activated, the 85C501 85C501 will reload the monitor standby timer. If it is inactive and the monitor standby timer expires, the system will enter monitor standby state. During the monitor standby state, if this input becomes active, the system will wake up from standby state and return back to normal state. OSC is a clock input for the timer and the DMA controller. It is 14.318MHz and is generated by an external oscillator. Advanced CPU clock should lead the CPUCLK by 3 to 7 ns to provide the clock for the 85C501 85C501 internal cache control logic. CPU clock input runs at the frequency and skew equal to those of the CPU clock. Power Good is a power on reset and push button reset input. +5V DC power +3.3V DC power in 3V system +5V DC power in 5V system Ground I 40,80,136 VDD 14,141 VDD3 199 6,11,31,37 VSS 43,68,84 109,128 139,183 195,204 Preliminary V2.0 January 9, 1995 49 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 2.12 Timing Diagram Cache Burst Read Hit Cycle 3-1-1-1 CPUCLK ADS# BRDY# KA4X KA4Y KREX# KREY# 501cbr1 Cache Burst Read Hit Cycle 4-2-2-2 CPUCLK ADS# BRDY# KA4X KA4Y KREX# KREY# 501cbr2 Cache Burst Read Hit Cycle 5-3-3-3 CPUCLK ADS# BRDY# KA4X KA4Y KREX# KREY# 501cbr3 Preliminary V2.0 January 9, 1995 50 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Cache Burst Write Hit Cycle 3-1-1-1 CPUCLK ADS# BRDY# KA4X KA4Y KWEX# KWEY# 501cbw1 Cache Burst Write Hit Cycle 4-2-2-2 CPUCLK ADS# BRDY# KA4X KA4Y KWEX# KWEY# 501cbw2 Cache Burst Write Hit Cycle 5-3-3-3 CPUCLK ADS# BRDY# KA4X KA4Y KWEX# KWEY# 501cbw3 Preliminary V2.0 January 9, 1995 51 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Cache Miss Update Cycle Only (WT or WB , Dirty=0,Cache:4-2-2-2 & DRAM:7-4-4-4 ) CPUCLK ADS# CAS# RAS# BRDY# NA# MA[11:0] CALE KWEX# KWEY# KA4X KA4Y 501cmu1 Preliminary V2.0 January 9, 1995 52 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Cache Miss,Concurrent Write Back Cycle ( Cache:4-2-2-2 & DRAM:7-4-4-4 ) CPUCLK ADS# CAS# RAS# BRDY# CMPSH NA# MA[11:0] CMPOP CALE KWEX# KWEY# KA4X KA4Y RAMW# KREX# KREY# 501cmwb1 Preliminary V2.0 January 9, 1995 53 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset DRAM Burst Read - Page Start 7-4-4-4 CPUCLK ADS# CAS# RAS# BRDY# MDLE NA# MA[11:0] CALE KWEX# KA3 KA4X 501dbr1 DRAM Burst Read - Page Start 8-5-5-5 CPUCLK ADS# CAS# RAS# BRDY# MDLE NA# MA[11:0] CALE KWEX# KA3 KA4X 501DBR2 501DBR2 Preliminary V2.0 January 9, 1995 54 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset DRAM Burst Write CPUCLK ADS# CAS# RAS# BRDY# CMPSH MA[11:0] CMPOP KWEX# KA3 KA4X 501dbw1 85C501 85C501 Configuration Register Read Cycle CPUCLK HA[31:3] HBE[7:0]# 0CF8 0CFC F0 CF ADS# BRDY# HGDW PCICLK FRAME# IRDY# DEVSEL# TRDY# PRDLE ADOE ADLE# Preliminary V2.0 January 9, 1995 55 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 85C501 85C501 Configuration Register Write Cycle CPUCLK HA[31:3] HBE[7:0]# 0CF8 0CFC F0 CF ADS# BRDY# HGDW PCICLK FRAME# IRDY# DEVSEL# TRDY# PRDLE ADOE ADLE# 501crw Preliminary V2.0 January 9, 1995 56 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset CPU Read PCI Slave CPUCLK HA[31:3] HBE[7:0]# ADS# BRDY# HGDW read low DW read high DW PCICLK AD[31:0] addr. C/BE[3:0]# 6 6 addr. data 0 6 data 0 FRAME# IRDY# DEVSEL# TRDY# PRDLE ADLE# HCR[1:0] 0 2 0 501crp Preliminary V2.0 January 9, 1995 57 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset CPU to PCI Psoted Write Cycle CPUCLK HA[31:3] HBE[7:0]# XXXXX800 XXXXX800 F0 XXXXX808 XXXXX808 0F 00 ADS# BRDY# HGDW PCICLK AD[31:0] C/BE[3:0]# XXX800 XXX800 DATA 7 0 FRAME# IRDY# DEVSEL# 1 wait state TRDY# ADOE CPPSH CPPOP PRDLE 501ctpp PCI master Reads a High DW from L2,NA=SAL PCICLK FRAME# IRDY# DEVSEL# KRE# TRDY# HGDW ADOE ADLE# 501prl2 Preliminary V2.0 January 9, 1995 58 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset PCI master Writes a QW to L2/DRAM, NA=SAL, Page Hit CPUCLK PCICLK FRAME# IRDY# DEVSEL# EADS# KWE#/CAS# TRDY# HGDW HCR[1:0] 00 10 00 ADLE# CALE PRDLE RAMW# 501prl2d Preliminary V2.0 January 9, 1995 59 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Snoop Hit a Modified line in L1, L2 miss PCI Master Writes the Last Two QW in the 16 Line Boundary, Disconnect CPUCLK PCICLK FRAME# IRDY# DEVSEL# TRDY# STOP# EADS# HITM# CPUHOLD CPUHLDA ADS# BRDY# RAS# CAS# MA row address 1st QW 2nd QW 3rd QW 4th QW 3rd QW 4th QW column addr RAMW# PRDLE ADLE# HGDW CALE 501snp2 Preliminary V2.0 January 9, 1995 60 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset Snoop Hit a Modified line in L1, Hit L2, PCI Master Read One Line from L2 CPUCLK PCICLK FRAME# IRDY# DEVSEL# TRDY# EADS# HITM# CPUHOLD CPUHLDA HA[31:3] 00100000 CPU drive 00100000 00100000 00100008 00100010 00100018 ADS# BRDY# KWE# KRE# ADOE PRDLE ADLE# HGDW 501snp1 Preliminary V2.0 January 9, 1995 61 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 2.13 Electrical Characteristics 2.13.1 Absolute Maximum Ratings Parameter Min Max Ambient operating temperature 0 70 Unit oC Storage temperature -40 125 oC Input voltage -0.3 5.5 V Output voltage -0.5 5.5 V 1 W Power Dissipation Note: Stress above these listed may cause permanent damage to device. Functional operation of this device should be restricted to the conditions described under operating conditions. 2.13.2 DC Characteristics TA = 0 - 70 oC, VSS = 0V , VDD=5V+5%, VDD3=3.3V+5% Symbol VIL1 VIH1 VIL2 VIH2 VT1VT1+ VH1 VOL1 VOH1 VOL2 VOH2 IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 IOL4 IOH4 IOL5 Parameter Input low voltage Input High Voltage Input low voltage Input high voltage Schmitt Trigger Threshod Voltage Falling Edge Schmitt Trigger Threshold Voltage Rising Edge Hysteresis Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Current Output High Current Output Low Current Output High Current Output Low Current Output High Current Output Low Current Output High Current Output Low Current Preliminary V2.0 January 9, 1995 Min -0.3 2.2 -0.3 2.2 1.6 Unit V V V V V Condition Note 1, VDD3=3.3V Note 1 Note 2 Note 2 Note 3 3.2 V Note 3 1.2 0.45 0.3 Max 0.8 VDD3+0.3V 0.8 VDD+0.3 V V V V V mA mA mA mA mA mA mA mA mA Note 3 Note 4 Note 4 Note 5 Note 5 Note 6 Note 6 Note 7 Note 7 Note 8 Note 8 Note 9 Note 9 Note 10 2.4 2.0 4 4 6 6 4,8,12 4,8,12 16 16 4 62 0.4 VDD3 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset IOH5 IIH IIL CIN COUT CI/O ICC3 Output High Current Input Leakage Current Input Leakage Current Input Capacitance Output Capacitance I/O Capacitance Power Supply Current of VDD3 1 mA mA mA pF pF pF mA +10 -10 12 12 12 40 Note 10, Note 11 Fc=1 Mhz Fc=1 Mhz Fc=1 Mhz 3.3V, 66MHz Note: 1. VIL1 and VIH1 apply to the following signals: HA[31:3], W/R#, HBE[7:0]#, HITM#, D/C#, ADS#, CPUHLDA, SMIACT#, CACHE#, M/IO# 2. VIL2 and VIH2 apply to the following signals: TA[7:0], ALT, CPUCLK, ACLK, PARITY#, AD[31:0], C/BE[3:0]#, REQ[3:0]#, STOP#, DEVSEL#, TRDY#, IRDY#, FRAME#, LOCK#, PCICLKI, SIOGNT#, SIOREQ#, WAKEUP[1:0], TURBO, KBRST#, OSC 3. VT1-,VT1+ and VH1 apply to PWRGD 4. VOL1 and VOH1 apply to the following signals: TA[7:0], ALTWE#, ALT, TAGWE#, CAS[7:0]#, RAS[3:0]#, RAMW#, MA[11:0], HGDW, ADLE#, CPPOP, CPPSH, CMPOP, CMPSH, MDLE, PRDLE, ADOE, HCR[1:0], HLDA, PCICLKO, AD[31:0], GNT[3:0]#, STOP#, DEVSEL#, TRDY#, FRAME#, PAR, SERR#, PCIRST#, SMOUT 5. VOL2 and VOH2 apply to the following signals: CALE, KA4Y, KA4X, KWY[1:0]#, KWX[1:0]#, KREX#, KREY#, ADSC#/FLUSH#, ADSV#, STPCLK#, INIT, SMI#, HA[31:3], CPURST, W/R#, A20M#, EADS#, CPUHOLD, NA#, BRDY#, KEN#, KCE[7:0]# 6. IOL1 and IOH1 apply to the following signals: TA[7:0], ALTWE#, ALT, TAGWE#, RAMW#, MA[11:0], HGDW, ADLE#, CPPOP, CPPSH, CMPOP, CMPSH, MDLE, PRDLE, ADOE, HCR[1:0], HLDA, PCICLKO, AD[31:0], C/BE[3:0]#, GNT[3:0]#, PAR, SERR#, PCIRST#, SMOUT, WAKEUP[1:0] 7. IOL2 and IOH2 apply to the following signals: FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#. 8. IOL3 and IOH3 apply to the following signals: CAS[7:0]# 9. IOL4 and IOH4 apply to the following signals: KA4X, KA4Y, KWY[1:0]#, KWX[1:0]#, ADSV#, ADSC#, RAS[3:0]# 10. IOL5 and IOH5 apply to the following signals: CALE, KREY#, KREX#, STPCLK#, INIT, SMI#, HA[31:3], W/R#, EADS#, CPUHOLD, NA#, BRDY#, KEN#, KCE[7:0]#, CPURST, A20M# 11. IOH5 is 1mA in 3.3 system, when in 5V system, the IOH4 is 4mA. Preliminary V2.0 January 9, 1995 63 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 2.13.3 AC Characteristics Symbol T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 Parameter BRDY# Active delay from CPUCLK BRDY# Inactive delay from CPUCLK KEN# Active delay from CPUCLK KEN# Inactive delay from CPUCLK NA# Active delay from CPUCLK NA# Inactive delay from CPUCLK EADS# Active delay from CPUCLK EADS# Inactive delay from CPUCLK CPUHOLD Active delay from CPUCLK CPUHOLD Inactive delay from CPUCLK CPURST Inactive delay from CPUCLK CPURST High Pulse Width KREX#,KREY# Active delay from ACLK KREX#,KREY# Inactive delay from ACLK KWX[0:1]#,KWY[0:1]# Active delay from ACLK KWX[0:1]#,KWY[0:1]# Inactive delay from ACLK KWX[0:1]#,KWY[0:1]# Active delay from CPUCLK KWX[0:1]#,KWY[0:1]# Inactive delay from CPUCLK KCE[7:0]# Active delay from ADS# falling edge KCE[7:0]# Inactive delay from CPUCLK MDLE High Active delay from CPUCLK MDLE High Inactive delay from CPUCLK KA4X,KA4Y Low Valid delay from ACLK KA4X,KA4Y High Valid delay from ACLK KA4X,KA4Y Low Valid delay from CPUCLK In Update Cycle & Write cycle KA4X,KA4Y High Valid delay from CPUCLK In Update Cycle & Write cycle Tag Output Valid delay from CPUCLK In Update Cycle RAS[3:0]# Active delay from CPUCLK RAS[3:0]# Inactive delay from CPUCLK CAS[7:0]# Active delay from CPUCLK CAS[7:0]# Inactive delay from CPUCLK MA[11:0] Low Valid delay from CPUCLK MA[11:0] High Valid delay from CPUCLK MA[11:0] Propagation delay from A[27:3] ALT Output Valid delay from CPUCLK ALTWE#,TAGWE# Active delay from CPUCLK ALTWE#,TAGWE# Inactive delay from CPUCLK A20M# Active delay from CPUCLK A20M# Inactive delay from CPUCLK AD[31:0],C/BE[3:0]# Output valid delay from PCICLKI PRDLE Active delay from PCICLKI DEVSEL#,FRAME#,IRDY#,STOP#,TRDY# Active delay from PCICLKI Preliminary V2.0 January 9, 1995 64 Typ 8 6 7 5 8 6 8 6 8 6 7 25 9 6 8 6 8 6 7 7 5 7 7 6 7 Max 12 9 11 8 12 9 12 9 12 9 11 13 9 12 9 12 9 12 12 8 11 11 9 11 Unit ns ns ns ns ns ns ns ns ns ns ns cpuclk ns ns ns ns ns ns ns ns ns ns ns ns ns CL 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 100pf 100pf 100pf 100pf 100pf 100pf 35pf 35pf 35pf 35pf 100pf 100pf 100pf 6 9 ns 100pf 14 23 ns 35pf 12 9 11 8 12 11 8 10 9 9 9 8 10 18 14 16 12 18 16 12 15 14 14 14 12 15 ns ns ns ns ns ns ns ns ns ns ns ns ns 250pf 250pf 120pf 120pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 50pf 9 10 14 15 ns ns 35pf 50pf Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset T43 T44 T45 T46 T47 T48 T49 T50 T51 T52 T53 T54 T55 T56 T57 T58 T59 T60 T61 T62 T63 T64 T65 T66 T67 T68 T69 T70 T71 T72 T73 T74 T75 T76 T77 T78 T79 T80 T81 T82 T83 DEVSEL#,FRAME#,IRDY#,STOP#,TRDY# Inactive delay from PCICLKI GNT[3:0]#,PAR,SERR#,SIOGNT#,STPCLK# Active delay from PCICLKI GNT[3:0]#,PAR,SERR#,SIOGNT#,STPCLK# Inactive delay from PCICLKI HA[31:3] Drive Output Valid delay from PCICLKI HCR[1:0],HGDW Active delay from CPUCLK HLDA Active delay from CPUCLK HLDA Inactive delay from CPUCLK INIT# Active delay from CPUCLK INIT# Inactive delay from CPUCLK MDLE Active delay from CPUCLK MDLE Inactive delay from CPUCLK PCICLKO,PCIRST Active delay from CPUCLK RAMW# Active delay from CPUCLK RAMW# Inactive delay from CPUCLK SMOUT Active delay from CPUCLK ADSC# Active delay from CPUCLK ADSC# Inactive delay from CPUCLK ADSV# Active delay from CPUCLK ADSV# Inactive delay from CPUCLK CPPSH Active delay from CPUCLK CPPOP Active delay from PCICLK CPPSH Inactive delay from CPUCLK CPPOP Inactive delay from PCICLK ADOE Active delay from PCICLK ADOE Inactive delay from PCICLK ADLE# Active delay from PCICLK ADLE# Inactive delay from PCICLK PCICLKO high time (Divided by 2) PCICLKO low time (Divided by 2) PCICLKO high time (Divided by 1.5) PCICLKO low time (Divided by 1.5) PCICLKO rise time (Divided by 2) PCICLKO fall time (Divided by 2) PCICLKO rise time (Divided by 1.5) PCICLKO fall time (Divided by 1.5) HCR[1:0] fall time to CPUCLK rising HCR[1:0] rise time to CPUCLK rising CALE# Active delay from CPUCLK CALE# Inactive delay from CPUCLK SMI# rise time to CPUCLK rising SMI# fall time to CPUCLK rising 9 14 ns 50pf 10 15 ns 50pf 10 15 ns 50pf 12 7 8 7 7 6 7 6 8 11 8 10 7 6 7 6 4 8 7 10 6 6 6 6 15.2 12.6 12.5 15.8 1.16 0.66 1.06 0.9 4.5 3.7 8 6 7.8 7.8 18 11 12 11 11 9 11 9 12 16 12 15 11 9 11 9 6 12 11 15 9 9 9 9 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 50pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 50pf 35pf 35pf 50pf 90pf 90pf 150pf 150pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 50pf 50pf 50pf 50pf 50pf 50pf 50pf 50pf 35pf 35pf 35pf 35pf 35pf 35pf 12 9 10 10 CPUCLK TR1 TF1 SIGNAL1 Preliminary V2.0 January 9, 1995 65 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset TF1 = T1, T3, T5, T7, T10, T11, T17, T22, T23, T25, T27, T28, T30, T32, T36, T38, T49, T50, T53, T55, T58, T60, T64, T78, T80, T83 TR1 = T2, T4, T6, T8, T9, T18, T20, T21, T24, T26, T27, T29, T31, T33, T35, T37, T39, T47, T48, T51, T52, T54, T56, T57, T59, T61, T62, T79, T81, T82 SIGNAL1 = BRDY#, KEN#, NA#, EADS#, CPUHOLD, CPURST, KWX[0:1]#, KWY[0:1]#, KCE[7:0]#, MDLE, CALE, KA4X, KA4Y, TA[7:0], RAS[3:0]#, CAS[7:0]#, MA[11:0], ALT, ALTWE#, TAGWE#, A20M#, HLDA, INIT#, PCICLKO, PCIRST, RAMW#, SMOUT, ADSC#, ADSV#, GNT[3:0]#, PAR, SERR#, SIOGNT#, STPCLK#, CPPSH ACLK TR2 TF2 SIGNAL2 TF2 = T13, T15, T23 TR2 = T14, T16, T24 SIGNAL2 = KREX#, KREY#, KWX[0:1]#, KWY[0:1]#, KA4X, KA4Y PCICLKI TR3 TF3 SIGNAL3 TF3 = T40, T41,T42, T46, T44, T65, T67, T68 TR3 = T40, T41, T43, T46, T45, T63, T66, T69 SIGNAL3 = AD[31:0], C/BE[3:0], ADLE#, ADOE, PRDLE, DEVSEL#, FRAME#, IRDY#,STOP#, TRDY#, HA[31:3], CPPOP, ADOE, ADLE ADS# T19 KCE[7:0]# Preliminary V2.0 January 9, 1995 66 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset T12 CPURST HA[27:3] MA[11:0] T34 TH4 TR4 PCICLKO TL4 TF4 TH4 = T70,T72 TL4 = T71, T73 TR4 = T74, T76 TF4 = T75, T77 Preliminary V2.0 January 9, 1995 67 Silicon Integrated Systems Corporation Pentium/P54C PCI/ISA Chipset 3 SiS85C502 SiS85C502 3.1 Features · Supports the Full 64-bit Pentium Processor Data Bus · Provides a 64-Bit Interface to DRAM Memory · Provides a 32-bit Interface to PCI · Three Integrated Posted Write Buffers and Two Read Buffers Increase System Performance - 1 level CPU-to-Memory Posted Write Buffer (CTMPB) with 4 QuadWords (QWs) Deep - 4 level CPU-to-PCI Posted Write Buffer (CTPPB) with 4 DoubleWords (DWs) Deep - 1 level PCI-to-Memory Posted Write Buffer (PTMPB) with 1 QW Deep - 1 level Memory-to-CPU Read Buffer (CRMB) with 1 QW Deep - 1 level Memory-to-PCI Read Buffer (PRMB) with 1 QW Deep · Near Zero Wait State Performance on CPU-to-Memory and CPU-to-PCI writes · Operates Synchronously to the 66.7 MHz CPU and 33.3 MHz PCI Clocks · Provides Parity Generation for Memory Writes · 208-Pin PQFP · 0.6 um CMOS Technology 3.2 General Description The SiS85C502 SiS85C502 PCI Local Data Buffer(PLDB) provides a bi-directional data buffering among the 64-bit Host Data Bus, the