SiI/DS-0007-E SiI/AN-0005 QE23QE0 QO23QO0 SiI/AN-0007-A SiI/AN-0008-A - Datasheet Archive

 

PanelLink® Digital Receiver July 1999 General Description Features The SiI151 uses PanelLink Digital technology to support

 

SiI 151 PanelLink® Digital Receiver July 1999 General Description Features The SiI151 uses PanelLink Digital technology to support displays ranging from VGA to SXGA (25-112 MHz) which is ideal for desktop and specialty applications. The SiI151 receiver supports up to true color panels (24 bit/pixel, 16.7M colors) in 1 or 2 pixels/clock mode, and also features an inter-pair skew tolerance up to 1 full input clock cycle. In addition, the receiver data output is time staggered to reduce ground bounce which affects EMI. Since all PanelLink products are designed on scaleable CMOS architecture to support future performance requirements while maintaining the same logical interface, system designers can be assured that the interface will be fixed through a number of technology and performance generations. PanelLink Digital technology simplifies PC design by resolving many of the system level issues associated with high-speed digital design, providing the system designer with a digital interface solution that is quicker to market and lower in cost. · · · · · · SiI151 Pin Diagram QO2 51 25 QE13 QO3 52 24 QE12 OCK_INV EVEN 8-bits GREEN QE14 QE15 OGND OVCC QE16 QE17 DF0 26 27 28 29 30 QE18 QE19 QE20 QE21 PIXS 31 32 33 34 QE23 VCC GND CTL1 CTL2 CTL3 QE22 36 37 38 39 40 41 42 EVEN 8-bits RED 35 OUTPUT CLOCK GPO OVCC ODCK OGND DE VSYNC HSYNC QO0 Functional Block Diagram 43 44 45 46 47 48 49 50 ODD 8-bits BLUE QO1 CONTROLS EXT_RES RX2- QO4 53 23 QE11 QO5 54 22 QE10 RX1+ 55 21 QE9 RX1- Data Recovery CH2 SYNC2 VCR Data Recovery CH1 SYNC1 Channel SYNC SYNC1 VCR Data Recovery CH0 SYNC0 SYNC0 VCR 56 20 CTL3 SYNC2 CTL2 QE8 57 19 OGND OGND 58 18 OVCC QO8 59 17 QE7 QE[23:0] DATA Decoder CTL1 Panel Interface Logic QO[23:0] ODCK DE HSYNC VSYNC SCDT CTL1 CTL2 CTL3 RXC+ RXC- 24 24 PLL VCR DATA QO7 OVCC RX0+ RX0- 60 16 QE6 61 15 QE5 QO11 62 14 QE4 QO12 63 13 QE3 QO13 64 12 QE2 QO14 65 11 QE1 66 10 QE0 VCC 67 9 PDO GND 68 8 SCDT QO16 69 7 STAG_OUT QO17 70 6 71 5 72 4 PIXS QO20 73 3 ST QO21 74 2 PD QO22 75 1 DFO HSYNC GND QO19 VSYNC VCC QO18 89 90 91 92 93 94 95 96 97 98 99 100 AGND RX0+ RX0- AGND RXC+ RXC- AVCC EXT_RES PVCC PGND RESERVED OCK_INV 84 AVCC 88 83 AGND AVCC 82 AVCC 87 81 RX2- AGND 80 RX2+ 86 79 AGND RX1- 78 OVCC 85 77 QO23 RX1+ 76 OGND (Top View) DIFFERNTIAL SIGNAL PLL STAG_OUT ST PWR MANAGEMENT 100-Pin TQFP PDO CONFIG. PINS SiI151 EVEN 8-bits BLUE QO9 QO10 QO15 ODD 8-bits GREEN Termination Control DATA RX2+ QO6 ODD 8-bits RED Scaleable Bandwidth: 25-112 MHz (VGA to SXGA) Low Power: 3.3V core operation & power-down mode High Skew Tolerance: 1 full input clock cycle (9ns at 108 MHz) Time staggered data output for reduced ground bounce Sync Detect: for Plug & Display "Hot Plugging" Cable Distance Support: over 5m with twisted-pair, fiber-optics ready Compliant with DVI 1.0 (DVI is backwards compatible TM with VESA® P&D and DFP) Subject to Change without Notice Silicon Image, Inc. SiI151 SiI/DS-0007-E SiI/DS-0007-E Absolute Maximum Conditions Note: Permanent device damage may occur if absolute maximum conditions are exceeded. Functional operation should be restricted to the conditions described under Normal Operating Conditions. Symbol Parameter Min Typ Max Units VCC Supply Voltage 3.3V -0.3 4.0 V VI Input Voltage -0.3 VCC+ 0.3 V VO Output Voltage -0.3 VCC+ 0.3 V TA Ambient Temperature (with power applied) -25 105 °C TSTG Storage Temperature -40 125 °C PPD Package Power Dissipation 1 W Normal Operating Conditions Symbol Parameter VCC Supply Voltage 1 VCCN Supply Voltage Noise TA Ambient Temperature (with power applied) 1 Note: Guaranteed by design. Min 3.00 Typ 3.3 0 25 Max 3.6 100 70 Units V mVP-P °C DC Digital I/O Specifications Under normal operating conditions unless otherwise specified. Symbol Parameter Conditions VIH High-level Input Voltage VIL Low-level Input Voltage VOH High-level Output Voltage VOL Low-level Output Voltage 1 VCINL Input Clamp Voltage ICL = -18mA 1 VCIPL Input Clamp Voltage ICL = 18mA 1 VCONL Output Clamp Voltage ICL = -18mA 1 VCOPL Output Clamp Voltage ICL = 18mA IOL Output Leakage Current High Impedance 1 Note: Guaranteed by design. Min 2 Typ Max Units V V V V V V V V µA 0.8 2.4 0.4 GND -0.8 IVCC + 0.8 GND -0.8 OVCC + 0.8 10 -10 DC Specifications Under normal operating conditions unless otherwise specified. Symbol Parameter Conditions IOHD Output High Drive VOUT = VOH; Data and Controls ST = 1 ST = 0 IOLD Output Low Drive VOUT = VOL; Data and Controls ST = 1 ST = 0 IOHC ODCK High Drive VOUT = VOH; ST = 1 ST = 0 IOLC ODCK Low Drive VOUT = VOL; ST = 1 ST = 0 VID Differential Input Voltage Single Ended Amplitude 2 IPD Power-down Current ICCR Receiver Supply Current CLOAD= 10pF DCLK=112MHz, 1-pixel/clock mode REXT_SWING = 680 3 Typical Pattern DCLK=112MHz, 1-pixel/clock mode Note: 1 2 3 4 CLOAD = 10pF REXT_SWING = 680 4 Worse Case Pattern Min Typ Max Units 4.2 2.1 8 4 18 9 mA 5.2 2.6 5.5 2.75 11 5.5 mA 8.5 4.2 17 9 37 18 mA 10.4 5.2 75 16 8 23 11 1000 mA 10 mA 215 235 mA 240 265 mA mV Guaranteed by design. The transmitter must be in power-down mode, powered off, or disconnected for the current to be under this maximum. The Typical Pattern contains a gray scale area, checkerboard area, and text. Black and white checkerboard pattern, each checker is two pixel wide. 2 Subject to Change without Notice Silicon Image, Inc. SiI151 SiI/DS-0007-E SiI/DS-0007-E AC Specifications Under normal operating conditions unless otherwise specified. Low drive strength values, when ST=0, are given below. Symbol Parameter Conditions Min Typ Max Units 1 TDPS Intra-Pair (+ to -) Differential Input Skew 112 MHz 360 ps One Pixel / Clock 1 TCCS Channel to Channel Differential Input Skew 112 MHz 6 ns One Pixel / Clock 2,3 TIJIT Worst Case Differential Input Clock Jitter tolerance 465 ps 65 MHz, One Pixel / Clock 112 MHz, One Pixel / Clock 270 DLHT Low-to-High Transition Time CL = 10pF; ST = 1 5.5 Data and Controls CL = 5pF; ST = 0 3.1 ns ODCK CL = 10pF; ST = 1 2.75 CL = 5pF; ST = 0 DHLT High-to-Low Transition Time CL = 10pF; ST = 1 3 Data and Controls CL = 5pF; ST = 0 2.5 ns ODCK CL = 10pF; ST = 1 2 CL = 5pF; ST = 0 4 TSOF Data/Control Setup Time to ODCK falling edge (OCK_INV = 0) CL = 10pF; ST = 1 3 ns 65MHz, 1-pixel/clock, PIXS = 0 CL = 5pF; ST = 0 3 56MHz, 2-pixel/clock, PIXS = 1 CL = 10pF; ST = 1 5 CL = 5pF; ST = 0 3.5 4 THOF Data/Control Hold Time to ODCK falling edge (OCK_INV = 0) CL = 10pF; ST = 1 8 ns 65MHz, 1-pixel/clock, PIXS = 0 CL = 5pF; ST = 0 8 56MHz, 2-pixel/clock, PIXS = 1 CL = 10pF; ST = 1 8 CL = 5pF; ST = 0 7 1 RCIP ODCK Cycle Time (1-pixels/clock) 8.9 50 ns 1 FCIP ODCK Frequency (1-pixel/clock) 20 112 MHz 1 RCIP ODCK Cycle Time (2-pixels/clock) 17.8 100 ns 1 FCIP ODCK Frequency (2-pixel/clock) 10 56 MHz 1,5 RCIH ODCK High Time 65MHz, 1-pixel/clock, PIXS = 0 CL = 10pF; ST = 1 3 ns CL = 5pF; ST = 0 56MHz, 1-pixel/clock, PIXS = 1 CL = 10pF; ST = 1 CL = 5pF; ST = 0 1,5 RCIL ODCK Low Time 65MHz, 1-pixel/clock, PIXS = 0 CL = 10pF; ST = 1 3 ns CL = 5pF; ST = 0 56MHz, 1-pixel/clock, PIXS = 1 CL = 10pF; ST = 1 CL = 5pF; ST = 0 1 TPDL Delay from PD Low to high impedance outputs 10 ns 1 THSC Link disabled (DE inactive) to SCDT low 100 ms 6 Link disabled (Tx power down) to SCDT low 250 1 TFSC Link enabled (DE active) to SCDT high 25 DE edges 1 TST ODCK high to even data output 0.25 RCIP 1 Notes: Guaranteed by design. 2 Jitter defined as per DVI 1.0 Specification, Section 4.6 Jitter Specification. 3 Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electrical Measurement Procedures. 4 The setup and hold timing for the data and controls relative to the ODCK rising edge (OCK_INV=1) is by design the same as the falling edge timing. 5 Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle. 6 Measured when transmitter was powered down (see SiI/AN-0005 SiI/AN-0005 "PanelLink Basic Design/Application Guide," Section 2.4). 3 Subject to Change without Notice Silicon Image, Inc. SiI151 SiI/DS-0007-E SiI/DS-0007-E Timing Diagrams 80% SiI151 80% 10pF 20% 20% DLHT DHLT Figure 1. Digital Output Transition Times RCIP RCIH V IH V IH V IL V IL RCIL Figure 2. Receiver Clock Cycle/High/Low Times RX0 VDIFF=0V RX1 TCCS VDIFF=0V RX2 Figure 3. Channel-to-Channel Skew Timing Output Timing V OH ODCK V OL TSOF QE[23:0]/QO[23:0], DE, HSYNC, VSYNC, CTL[3:1] THOF V OH V OL V OH V OL Figure 4. Output Data, DE, and Control Signals Setup/Hold Times to ODCK Falling Edge PD VIL TPDL QE[23:0]/QO[23:0], DE, VSYNC,HSYNC, CTL[3:1],PLLCK Figure 5. Output Signals Disabled Timing from PD Active 4 Subject to Change without Notice Silicon Image, Inc. SiI151 SiI/DS-0007-E SiI/DS-0007-E Output Timing (continued) THSC DE SCDT TFSC DE SCDT Figure 6. SCDT Timing from DE Inactive/Active Internal ODCK * 2 ODCK DE TST QE[23:0] QO[23:0] FIRST DATA SECOND DATA THIRD DATA FOURTH DATA Figure 7. TFT 2-Pixels/Clock Staggered Output Timing Diagram Output Pin Description Pin Name QE23QE0 QE23QE0 Pin # See SiI151 Pin Diagram Type Out QO23QO0 QO23QO0 See SiI151 Pin Diagram Out ODCK 44 Out DE 46 Out HSYNC VSYNC CTL1 CTL2 CTL3 48 47 40 41 42 Out Out Out Out Out Description Output Even Data[23:0] corresponds to 24-bit pixel data for 1-pixel/clock input mode and to the first 24-bit pixel data for 2-pixels/clock mode. Output data is synchronized with output data clock (ODCK). Refer to the TFT and DSTN Signal Mapping application notes (SiI/AN-0007-A SiI/AN-0007-A and SiI/AN-0008-A SiI/AN-0008-A) which tabulates the relationship between the input data to the transmitter and output data from the receiver. A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. Output Odd Data[23:0] corresponds to the second 24-bit pixel data for 2-pixels/clock mode. During 1-pixel/clock mode, these outputs are driven low. Output data is synchronized with output data clock (ODCK). Refer to the TFT and DSTN Signal Mapping application notes (SiI/AN-0007-A SiI/AN-0007-A and SiI/AN-0008-A SiI/AN-0008-A) which tabulates the relationship between the input data to the transmitter and output data from the receiver. A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. Output Data Clock. A low level on PD or PDO will put the output driver into a high impedance (tri-state) mode. A weak internal pull-down device brings the output to ground. Output Data Enable. This signal qualifies the active data area. A low level on PD or PDO will put the output driver into a high impedance (tri-state) mode. A weak internal pull-down device brings the output to ground. Horizontal Sync input control signal. Vertical Sync input control signal. General output control signal 1. This output is not powered down by PDO. General output control signal 2. General output control signal 3. A low level on PD or PDO will put the output drivers (except CTL1 by PDO) into a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. 5 Subject to Change without Notice Silicon Image, Inc. SiI151 SiI/DS-0007-E SiI/DS-0007-E Configuration Pin Description Pin Name OCK_INV Pin # 100 Type In PIXS 4 In DFO 1 In STAG_OUT 7 In ST 3 Description ODCK Polarity. A low level selects normal ODCK output. A high level (3.3V) selects inverted ODCK output. All other outputs signals are not affected by this pin. They will maintain the same timing no matter the setting of OCK_INV pin. Pixel Select. A low level indicates one pixel (up to 24-bits) per clock mode using QE[23:0]. A high level (3.3V) indicates two pixels (up to 48-bits) per clock mode using QE[23:0] for first pixel and QO[23:0] for second pixel. Output Data Format. This pin controls clock output format. A low level indicates that ODCK runs continuously for TFT panel support. A high level indicates that ODCK is stopped (LOW) when DE is low for DSTN panel support. Refer to the TFT and/or DSTN Signal Mapping application notes (SiI/AN-0007-A SiI/AN-0007-A and SiI/AN-0008-A SiI/AN-0008-A) for a table on TFT or DSTN panel support. A high level selects normal simultaneous outputs on all odd and even data lines. A low level selects staggered output drive. This function is only available in 2-pixels per clock mode. Output Drive. A high level selects HIGH output drive strength. A low level selects LOW output drive strength. In Power Management Pin Description Pin Name SCDT Pin # 8 Type Out PDO 9 In PD 2 In Description Sync Detect. A high level is outputted when DE is actively toggling indicating that the link is alive. A low level is outputted when DE is inactive, indicating the link is down. Can be connected to PDO to power down the outputs when DE is not detected. The SCDT output itself, however, remains in the active mode at all times. Output Driver Power Down (active low). A high level indicates normal operation. A low level puts all the output drivers only (except SCDT and CTL1) into a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. PDO is a sub-set of the PD description. The chip is not in power-down mode with this pin. There is an internal pull-up resistor that defaults the chip to normal operation if left unconnected. SCDT and CTL1 are not tri-stated by this pin. Power Down (active low). A high level (3.3V) indicates normal operation and a low level indicates power down mode. During power down mode, all output buffers are disabled and brought low, all analog logic is powered down, and all inputs are disabled. Differential Signal Data Pin Description Pin Name RX0+ RX0RX1+ RX1RX2+ RX2RXC+ RXCEXT_RES Pin # 90 91 85 86 80 81 93 94 96 Type Analog Analog Analog Analog Analog Analog Analog Analog Analog Description TMDS Low Voltage Differential Signal input data pairs. TMDS Low Voltage Differential Signal input data pairs. Impedance Matching Control. Resistor value should be ten times the characteristic impedance of the cable. In the common case of 50 transmission line, an external 500 resistor must be connected between AVCC and this pin. Reserved Pin Description Pin Name RESERVED Pin # 99 Type In Description Must be tied high for normal operation. Power and Ground Pin Description Pin Name VCC GND OVCC OGND AVCC AGND PVCC PGND Pin # 6,38,67 5,39,68 18,29,43,57,78 19,28,45,58,76 82,84,88,95 79,83,87,89,92 97 98 Type Power Ground Power Ground Power Ground Power Ground Description Digital Core VCC, must be set to 3.3V. Digital Core GND. Output VCC, must be set to 3.3V. Output GND. Analog VCC must be set to 3.3V. Analog GND. PLL Analog VCC must be set to 3.3V. PLL Analog GND. Application Information To obtain the most updated Application Notes and other useful information for your design application, please visit the Silicon Image web site at www.siimage.com, or contact your local Silicon Image sales office. 6 Subject to Change without Notice Silicon Image, Inc. SiI151 SiI/DS-0007-E SiI/DS-0007-E Package Dimensions 100-pin TQFP Package Dimensions Lead Length 1.00mm Lead Width 0.20mm 100-pin Plastic TQFP Package Height 1.20mm max. SiINNN CT NNN LNNNNN.NLLL XXYY X.XX Footprint 16.00mm Device # Lot # Date Code # SiI Rev. # Body Size 14.00mm 12.00mm Lead Pitch 0.50mm Body Thickness 1.05 mm max. Clearance 0.15mm max. 12.00mm Body Size 14.00mm Footprint 16.00mm Copyright Notice This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or send/transmit any part of this documentation without the express written permission of Silicon Image, Inc. Trademark Acknowledgment PanelLink and the PanelLink Digital Image Logo are registered trademarks of Silicon Image, Inc. Silicon Image, the Silicon Image Logo, and TMDS are trademarks of Silicon Image, Inc. VESA is a registered trademark of Video Electronics Standards Association. All other trademarks are the property of their respective holders. Disclaimer This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the information in this document as necessary. The customer should make sure that they have the most recent data sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Ordering Information Part Number: SiI151CT100 SiI151CT100 © 1999 Silicon Image, Inc. 7/99 SiI /DS-0007-E /DS-0007-E Silicon Image, Inc. 10131 Bubb Road Cupertino, CA 95014 USA Tel: 408-873-3111 Fax: 408-873-0446 E-Mail: salessupport@siimage.com Web: www.siimage.com www.panellink.com 7 Subject to Change without Notice