-48-V Vishay Siliconix 3-W High-Voltage Switchmode Regulator FEATURES · 10- to

Vishay Siliconix 3-W High-Voltage Switchmode Regulator FEATURES · 10- to 70-V Input Range · Current-Mode Control

Si9100 Vishay Siliconix 3-W High-Voltage Switchmode Regulator FEATURES · 10- to 70-V Input Range · Current-Mode Control · On-Chip 150-V, 5- MOSFET Switch · Reference Selection Si9100 - ±1% · High Efficiency Operation (> 80%) · Internal Start-Up Circuit · Internal Oscillator (1 MHz) · SHUTDOWN and RESET DESCRIPTION The Si9100 high-voltage switchmode regulators are monolithic BiC/DMOS integrated circuits which contain most of the components necessary to implement high-efficiency dcto-dc converters up to 3 watts. They can either be operated from a low-voltage dc supply, or directly from a 10- to 70-V unregulated dc power source. The Si9100 may be used with an appropriate transformer to implement most single-ended isolated power converter topologies (i.e., flyback and forward), or by using a level shift circuit can generate a +5-V or a -5-V non-isolated output from a -48-V -48-V source. The Si9100 is available in 14-pin plastic DIP and 20-pin PLCC packages. It is specified over the industrial, D suffix (-40 to 85°C) temperature ranges. FUNCTIONAL BLOCK DIAGRAM Note: Figures in parenthesis represent pin numbers for 20-pin package. Applications information may also be obtained via FaxBack, request documents #70576 and #70584. FaxBack 408-970-5600, request 70000 www.siliconix.com S-60752-Rev. F, 05-Apr-99 1 Si9100 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85°C Voltages Referenced to -VIN (VCC < +VIN + 0.3 V) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 V Power Dissipation (Package)a 14-Pin Plastic DIP (J Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . 750 mW 20-Pin PLCC (N Suffix)c. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400 mW VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 V ID (Peak) (Note: 300 µs pulse, 2% duty cycle). . . . . . . . . . . . . . 2.5 A ID (rms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 mA Logic Inputs (RESET, SHUTDOWN, OSC IN) . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V Linear Inputs (FEEDBACK, SOURCE). . . . . . . . . . . . . . .-0.3 V to 7 V HV Pre-Regulator Input Current (continuous). . . . . . . . . . . . . . . 3 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 125°C Thermal Impedance (JA) 14-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167°C/W 20-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90°C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 6 mW/°C above 25°C c. Derate 11.2 mW/°C above 25°C RECOMMENDED OPERATING RANGE Voltages Referenced to -VIN ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 k to 1 M VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9.5 V to 13.5 V Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 7 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 V to 70 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC fOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 kHz to 1 MHz SPECIFICATIONSa Limits Test Conditions Unless Otherwise Specified Parameter Symbol DISCHARGE = -VIN = 0 V VCC = 10 V, +VIN = 48 V RBIAS = 390 k , ROSC = 330 k D Suffix -40 to 85°C Tempb Minc Typd Maxc Unit Room 3.92 4.0 4.08 V Room 15 30 45 k Room 70 100 130 µA 0.5 1.0 mV/°C Reference Output Voltage VR Output Impedancee ZOUT Short Circuit Current ISREF Temperature Stabilitye OSC IN = - VIN (OSC Disabled) RL = 10 M TREF VREF = -VIN Full Oscillator Maximum Frequencye fMAX Initial Accuracy fOSC Voltage Stability f/f Temperature Coefficiente ROSC = 0 Room 1 3 ROSC = 330 kf Room 80 100 120 ROSC = 150 kf Room 160 200 240 f/f = f(13.5 V) - f(9.5 V)/f(9.5 V) Room 10 15 % Full 200 500 ppm/°C 4.00 4.04 V TOSC MHz kHz Error Amplifier Feedback Input Voltage VFB FB Tied to COMP OSC In = -VIN (OSC Disabled) Room OSC IN = -VIN, VFB = 4 V Room 25 500 nA Room ±15 ±40 mV Input BIAS Current IFB Input OFFSET Voltage VOS Open Loop Voltage Gaine AVOL Unity Gain Bandwidthe BW Dynamic Output Impedancee Output Current Power Supply Rejection S-60752-Rev. F, 05-Apr-99 2 OSC IN = - VIN, (OSC Disabled) ZOUT IOUT PSRR Room 3.96 80 dB Room 60 1 MHz Room 1000 2000 SOURCE (VFB = 3.4 V) Room -2.0 -1.4 SINK (VFB = 4.5 V) Room 0.12 0.15 OSC IN = - VIN, (OSC Disabled) Room 50 70 mA dB FaxBack 408-970-5600, request 70000 www.siliconix.com Si9100 Vishay Siliconix SPECIFICATIONSa Limits Test Conditions Unless Otherwise Specified Parameter Symbol DISCHARGE = -VIN = 0 V VCC = 10 V, +VIN = 48 V RBIAS = 390 k , ROSC = 330 k D Suffix -40 to 85°C Tempb Minc Typd Maxc Unit 1.0 1.2 1.4 V 100 200 ns Current Limit VSOURCE RL = 100 from DRAIN to VCC VFB = 0 V Room td RL = 100 from DRAIN to VCC VSOURCE = 1.5 V, See Figure 1. . Room Input Voltage +VIN IIN = 10 µA Room 70 V Input Leakage Current 10 µA Threshold Voltage Delay to Outpute Pre-regulator/Start-up +IIN VCC 10 V Room Pre-Regulator Start-Up Current ISTART Pulse Width 300 µs VCC = VUVLO Room 8 15 VCC Pre-Regulator Turn-Off Threshold Voltage VREG IPRE-REGULATOR = 10 µA Room 7.8 9.4 9.7 Undervoltage Lockout VUVLO RL = 100 from DRAIN to VCC See Detailed Description Room 7.0 8.8 9.2 VREG -VUVLO VDELTA Room 0.3 0.6 ICC Room 0.45 0.6 1.0 mA IBIAS Room 10 15 20 µA 50 100 mA V Supply Supply Current Bias Current Logic SHUTDOWN Delaye tSD SHUTDOWN Pulse Widthe tSW RESET Pulse Widthe tRW VSOURCE = -VIN, See Figure 2. Room Room 50 Room 50 25 ns See Figure 3. Latching Pulse Widthe SHUTDOWN and RESET Low tLW Room Input Low Voltage VIL Room Input High Voltage VIH Room Input Current Input Voltage High IIH VIN = 10 V Room Input Current Input Voltage Low IIL VIN = 0 V Room -35 -25 V(BR)DSS VSOURCE = SHUTDOWN = 0 V IDRAIN = 100 µA Full 150 180 rDS(on) VSOURCE = 0 V IDRAIN = 100 mA Room Drain Off Leakage Current IDSS VSOURCE = SHUTDOWN = 0 V VDRAIN = 100 V Room Drain Capacitance CDS VSOURCE = SHUTDOWN = 0 V Room 2.0 8.0 1 V 5 µA MOSFET Switch Breakdown Voltage Drain-Source On Resistanceg V 5 10 3 µA 35 pF Notes a. Refer to PROCESS information. OPTION FLOWCHART for additional d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. b. Room = 25°C, Full = as determined by the operating temperature suffix. e. Guaranteed by design, not subject to production test. c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. g. Temperature coefficient of rDS(on) is 0.75% per °C, typical. FaxBack 408-970-5600, request 70000 www.siliconix.com f. CSTRAY Pin 8 = 5 pF S-60752-Rev. F, 05-Apr-99 3 Si9100 Vishay Siliconix TIMING WAVEFORMS FIGURE 1. FIGURE 2. FIGURE 3. TYPICAL CHARACTERISTICS FIGURE 4. S-60752-Rev. F, 05-Apr-99 4 FIGURE 5. FaxBack 408-970-5600, request 70000 www.siliconix.com Si9100 Vishay Siliconix PIN CONFIGURATIONS PIN DESCRIPTION Pin Function 14-Pin DIP 20-Pin PLCC* BIAS 1 2 +VIN 2 3 DRAIN 3 5 SOURCE 4 7 -VIN 5 8 VCC 6 9 OSC OUT 7 10 OSC IN 8 11 DISCHARGE 9 12 VREF 10 14 SHUTDOWN 11 16 RESET 12 17 COMP 13 18 FB 14 20 *Pins 1, 4, 6, 13, 15, and 19 = N/C DETAILED DESCRIPTION Pre-Regulator/Start-Up Section Due to the low quiescent current requirement of the Si9100 control circuitry, bias power can be supplied from the unregulated input power source, from an external regulated low-voltage supply, or from an auxiliary "bootstrap" winding on the output inductor or transformer. When power is first applied during start-up, +VIN will draw a constant current. The magnitude of this current is determined by a high-voltage depletion MOSFET device which is connected between +VIN and VCC. This start-up circuitry provides initial power to the IC by charging an external bypass capacitance connected to the VCC pin. The constant current is disabled when VCC exceeds 9.4 V. If VCC is not forced to exceed the 9.4-V threshold, then VCC will be regulated to a nominal value of 9.4 V by the pre-regulator circuit. As the supply voltage rises toward the normal operating conditions, an internal undervoltage (UV) lockout circuit keeps the output MOSFET disabled until VCC exceeds the undervoltage lockout threshold (typically 8.8 V). This guarantees that the control logic will be functioning properly FaxBack 408-970-5600, request 70000 www.siliconix.com and that sufficient gate drive voltage is available before the MOSFET turns on. The design of the IC is such that the undervoltage lockout threshold will not exceed the preregulator turn-off voltage. Power dissipation can be minimized by providing an external power source to VCC such that the constant current source is always disabled. Note: During start-up or when VCC drops below 9.4V the start-up circuit is capable of sourcing up to 20 mA. This may lead to a high level of power dissipation in the IC (for a 48-V input, approximately 1 W). Excessive start-up time caused by external loading of the VCC supply can result in device damage. Figure 4 gives the typical pre-regulator current at start-up as a function of input voltage. BIAS To properly set the bias for the Si9100, a 390-k resistor should be tied from BIAS to -VIN. This determines the magnitude of bias current in all of the analog sections and the pull-up current for the SHUTDOWN and RESET pins. The current flowing in the bias resistor is nominally 15 µA. S-60752-Rev. F, 05-Apr-99 5 Si9100 Vishay Siliconix Reference Section The reference section of the Si9100 consists of a temperature compensated buried zener and trimmable divider network. The output of the reference section is connected internally to the non-inverting input of the error amplifier. Nominal reference output voltage is 4 V. During the reference trimming procedure the error amplifier is connected for unity gain in order to compensate for the input offset voltage in the error amplifier. The output impedance of the reference section has been purposely made high so that a low impedance external voltage source can be used to override the internal voltage source, if desired, without otherwise altering the performance of the device. Error Amplifier Closed-loop regulation is provided by the error amplifier, which is intended for use with "around-the-amplifier" compensation. A MOS differential input stage provides for low input leakage current. The noninverting input to the error amplifier (VREF) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground. Remote synchronization is accomplished by capacitive coupling of a positive SYNC pulse into the OSC IN terminal. For a 5-V pulse amplitude and 0.5-µs pulse width, typical values would be 100 pF in series with 3 k to OSC IN. SHUTDOWN and RESET SHUTDOWN and RESET are intended for overriding the output MOSFET switch via external control logic. The two inputs are fed through a latch preceding the output switch. Depending on the logic state of RESET, SHUTDOWN can be either a latched or unlatched input. The output is off whenever SHUTDOWN is low. By simultaneously having SHUTDOWN and RESET low, the latch is set and SHUTDOWN has no effect until RESET goes high. The truth table for these inputs is given in Table 1. Both pins have internal current source pull-ups and should be left disconnected when not in use. An added feature of the current sources is the ability to connect a capacitor and an open-collector driver to the SHUTDOWN or RESET pins to provide variable shutdown time. TABLE 1. Truth Table for the SHUTDOWN and RESET Pins SHUTDOWN RESET Output H H Normal Operation Oscillator Section H The oscillator consists of a ring of CMOS inverters, capacitors, and a capacitor discharge switch. Frequency is set by an external resistor between the OSC IN and OSC OUT pins. (See Figure 5 for details of resistor value vs. frequency.) The DISCHARGE pin should be tied to -VIN for normal internal oscillator operation. A frequency divider in the logic section limits switch duty cycle to 50% by locking the switching frequency to one half of the oscillator frequency. L S-60752-Rev. F, 05-Apr-99 6 L Normal Operation (No Change) H Off (Not Latched) L Off (Latched) L Off (Latched, No Change) Output Switch The output switch is a 5- , 150-V lateral DMOS device. Like discrete MOSFETs, the switch contains an intrinsic body-drain diode. However, the body contact in the Si9100 is connected internally to -VIN and is independent of the SOURCE. FaxBack 408-970-5600, request 70000 www.siliconix.com Si9100 Vishay Siliconix APPLICATIONS FIGURE 6. Buck-Boost, Non-Isolated 1-W Supply FIGURE 7. Non-Isolated 1-W Supply (Buck) FaxBack 408-970-5600, request 70000 www.siliconix.com S-60752-Rev. F, 05-Apr-99 7