Si6925ADQ - Datasheet Archive

 

Vishay Siliconix Dual N-Channel 2.5-V (G-S) MOSFET CHARACTERISTICS · N-Channel Vertical DMOS · Macro Model

 

SPICE Device Model Si6925ADQ Si6925ADQ Vishay Siliconix Dual N-Channel 2.5-V (G-S) MOSFET CHARACTERISTICS · N-Channel Vertical DMOS · Macro Model (Subcircuit Model) · Level 3 MOS · Apply for both Linear and Switching Application · Accurate over the -55 to 125°C Temperature Range · Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125°C temperature ranges under the pulsed 0 to 5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 72663 23-May-04 www.vishay.com 1 SPICE Device Model Si6925ADQ Si6925ADQ Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Symbol Test Conditions Simulated Data VGS(th) VDS = VGS, ID = 250 µA 1.1 ID(on) VDS = 5 V, VGS = 4.5 V 80 VGS = 4.5 V, ID = 3.9 A 0.036 0.035 rDS(on) VGS = 3 V, ID = 3.5 A 0.043 0.042 VGS = 2.5 V, ID = 3 A Parameter Measured Data 0.052 0.050 gfs VDS = 10 V, ID = 3.9 A 15 14 S VSD IS = 1 A, VGS = 0 V 0.78 0.75 V 4 4 VDS = 6 V, VGS = 4.5 V, ID = 3.9 A 0.90 0.90 1 1 Unit Static Gate Threshold Voltage On-State Drain Current a Drain-Source On-State Resistancea Forward Transconductancea Forward Voltage a V A Dynamicb Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) 52 40 tr 28 50 25 20 8 10 Rise Time Turn-Off Delay Time Fall Time td(off) tf VDD = 6 V, RL = 6 ID 1 A, VGEN = 4.5 V, RG = 6 nC ns Notes a. Pulse test; pulse width 300 µs, duty cycle 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 72663 23-May-04 SPICE Device Model Si6925ADQ Si6925ADQ Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 72663 23-May-04 www.vishay.com 3