Si4336DY - Datasheet Archive

 

Vishay Siliconix N-Channel 30-V (D-S) MOSFET CHARACTERISTICS · N-Channel Vertical DMOS · Macro Model (Model

 

SPICE Device Model Si4336DY Si4336DY Vishay Siliconix N-Channel 30-V (D-S) MOSFET CHARACTERISTICS · N-Channel Vertical DMOS · Macro Model (Model Subcircuit) · Level 3 MOS · Apply for both Linear and Switching Application · Accurate over the -55 to 125°C Temperature Range · Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit mode is extracted and optimized over the -55 to 125°C temperature ranges under the pulsed 0-to-10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 72536 c www.vishay.com 1 SPICE Device Model Si4336DY Si4336DY Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Simulated Data Measured Data VGS(th) VDS = VGS, ID = 250µA 1.9 ID(on) VDS 5V, VGS = 10V 1882 VGS = 10V, ID = 25A 0.0024 0.0026 VGS = 4.5V, ID = 22A 0.0033 0.0033 Unit Static Gate Threshold Voltage On-State Drain Current a Drain-Source On-State Resistancea rDS(on) V A Forward Transconductancea gfs VDS = 15V, ID = 25A 95 110 Forward Voltagea VSD IS = 2.9A, VGS = 0 V 0.83 0.72 37 32 16.5 16.5 V b Dynamic Total Gate Charge Gate-Source Charge Qg Qgs VDS = 15V, VGS = 4.5V, ID = 20A Gate-Drain Charge Qgd 8.5 8.5 Turn-On Delay Time td(on) 22 24 13 16 70 90 55 nC 32 Rise Time Turn-Off Delay Time Fall Time tr td(off) tf VDD = 15V, RL = 15 ID 1A, VGEN = 10V, RG = 6 ns Notes a. Pulse test; pulse width 300 µs, duty cycle 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 72536 24-Sep-03 SPICE Device Model Si4336DY Si4336DY Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 72536 24-Sep-03 www.vishay.com 3