Si3456DV - Datasheet Archive

 

Vishay Siliconix N-Channel 30-V (D-S) MOSFET CHARACTERISTICS · N-Channel Vertical DMOS · Macro Model (Subcircuit

 

SPICE Device Model Si3456DV Si3456DV Vishay Siliconix N-Channel 30-V (D-S) MOSFET CHARACTERISTICS · N-Channel Vertical DMOS · Macro Model (Subcircuit Model) · Level 3 MOS · Apply for both Linear and Switching Application · Accurate over the -55 to 125°C Temperature Range · Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125°C temperature ranges under the pulsed 0-to-5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70509 07-May-01 www.vishay.com 1 SPICE Device Model Si3456DV Si3456DV Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Typical Unit VGS(th) ID(on) VDS = VGS, ID = 250 µA 2.1 V VDS = 5 V, VGS = 10 V 125 A VGS = 10 V, ID = 5.1 A 0.037 VGS = 4.5 V, ID = 4.3 A 0.051 Static Gate Threshold Voltage a On-State Drain Current a Drain-Source On-State Resistance rDS(on) a Forward Transconductance gfs Diode Forward Voltage VDS = 10 V, ID = 5.1 A 12 S VSD a Dynamic IS = 1.7 A, VGS = 0 V 0.87 V VDS = 15 V, VGS = 10 V, ID = 5.1 A 2.8 b b Total Gate Charge Qg Gate-Source Chargeb Qgs Gate-Drain Chargeb Qgd 1.6 Turn-On Delay Timeb td(on) 10 Rise Timeb Turn-Off Delay Timeb tr td(off) b Fall Time trr VDD = 15 V, RL = 15 ID 1 A, VGEN = 10 V, RG = 6 tf Source-Drain Reverse Recovery Time 11 nC 11 21 ns 30 IF = 1.7 A, di/dt = 100 A/µs 61 Notes a. Pulse test; pulse width 300 µs, duty cycle 2% b. Guaranteed by design, not subject to production testing www.vishay.com 2 Document Number: 71509 07-May-01 SPICE Device Model Si3456DV Si3456DV Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 70509 07-May-01 www.vishay.com 3