Si3210/11/12 Si3210-DS111 211/S Si3210/Si3211/Si3212 TSSOP-38 2N2222 - Datasheet Archive

 

P R O S LI CTM P R O G R A M M A B L E CMO S SL IC /C O D E C W I T H R I N G I N G / B A T T E R Y V O L TA G E G E N E R A T I

 

S i 3 2 1 0 / S i 3 2 11 / S i 3 2 1 2 P R O S LI CTM P R O G R A M M A B L E CMO S SL IC /C O D E C W I T H R I N G I N G / B A T T E R Y V O L TA G E G E N E R A T I O N Applications ro S Programmable Constant Current Feed (20­41 mA) Programmable Loop Closure and Ring Trip Thresholds with Debouncing Loop or Ground Start Operation and Polarity Battery Reversal Continuous Line Voltage and Current Monitoring DTMF Decoder Dual Tone Generator SPI and PCM Bus Digital Interfaces with Programmable Interrupt for Control and Data 3.3 V or 5 V Operation Multiple Loopback Modes for Testing Pulse Metering FSK Caller ID Generation P Performs all BORSCHT Functions Ideal for Short Loop Applications (5 REN at 2 kft, 3 REN at 4 kft) Low Voltage CMOS Package: 38-Pin TSSOP Compliant with Relevant LSSGR and CCITT Specifications Battery Voltage Generated Dynamically with On-Chip DC-DC Converter Controller (Si3210 only) 5 REN Ringing Generator Programmable Frequency, Amplitude, Waveshape, and Cadence Programmable AC Impedance A-Law/µ-Law, Linear PCM Companding On-Hook Transmission LI C Features Ordering Information See page 118. Pin Assignments Si3210/11/12 Si3210/11/12 CS INT PCLK DRX Terminal Adaptors Cable Telephony PBX/Key Systems Wireless Local Loop Voice Over IP Integrated Access Devices DTX FSYNC RESET Description SDCH/DIO1 The ProSLICTM is a low-voltage CMOS device that integrates SLIC, codec, and battery generation functionality into a complete analog telephone interface. The device is ideal for short loop applications such as terminal adaptors, cable telephony, and wireless local loop. The ProSLIC is powered with a single 3.3 V or 5 V supply. The Si3210 generates battery voltages dynamically using a software programmable dc-dc converter from a 3.3 V to 35 V supply; negative high-voltage supplies are not needed. All high voltage functions are performed locally with a few low cost discrete components. The device is available in a 38-pin TSSOP and interfaces directly to standard SPI and PCM bus digital interfaces. SDCL/DIO2 VDDA1 IREF CAPP QGND CAPM STIPDC SRINGDC STIPE SVBAT Functional Block Diagram INT RESET SRINGE SDO PCM Interface Expan sio n D RX FSYNC PCL K DTMF Deco de Co mpression DTX SCLK SDI SDO SDITHRU DCDRV/DCSW DCFF/DOUT TEST GNDD VDDD ITIPN ITIPP VDDA2 IRINGP IRINGN IGMP GNDA IGMN SRINGAC STIPAC Patents pending L ine Status Co ntrol Interface SDI 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 Si3210/11/12 Si3210/11/12 CS SCL K 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PLL Preliminary Rev. 1.11 9/01 G ain/ Atte nuation/ Filter Tone G ene rator G ain/ Atte nua tion / Filter TIP A/D Progra m Hybrid D/A L ine Fe ed Co ntrol Low C ost Extern al Discretes ZS RING DC-D C Co nverter Co ntrolle r (Si3210 o nly) Copyright © 2001 by Silicon Laboratories Si3210-DS111 Si3210-DS111 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si 3210/ Si3 211/S 211/S i32 12 2 Preliminary Rev. 1.11 Si3210/Si3211/Si3212 Si3210/Si3211/Si3212 TA B L E O F C O N T E N TS Section Page Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linefeed Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Voltage Generation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Metering Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTMF Decoding (Si3210 and Si3211 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si3210/11/12 Si3210/11/12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline: 38-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preliminary Rev. 1.11 4 21 21 27 30 33 37 38 39 42 42 42 43 46 47 50 108 108 110 111 112 113 115 118 119 122 3 Si 3210/ Si3 211/S 211/S i32 12 Electrical Specifications Table 1. Absolute Maximum Ratings and Thermal Information* Parameter DC Supply Voltage Symbol Value Unit VDDD, VDDA1, V DDA2 ­0.5 to 6.0 V IIN ±10 mA VIND ­0.3 to (VDDD + 0.3) V 2000 V TA ­40 to 100 °C TSTG ­40 to 150 °C JA 50 °C/W Input Current, Digital Input Pins Digital Input Voltage ESD, Si3210/11/12 Si3210/11/12 (Human Body Model) Operating Temperature Range Storage Temperature Range TSSOP-38 TSSOP-38 Thermal Resistance, Typical *Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Recommended Operating Conditions Symbol Test Condition Min* Typ Max* Unit Ambient Temperature TA K-grade 0 25 70 oC Ambient Temperature TA B-grade ­40 25 85 o 3.13 3.3/5.0 5.25 Parameter Si3210/11/12 Si3210/11/12 Supply Voltage VDDD,VDDA1 ,VDDA2 C V *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 oC unless otherwise stated. Product specifications are only guaranteed when the typical application circuit (including component tolerances) is used. 4 Preliminary Rev. 1.11 Si3210/Si3211/Si3212 Si3210/Si3211/Si3212 Table 3. AC Characteristics (VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70°C for K-Grade, ­40 to 85°C for B-Grade) Parameter Test Condition Min Typ Max Unit THD = 1.5% 2.5 - - VPK 2-wire ­ PCM or PCM ­ 2-wire: 200 Hz­3.4 kHz - - ­45 dB Signal-to-(Noise + Distortion) Ratio2 200 Hz to 3.4 kHz D/A or A/D 8-bit Active off-hook, and OHT, any ZAC Figure 1 - - Audio Tone Generator Signal-to-Distortion Ratio2 0 dBm0, Active off-hook, and OHT, any Zac 45 - - dB - - ­41 dB 2-wire to PCM, 1014 Hz ­0.5 0 0.5 dB PCM to 2-wire, 1014 Hz ­0.5 0 0.5 dB Gain Accuracy Over Frequency Figure 3,4 - - Group Delay Over Frequency Figure 5,6 - - 3 dB to ­37 dB ­0.25 - 0.25 dB ­37 dB to ­50 dB ­0.5 - 0.5 dB ­50 dB to ­60 dB ­1.0 - 1.0 dB at 1000 Hz - 1100 - µs ­6 dB to 6 dB ­0.017 - 0.017 dB All gain settings ­0.25 - 0.25 dB VDDA = VDDA = 3.3/5 V ± 5% ­0.1 - 0.1 dB 2-Wire Return Loss 200 Hz to 3.4 kHz 30 35 - dB Transhybrid Balance 300 Hz to 3.4 kHz 30 - - dB C-Message Weighted - - 15 dBrnC Psophometric Weighted - - ­75 dBmP 3 kHz flat - - 18 dBrn PSRR from VDDA RX and TX, DC to 3.4 kHz 40 - - dB PSRR from VDDD RX and TX, DC to 3.4 kHz 40 - - dB PSRR from VBAT RX and TX, DC to 3.4 kHz 40 - - dB TX/RX Performance Overload Level Single Frequency Distortion 1 Intermodulation Distortion Gain Accuracy2 Gain Tracking 3 Round-Trip Group Delay Gain Step Accuracy Gain Variation with Temperature Gain Variation with Supply 1014 Hz sine wave, reference level ­10 dBm signal level: Noise Performance Idle Channel Noise4 Preliminary Rev. 1.11 5 Si 3210/ Si3 211/S 211/S i32 12 Table 3. AC Characteristics (Continued) (VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70°C for K-Grade, ­40 to 85°C for B-Grade) Parameter Test Condition Min Typ Max Unit 200 Hz to 3.4 kHz, Q1,Q2 150, 1% mismatch 56 60 - dB Q1,Q2 = 60 to 2405 43 60 - dB Q1,Q2 = 300 to 53 60 - dB 40 - - dB - - - 33 17 17 - - - - - - 4 8 8 - - - mA mA mA Longitudinal Performance Longitudinal to Metallic or PCM Balance Metallic to Longitudinal Balance Longitudinal Impedance 8005 200 Hz to 3.4 kHz 200 Hz to 3.4 kHz at TIP or RING Register selectable ETBO/ETBA 00 01 10 Longitudinal Current per Pin Active off-hook 200 Hz to 3.4 kHz Register selectable ETBO/ETBA 00 01 10 Notes: 1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be ­10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified. 2. Analog signal measured as VTIP ­ VRING. Assumes ideal line impedance matching. 3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking performance in the signal range of 3 dB to ­37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate. 4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed ­55 dBm. 5. Assumes normal distribution of betas. 6 Preliminary Rev. 1.11 Si3210/Si3211/Si3212 Si3210/Si3211/Si3212 Figure 1. Transmit and Receive Path SNDR 9 8 7 6 Fundamental Output Power 5 (dBm0) Acceptable Region 4 3 2.6 2 1 0 1 2 3 4 5 6 7 8 9 Fundamental Input Power (dBm0) Figure 2. Overload Compression Performance Preliminary Rev. 1.11 7 Si 3210/ Si3 211/S 211/S i32 12 Typical Response Typical Response Figure 3. Transmit Path Frequency Response 8 Preliminary Rev. 1.11 Si3210/Si3211/Si3212 Si3210/Si3211/Si3212 Figure 4. Receive Path Frequency Response Preliminary Rev. 1.11 9 Si 3210/ Si3 211/S 211/S i32 12 Figure 5. Transmit Group Delay Distortion Figure 6. Receive Group Delay Distortion 10 Preliminary Rev. 1.11 Si3210/Si3211/Si3212 Si3210/Si3211/Si3212 Table 4. Linefeed Characteristics (VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70°C for K-Grade, ­40 to 85°C for B-Grade) Parameter Symbol Test Condition Min Typ Max Unit RLOOP See note.* 0 - 160 ILIM = 29 mA, ETBA = 4 mA ­10 - 10 % Active Mode; VOC = 48 V, VTIP ­ VRING ­4 - 4 V RDO ILOOP < ILIM - 160 - DC Open Circuit Voltage- Ground Start VOCTO IRING