SY58020/21/22U SY58022U--5 SY58020U SY58021U SY58022U OC-48 E3620A SY58021/22U - Datasheet Archive

 

1:4 LVPECL/CML FANOUT BUFFER WITH INTERNAL TERMINATION FEATURES ® Precision Edge SY58020/21/22U Evaluation Board

 

Micrel, Inc. 1:4 LVPECL/CML FANOUT BUFFER WITH INTERNAL TERMINATION FEATURES ® Precision Edge SY58020/21/22U SY58020/21/22U Evaluation Board SY58020/21/22U SY58020/21/22U EVALUATION BOARD DESCRIPTION Precision, fully differential 1:4 fanout buffer family · SY58020U-6GHz any diff. input-to-CML outputs (4) · SY58021U-4GHz any diff. input-to-800mV LVPECL outputs (4) · SY58022U-5 SY58022U-5.5GHz any diff. input-to-400mV LVPECL outputs (4) Low jitter performance: · < 10psPP total jitter (clock) · < 1psRMS random jitter (data) · < 10psPP deterministic jitter (data) Accepts an input signal as low as 100mV Unique input termination and VT pin accepts DC- and AC-coupled differential inputs: LVPECL, LVDS, and CML Power supply 2.5V ±5% and 3.3V ±10% Industrial ­40°C to +85°C temperature range Available in 16-pin (3mm × 3mm) MLF® package The SY58020U SY58020U, SY58021U SY58021U, and SY58022U SY58022U are 2.5V/3.3V precision, high-speed, fully differential 1:4 fanout buffers with CML, LVPECL, and 400mV LVPECL outputs. The SY58020U SY58020U and SY58022U SY58022U can process clock signals as fast as 6GHz and 5.5GHz respectively, whereas, the SY58021U SY58021U (800mV LVPECL) can process clock signals as fast as 4GHz. The 1:4 fanout buffers include Micrel's unique, 3-pin input termination architecture that allows the devices to directly interface to LVPECL, CML, and LVDS differential signals (AC-coupled or DC-coupled) without any level-shifting or termination resistor network in the signal path. This documentation provides design and implementation information, and a detailed description of the SY58020U SY58020U, SY58021U SY58021U, and SY58022U SY58022U evaluation boards. The evaluation boards are intended to provide a convenient test and evaluation platform. All data sheets and support documentation can be found on Micrel's web site at: www.micrel.com. APPLICATIONS All SONET and all GigE clock distribution Fibre Channel clock and data distribution Backplanes Data distribution: OC-48 OC-48, OC-48 OC-48+FEC, XAUI High-end, low skew, multiprocessor synchronous clock distribution Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc. Rev.: D 1 Amendment: /0 Issue Date: March 2007 SY58020/21/22U SY58020/21/22U Evaluation Board Micrel, Inc. Agilent 83752A 0.01GHz to 20GHz Synthersizer Sweeper Agilent 86100A Wide bandwidth Oscilloscope DCA RFOUT TRIG HP 70004A Display Agilent 70818A 0.1Gbps to 12Gbps Error Performance Analyzer CLK IN /IN VEE CLK_IN /CLK TRIG U1 SY58020U SY58020U Q0 /Q0 IN Q1 VT /Q1 VREF-AC Q2 /IN /Q2 /Q3 Q3 VCC HP Power Supply E3620A E3620A VCC = +3.3V Figure 1. SY58020U SY58020U Evaluation Board and DC-Coupled Test Setup (Eye Diagram and tr/tf Setup) Agilent 83752A 0.01GHz to 20GHz Synthersizer Sweeper Agilent 86100A Wide bandwidth Oscilloscope DCA RFOUT TRIG HP 70004A Display Agilent 70818A 0.1Gbps to 12Gbps Error Performance Analyzer CLK VEE CLK_IN /CLK TRIG U1 SY58020U SY58020U Q0 /Q0 IN Q1 VT /Q1 VREF-AC Q2 /IN /Q2 /Q3 Q3 VCC HP Power Supply E3620A E3620A VCC = +3.3V Figure 2. SY58020U SY58020U Evaluation Board and AC-Coupled Test Setup (Eye Diagram and tr/tf Setup) 2 IN /IN Micrel, Inc. SY58020/21/22U SY58020/21/22U Evaluation Board Agilent 83752A 0.01GHz to 20GHz Synthersizer Sweeper Agilent 86100A Wide bandwidth Oscilloscope DCA RFOUT TRIG IN /IN HP 70004A Display Agilent 70843A 0.1Gbps to 12Gbps Error Performance Analyzer CLK CLK_IN /CLK TRIG VEE U1 SY58021/22U SY58021/22U Q0 /Q0 IN VT VCC Q1 /Q1 Q2 VREF-AC /IN /Q2 /Q3 Q3 VCC GND HP Power Supply E3620A E3620A +2V +1.3V Figure 3. SY58021/22U SY58021/22U Evaluation Board and DC-Coupled Test Setup (Eye Diagram and tr/tf Setup) Agilent 83752A 0.01GHz to 20GHz Synthersizer Sweeper Agilent 86100A Wide bandwidth Oscilloscope DCA RFOUT TRIG HP 70004A Display Agilent 70843A 0.1Gbps to 12Gbps Error Performance Analyzer CLK CLK_IN /CLK TRIG VEE U1 SY58021/22U SY58021/22U Q0 IN VT /Q0 Q1 VREF-AC /IN /Q3 VCC Q2 /Q2 Q3 /Q1 VCC GND HP Power Supply E3620A E3620A VCC = +3.3V Figure 4. SY58021/22U SY58021/22U Evaluation Board and AC-Coupled Test Setup (Eye Diagram and tr/tf Setup) 3 IN /IN SY58020/21/22U SY58020/21/22U Evaluation Board Micrel, Inc. FUNCTIONAL DESCRIPTION The SY58020U SY58020U, SY58021U SY58021U and SY58022U SY58022U evaluation boards simplify test and measurement of jitter and ACperformance and have been preconfigured to function at both 2.5 ±5% and 3.3V ±10% supply voltage. Layer Stack SY58020U SY58020U L1 L2 L3 L4 Signal Inputs/Outputs The SY58020/21/22U SY58020/21/22U evaluation boards have been designed and shipped with AC-coupled inputs, and DCcoupled outputs. The SY58020U SY58020U, SY58021U SY58021U and SY58022U SY58022U require a 100mV minimum input signal to guarantee operation. The SY58020U SY58020U CML outputs deliver 400mV swing into 50. The SY58021U SY58021U outputs provide 800mV swing (100k compatible), and the SY58022U SY58022U outputs provide a faster, 400mV LVPECL swing (100k compatible). Unused output pairs maybe left floating with no impact on jitter. Signal/VCC Impedance VCC GND Signal/VCC Layer Stack SY58021/22U SY58021/22U L1 L2 L3 L4 Signal/GND Impedance GND VCC Signal/GND Test Description This section contains step-by-step instructions for evaluating the SY58020U SY58020U, SY58021U SY58021U, and SY58022U SY58022U. There are several evaluation tests that can be performed on the devices. First, the devices can be tested functionally for AC-performance including eye-diagram generation, and second, the devices can be tested for jitter. Power Supply The SY58020U SY58020U, SY58021U SY58021U and SY58022U SY58022U are 2.5V ±5% and 3.3V ±10% devices. The SY58020U SY58020U CML evaluation board has been configured for positive power supply, see Figure 1, meaning VCC = +3.3V, and GND = 0V. Further, the SY58021U SY58021U and SY58022U SY58022U LVPECL evaluation boards have been configured for split power supply, meaning VCC = 2V, GND = 0V, and VEE = (­0.5V or ­1.3) see Figure 3. Therefore, the SY58021/22U SY58021/22U are shipped with split power supply, so that the output can directly interface with a 50 load. Functionality AC-Testing Equipment 1. 2. 3. 4. HP8133A HP8133A Function Generator HP E3620A E3620A Power Supply Agilent 86100A Widebandwidth Oscilloscope DCA Agilent 83752A 0.01GHz to 20GHz Synthesizer Sweeper 5. HP70004A HP70004A Display 6. Agilent 70843A 0.1Gbps to 12Gbps Error Performance Analyzer 7. Harbour Industries Stiff Cables Model 2748 SB-142 SB-142 SY58020U SY58020U AC-Coupled Output Configuration The SY58020U SY58020U can be configured for AC-coupled output by following the next few steps. 1. Add AC-coupling capacitors, which normally is 0.1µF, to C6-C7, C8-C11 C8-C11 and C12-C13 C12-C13, see Figure 5 and 6. (The value of the AC-coupling capacitor depends on the frequency of the application.) SY58021/22U SY58021/22U AC-Coupled Output Configuration AC-Testing The SY58021/22U SY58021/22U can be configured for normal power supply or VCC = 2.5V/3.3V and GND = VEE = 0 by following the next few steps. 1. Add AC-coupling capacitors, which normally is 0.1µF to C6-C7, C8-C11 C8-C11 and C7-C8, see Figure 7 and 8. (The value of the AC-coupling capacitor depends on the frequency of the application.) 2. Add resistor pull-downs R1-R8. The resistor pull-downs, are normally 50 for VCC = 2.5V or 100 for VCC = 3.3V. SY58020U SY58020U 1. Connect VCC to +3.3V, and GND to 0V. 2. Using Agilent BERT Stack (see Figure 1) connect OUT and /OUT to IN and /IN of the SY58020U SY58020U. 3. Set the desired frequency of operation, and make sure that VIL and VIH and fMAX are within data sheet limits. The SY58020U SY58020U can accept LVPECL, LVDS, and CML input compatible signals. In addition, if an eye-diagram is desired, set the Agilent BERT Stack to 223­1 PRBS pattern, if a clock pattern is desired, set the Agilent BERT Stack accordingly. 4. Connect OUT and /OUT of the evaluation board to an oscilloscope. 5. Connect the trigger out connection of the Agilent BERT Stack to the input trigger of the oscilloscope and make measurement. Board Layout The evaluation boards are constructed with Rogers 4003 material and is co-planer designed to minimize noise, and achieve high bandwidth, and minimize crosstalk. 4 Micrel, Inc. SY58020/21/22U SY58020/21/22U Evaluation Board SY58021U SY58021U and SY58022U SY58022U trigger output of the HP8133A HP8133A should connect to the ARM input of the Wavecrest instrument. 2. On the HP8133A HP8133A, select bit 0 as trigger start, in addition, configure the HP8133A HP8133A to the desired datarate and NRZ data pattern. 3. On the Wavecrest instruments menu, select datacom tool. 4. Then click on known pattern w/marker on the menu. 5. Under the View Tab, select ­DCD+DDJ vs. SPA. 6. Make sure that the following settings are configured: a. Quick Mode = On b. Tail Fit = Off c. Advanced Options = Off 7. Hit the pulse find button and make sure that the appropriate levels are being read on the Wavecrest. For example, if the device is LVPECL, 800mV should be read from the Wavecrest with correct VOH and VOL levels. 8. Click on the display bottom and select values on plot to be view all. 9. Then on the advanced options button select on and go to page 2 of the Wavecrest menu, select learn pattern option and include DCD+DDJ calibration. Additionally, set the total number of bits to be 32, and set the appropriate bit rate then click on learn. 10. The Wavecrest will then plot the K28.5 bit sequence and determine the deterministic jitter, random jitter, and total jitter of the HP8133A HP8133A. 11. At this point save the results, and reload the results into the Wavecrest. 12. Next, drive the SY58020U SY58020U, or SY58021U SY58021U, or SY58022U SY58022U with the HP8133A HP8133A, and connect the outputs of the Wavecrest. 13. Repeat #3 and #10 and compare the results of the generated jitter to the jitter generated by the HP8133A HP8133A. The difference between the two measurements will determine the deterministic jitter being generated by the device. 1. Connect VCC to 2V, GND to 0V, and VEE = (­0.5V or ­1.3V) for DC-coupled outputs shown in Figure 3 and connect VCC = 3.3V, GND and VEE to 0V for ACcoupled outputs as shown in Figure 1. 2. Using Agilent BERT Stack (see Figure 1) connect OUT and /OUT to IN and /IN of the SY58021U SY58021U and SY58022U SY58022U. 3. Set the desired frequency of operation, and make sure that VIL and VIH and fMAX are within data sheet limits. The SY58021U SY58021U and SY58022U SY58022U can accept LVPECL, LVDS, and CML input compatible signals. In addition, if an eye-diagram is desired, set the Agilent BERT Stack to 223­1 PRBS pattern, if a clock pattern is desired, set the Agilent BERT Stack accordingly. 4. Connect OUT and /OUT of the evaluation board to an oscilloscope. 5. Connect the trigger out connection of the Agilent BERT Stack to the input trigger of the oscilloscope and make measurement. Jitter Test Measuring jitter is a relative process and involves establishing a base line. Measure the generated jitter from a pulse generator used to drive the SY58020U SY58020U, SY58021U SY58021U, or SY58022U SY58022U. Once this is established, jitter generated from the part is compared against the jitter generated from the pulse generator, and the difference is the jitter generated from the DUT. Deterministic Jitter Configure a HP8133A HP8133A Pulse Generator to a PRBS K28.5 data pattern at 3E8CC173 3E8CC173'H and set the HP8133A HP8133A to a desired frequency with LVPECL, 400mV LVPECL, or CML levels and connect the outputs to a Wavecrest DTS-2079 DTS-2079. Remember that the level set should correspond to the output level expected from the device under test. In other words, if it's the SY58020U SY58020U that is being tested, the output of the HP8133A HP8133A should be set to CML and the VOH and VOL levels should correspond to the outputs of the device. If the level is not set at the same level generated from the device, the measurement will be off. In addition, if it's the SY58021U SY58021U that is to be tested, the LVPECL should be programmed level generated from the HP8133A HP8133A, and likewise for the SY58022U SY58022U, set the output of the HP8133A HP8133A to 400mV LVPECL. The next few steps involves performing a learn operation which measures the amount of jitter generated from the HP8133A HP8133A which will be stored and the results compared against the jitter generated by the devices when driven by a HP8133A HP8133A. Random Jitter Random jitter can be measured two different ways. One way is similar to measuring the deterministic jitter which uses a Wavecrest DTS instrument, but with a K28.7 1010. (clock pattern) using the same concept of measuring the jitter generated by the Agilent 8133A, then comparing it to the jitter generated from the device while being driven by the Agilent 8133A. Another way is to drive the device using a clock pattern and measuring the histogram at the output using a Tektronic scope and directly measuring the random jitter. Wavecrest Setup 1. Connect the HP8133A HP8133A to the Wavecrest instruments. The output OUT of the HP8133A HP8133A should connect to the input CH1 of the Wavecrest instrument, and the 5 SY58020/21/22U SY58020/21/22U Evaluation Board Micrel, Inc. J2 111-0702-001 VCC C4 C5 J1 111-0702-001 VCC VCC SMA10 SMA10 142-0701-851 SMA9 142-0701-851 C13 C12 Boards are shipped for DC-coupled outputs. C6 to C13 = 0 resistors. VCC /Q0 U1 SY58020U SY58020U VREF-AC VT VCC C10 /Q1 Q2 5 6 7 10 C9 9 C8 SMA7 142-0701-851 SMA6 142-0701-851 8 SMA5 142-0701-851 SMA2 142-0701-851 VCC C11 11 /Q2 /IN GND 4 12 VCC 3 SMA8 142-0701-851 Q1 Q3 C2 C3 13 IN 2 VCC GND 1 14 /Q3 C1 15 VCC 16 SMA1 142-0701-851 Q0 VCC VCC VCC VCC VCC C6 C7 SMA3 142-0701-851 SMA4 142-0701-851 VCC Notes. 1. EPAD = GND 2. In DC-coupled mode, C6-C13 C6-C13 are 0 resistors. VCC Figure 5. SY58020U SY58020U DC-Coupled Evaluation Board Schematic 6 Micrel, Inc. SY58020/21/22U SY58020/21/22U Evaluation Board J2 111-0702-001 VCC C4 C5 J1 111-0702-001 VCC VCC SMA10 SMA10 142-0701-851 SMA9 142-0701-851 C12 C13 VCC C11 IN 3 /IN 6 7 C10 11 SMA7 142-0701-851 /Q1 Q2 /Q2 GND C3 4 U1 SY58020U SY58020U VREF-AC VT 10 C9 9 SMA6 142-0701-851 8 C8 VCC 5 SMA2 142-0701-851 VCC SMA5 142-0701-851 C7 C6 SMA3 142-0701-851 SMA4 142-0701-851 VCC VCC Notes. 1. EPAD = GND 2. In AC-coupled mode, C6-C13 C6-C13 are 0.1µF capacitors, (actual value depends on the frequency of interest.) Figure 6. SY58020U SY58020U AC-Coupled Evaluation Board Schematic 7 VCC 12 VCC C2 SMA8 142-0701-851 Q1 Q3 2 VCC 13 VCC 1 14 /Q3 C1 GND SMA1 142-0701-851 15 Q0 16 /Q0 VCC VCC VCC VCC SY58020/21/22U SY58020/21/22U Evaluation Board Micrel, Inc. VCC J2 VCC Red Banana Jack 111-0702-001 C1 C2 VEE J3 VEE C4 SMA10 SMA10 142-0701-851 J1 C13 VCC 3 4 C15 Q0 VCC 12 IN 2 C5 13 Q1 U1 /Q1 SY58021/22U SY58021/22U Q2 VREF-AC C11 11 C10 10 C9 9 C8 VT /Q2 /IN 6 5 SMA2 142-0701-851 VCC VCC 1 14 Q3 C14 15 GND 16 /Q0 SMA1 142-0701-851 Boards are shipped for DC-coupled outputs. C6 to C13 = 0 resistors. C12 VEE GND Red Banana Jack 111-0702-001 SMA9 142-0701-851 /Q3 C3 GND Red Banana Jack 111-0702-001 7 8 VEE SMA7 142-0701-851 SMA6 142-0701-851 SMA5 142-0701-851 VCC C6 SMA8 142-0701-851 C7 SMA3 142-0701-851 SMA4 142-0701-851 Notes. 1. EPAD = VEE 2. In DC-coupled mode, C6-C13 C6-C13 are 0 resistors, and R3-R6 are not mounted, see Figure 8. Figure 7. SY58021/22U SY58021/22U DC-Coupled Evaluation Board Schematic 8 Micrel, Inc. SY58020/21/22U SY58020/21/22U Evaluation Board VCC J2 VCC Red Banana Jack 111-0702-001 C1 C2 VEE J3 VEE Red Banana Jack 111-0702-001 C3 C4 SMA10 SMA10 142-0701-851 SMA9 142-0701-851 C13 J1 R8 C12 R7 GND 12 Q0 SMA7 142-0701-851 C9 SMA6 142-0701-851 C8 SMA5 142-0701-851 R5 U1 /Q1 SY58021/22U SY58021/22U VREF-AC Q2 11 /Q2 9 VT /IN 6 7 10 R4 VCC 4 SMA8 142-0701-851 Q1 Q3 3 C15 R6 C11 C10 13 IN 2 C5 /Q0 1 14 /Q3 C14 VCC 15 GND 16 VCC VCC VEE SMA1 142-0701-851 GND Red Banana Jack 111-0702-001 8 R3 5 SMA2 142-0701-851 VEE VCC R1 C6 SMA3 142-0701-851 Notes. 1. EPAD = VEE 2. For a 2.5V system, R1-R8 is 50. For a 3.3V system, R1-R8 is 100. R2 C7 SMA4 142-0701-851 Figure 8. SY58021/22U SY58021/22U AC-Coupled Evaluation Board Schematic 9 SY58020/21/22U SY58020/21/22U Evaluation Board Micrel, Inc. BILL OF MATERIALS SY58020U SY58020U Item Part Number Manufacturer Description C1-C4, C6-C13 C6-C13 VJ0402Y104KXXAT VJ0402Y104KXXAT Vishay(1,4) 0.1µF, 10%, Ceramic Capacitor, Size 0402 Dielectric, Size 0402 Qty. 12 C5 293D685X0025C2T 293D685X0025C2T Vishay(1) 6.8µF, 20V, Tantalum Electrolytic, Capacitor, Size C 1 J1 111-0703-001 Johnson Components(2) Black Banana Jack 1 J2 111-0703-001 Johnson Components(2) Red Banana Jack 1 SMA1­SMA10 SMA10 142-0701-851 Johnson Components(2) Jack Assembly End Launch SMA 10 U1 SY58020U SY58020U Micrel, Inc.(3) 6GHz 1:4 Fanout Buffer w/CML Outputs and Internal Termination 1 Part Number Manufacturer Description C1, C3, C5-C15 C5-C15 VJ0402Y104KXXAT VJ0402Y104KXXAT Panasonic(1, 4) 0.1µF, 25V, 10%, Ceramic Capacitor, X5R Dielectric, Size 0402 13 C2, C4 293D685X0025C2T 293D685X0025C2T Panasonic(1) 6.8µF, 20V, Tantalum Electrolytic, Capacitor, Size C 2 J1 111-0703-001 Johnson Components(2) Black Banana Jack 1 J2, J3 111-0703-001 Johnson Components(2) Red Banana Jack 2 Panasonic(1, 5) Chip Resistors, size 0403 8 Jack Assembly End Launch SMA 10 4GHz to 5.5GHz 1:4 Fanout Buffer w/LVPECL Outputs and Internal Termination 1 SY58021/22U SY58021/22U Item R1-R8 Components(2) SMA1­SMA10 SMA10 142-0701-851 Johnson U1 SY58021/22U SY58021/22U Micrel, Inc.(3) Qty. Notes: 1. Vishay: www.vishay.comm. 2. Johnson Components: www.johnsoncomponents.com. 3. Micrel, Inc.: www.micrel.com. 4. In DC-coupled mode, C6-C13 C6-C13 are 0 resistors. 5. In AC-coupled mode, R1-R8 are 50 for a 2.5V system, and 100 for a 3.3V system. In addition, in DC-coupled mode R1-R8 are unmounted. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. 10