SUD50P10-43L - Datasheet Archive

 

Vishay Siliconix P-Channel 100-V (D-S) MOSFET CHARACTERISTICS · P-Channel Vertical DMOS · Macro Model (Subcircuit

 

SPICE Device Model SUD50P10-43L SUD50P10-43L Vishay Siliconix P-Channel 100-V (D-S) MOSFET CHARACTERISTICS · P-Channel Vertical DMOS · Macro Model (Subcircuit Model) · Level 3 MOS · Apply for both Linear and Switching Application · Accurate over the -55 to 125°C Temperature Range · Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 73467 S-51620Rev. A, 05-Sep-05 www.vishay.com 1 SPICE Device Model SUD50P10-43L SUD50P10-43L Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Condition Simulated Data VGS(th) VDS = VGS, ID = -250 A Measured Data 1.9 Unit Static Gate Threshold Voltage On-State Drain Current a Drain-Source On-State Resistancea ID(on) rDS(on) V VDS -5 V, VGS = -10 V 146 VGS = -10 V, ID = -9.2 A 0.034 0.036 VGS = -4.5 V, ID = -7.7 A 0.038 0.040 A Forward Transconductancea gfs VDS = -15 V, ID = -9.2 A 24 38 S Diode Forward Voltagea VSD IS = -7.7 A -0.85 -0.80 V 5013 4600 Dynamicb Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg VDS = -50 V, VGS = 0 V, f = 1 MHz Qgs Gate-Drain Charge Qgd VDS = -50 V, VGS = -4.5 V, ID = -9.2 A 100 106 54 14 14 26 pF 175 54 Gate-Source Charge 230 177 VDS = -50 V, VGS = -10 V, ID = -9.2 A 246 26 nC Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 73467 S-51620Rev. A, 05-Sep-05 SPICE Device Model SUD50P10-43L SUD50P10-43L Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 73467 S-51620Rev. A, 05-Sep-05 www.vishay.com 3