SUD50P08-25L - Datasheet Archive

 

Vishay Siliconix P-Channel 80-V (D-S) MOSFET CHARACTERISTICS · P-Channel Vertical DMOS · Macro Model (Subcircuit

 

SPICE Device Model SUD50P08-25L SUD50P08-25L Vishay Siliconix P-Channel 80-V (D-S) MOSFET CHARACTERISTICS · P-Channel Vertical DMOS · Macro Model (Subcircuit Model) · Level 3 MOS · Apply for both Linear and Switching Application · Accurate over the -55 to 125°C Temperature Range · Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 73498 S-51618Rev. A, 05-Sep-05 www.vishay.com 1 SPICE Device Model SUD50P08-25L SUD50P08-25L Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Condition Simulated Data VGS(th) VDS = VGS, ID = -250 A Measured Data 2 Unit Static Gate Threshold Voltage On-State Drain Current a Drain-Source On-State Resistancea ID(on) rDS(on) V VDS = -5 V, VGS = -10 V 234 VGS = -10 V, ID = -12.5 A 0.021 0.021 VGS = -6 V, ID = -10.5 A 0.024 0.024 A Forward Transconductancea gfs VDS = -15 V, ID = -12.5 A 33 30 S Diode Forward Voltagea VSD IS = -10.5 A -0.86 -0.80 V 5320 4700 Dynamicb Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg VDS = -40 V, VGS = 0 V, f = 1 MHz Qgs Gate-Drain Charge Qgd VDS = -40 V, VGS = -4.5 V, ID = -12.5 A 108 105 55 22 22 43 pF 235 55 Gate-Source Charge 320 198 VDS = -40 V, VGS = -10 V, ID = -12.5 A 272 43 nC Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 73498 S-51618Rev. A, 05-Sep-05 SPICE Device Model SUD50P08-25L SUD50P08-25L Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 73498 S-51618Rev. A, 05-Sep-05 www.vishay.com 3