STV8130AD DIP16 STV8130A ----------------------------10A STV8130D

Adjustable and +3.3 V dual voltage regulator with disable and reset functions Features Input voltage range: 5 V to 18 V Output

STV8130AD STV8130AD Adjustable and +3.3 V dual voltage regulator with disable and reset functions Features Input voltage range: 5 V to 18 V Output currents up to 750 mA Fixed precision output 1 voltage: 3.3 V ±2% Adjustable output 2 voltage: 2.8 to 16 V Output 1 with reset function Output 2 with disable function by TTL Input Short-circuit protection at both outputs Thermal protection Low dropout voltage SIP9 (plastic package) DIP16 DIP16 (8 + 8) Table 1. uc d Device summary STV8130A STV8130A# ro STV8130AD STV8130AD Tray Order code Description eP let The STV8130A STV8130A# and STV8130AD STV8130AD are monolithic dual positive voltage regulators designed to provide a fixed precision output voltage of 3.3 V and an adjustable voltage between 2.8 and 16 V for currents up to 750 mA. An internal reset circuit generates a reset pulse when the voltage of output 1 drops below the regulated voltage value. (s) ct s) t( Packaging Tray so Ob - Output 2 can be disabled via the TTL input. du o Short-circuit and thermal protections are included. Figure 1. Pr e STV8130A STV8130A# and STV8130AD STV8130AD let o bs O 9 8 7 6 5 4 3 2 1 OUTPUT1 OUTPUT2 PROGRAM RESET GROUND DISABLE DELAY CAPACITOR INPUT2 INPUT1 1 16 GROUND Rev 3 INPUT2 2 15 GROUND DELAY CAPACITOR 3 14 GROUND DISABLE 4 13 GROUND RESET 5 12 GROUND PROGRAM 6 11 GROUND OUTPUT2 7 10 GROUND OUTPUT1 Tab is connected to GROUND March 2009 INPUT1 8 9 GROUND 1/14 www.st.com 1 Contents STV8130AD STV8130AD Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Power dissipation and layout indications . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.1 7 uc d Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 te le (s) ct du o Pr e let o bs O 2/14 s) t( Environmentally-friendly packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 so Ob - ro P STV8130AD STV8130AD 1 Description Description Figure 2. STV8130A STV8130A# block diagram DELAY CAPACITOR 3 6 RESET Reference INPUT1 1 9 OUTPUT1 Regulator 1 Protection INPUT2 2 DISABLE 4 uc d 7 PROGRAM 5 te le GROUND Figure 3. s) t( 8 OUTPUT2 Regulator 2 ro P so Ob - STV8130AD STV8130AD block diagram DELAY CAPACITOR 3 (s) 5 RESET ct u Reference od Pr e INPUT1 let o O bs 1 INPUT2 2 DISABLE 8 OUTPUT1 Regulator 1 Protection 4 Regulator 2 7 OUTPUT2 6 PROGRAM Pins 9 to 16 GROUND 3/14 Electrical characteristics 2 STV8130AD STV8130AD Electrical characteristics Table 2. Absolute maximum ratings Symbol Parameter Value Unit VIN DC input voltage at pins INPUT1 and INPUT2 20 V VDIS Disable input voltage at pin DISABLE 20 V VRST Output voltage at pin RESET 20 V IOUT1,2 Output currents Internally limited Pt Power dissipation Internally limited TSTG Storage temperature -65 to +150 °C TJ Junction temperature 0 to +150 °C Table 3. Thermal data Symbol Parameter uc Value RthJC Thermal resistance (junction-to-case) STV8130A STV8130A# STV8130AD STV8130AD RthJA Thermal resistance (1) (junction-toambient) STV8130A STV8130A# STV8130AD STV8130AD TJ TOPER od r eP let 9 15 s) t( Unit °C/W 50 56 °C/W Maximum recommended junction temperature 140 °C Operating free air temperature range 0 to +70 °C so Ob - 1. Mounted on board. For more information, refer to Section 5. Table 4. (s) ct Electrical characteristics Symbol Parameter VOUT1 Output voltage VOUT2 Output voltage VIO1,2 du Dropout voltage Test conditions Min. 16.0 V IOUT1,2 = 750 mA 1.4 V Line regulation 6 V < VIN1 < 12 V 12 V < VIN2 < 18 V IOUT1,2 = 200 mA 50 100 mV VO1,2LO Load regulation 5 mA < IOUT1 < 600 mA 5 mA < IOUT2 < 600 mA 100 200 mV IQ Quiescent current IOUT1 = 10 mA, OUTPUT2 Disabled 2 mA VO1RST Reset threshold voltage(1) K = VOUT1, IOUT1 50 mA K - 0.4 K - 0.25 K - 0.1 V VRTH Reset threshold hysteresis See circuit description 20 50 mV tRD Reset pulse delay Ce = 100 nF See circuit description let o bs O 4/14 IOUT2 = 10 mA 3.30 2.8 Unit V VO1,2LI 3.23 Max. 3.37 ro P e IOUT1 = 10 mA Typ. 25 75 ms STV8130AD STV8130AD Table 4. Electrical characteristics Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit VRL Saturation voltage in reset condition IRESET = 5 mA 0.4 V IRH Leakage current in normal condition VRESET = 10 V 10 µA KOUT1, 2 V 0 10 6 K 0 = -T V 0 Output voltage thermal drift 100 ppm/°C TJ = 0 to + 125°C VIN1 = 7 V, VIN2 = 10 V VIN1,2 = 16 V(2) IOUT1,2SC Short circuit output current VDISH Disable voltage when pin DISABLE is high (OUTPUT2 active) VDISL Disable voltage when pin DISABLE is low (OUTPUT2 disabled) IDIS Disable bias current VREF Reference voltage at PROGRAM pin TJSD 1.6 1.0 Junction temperature for thermal shutdown 2 V 0.8 0 V < VDIS < 7 V A -100 2 uc d 2.44 ro P 145 V s) t( µA V °C 1. This reset signal is activated by a decrease of VOUT1 voltage which can be due to an overload of pin OUT1 or by a lack of Input Voltage (VIN1). te le 2. The output short-circuit currents are tested one channel at time. During a short-circuit, a large consumption of power occurs, but the thermal protection circuit prevents any excessive temperatures. A safe permanent short-circuit protection is only guaranteed for input voltages up to 16 V. Note: so Ob - TAMB = 25° C, VIN1 = 7 V, VIN2 = 10 V, unless otherwise specified. (s) ct du o Pr e let o bs O 5/14 Circuit description 3 STV8130AD STV8130AD Circuit description The STV8130A STV8130A# and STV8130AD STV8130AD are dual-voltage regulators with reset and disable functions. The two regulation parts are supplied from a single voltage reference circuit trimmed by zener zapping during EWS testing. Since the supply voltage of this voltage reference is connected to pin INPUT1 (VIN1), the second regulator will not work if pin INPUT1 is not supplied. The adjustable voltage of pin OUTPUT2 (VOUT2) is defined by output bridge resistors (R1, R2): the values of these resistors are calculated to obtain, with the targetted value for VOUT2, the reference voltage (VREF = 2.44 V) on the median point connected to pin PROGRAM. The output stages are designed using a Darlington configuration with a typical dropout voltage of 1.2 V. The disable circuit will switch off pin OUTPUT2 if a voltage less than 0.8 V is applied to pin DISABLE. s) t( The reset circuit checks the voltage at pin OUTPUT1. If this voltage drops below VOUT1 0.25 V (3.05 V Typ.), the "a" comparator (Figure 4) rapidly discharges the external capacitor (Ce) and the reset output immediately switches to low. This drop can be caused by a parasitic loading condition on pin OUTPUT1 or by a too low value of VIN (short powering off). When the voltage at pin OUTPUT1 exceeds VOUT1 - 0.2 V (3.1 V Typ.), the VCe voltage increases linearly to the reference voltage (VREF = 2.44 V) corresponding to a reset pulse delay (tRD) as shown in Figure 5. uc d te le ro P C e × 2.44V t RD = -10A so Ob - Afterwards, the reset output returns to high. To avoid glitches in the reset output, the second comparator "b" has a large hysteresis (1.84 V). Figure 4. (s) ct Reset diagram du o VREF Pr e OUTPUT1 let o VREF = 2.44 V bs O 6/14 REG 10 µA + a - 50 + 3 Ce VREF 0.6V b RESET STV8130AD STV8130AD Circuit description Figure 5. Internal reset diagram VOUT1 K VO1RST VRTH RESET K = Actual Value of VOUT1 tRD Power On tRD Power Off uc d te le (s) ct s) t( ro P so Ob - du o Pr e let o bs O 7/14 Application diagrams 4 STV8130AD STV8130AD Application diagrams Figure 6. STV8130A STV8130A# typical application RESET Ce 6 RESET V IN1 1 INPUT1 V IN2 R1 + R2 V O2 = V REF -R1 0.1 µF 3 DELAY CAPACITOR OUTPUT1 9 2 INPUT2 R1 Value (typ.) = 10 k VREF = 2.44 V V OUT1 STV8130A STV8130A# OUTPUT2 8 GROUND C1 DISABLE PROGRAM 5 4 7 V OUT2 C4 C2 R2 C3 DISABLE R1 uc d C1 to C4 = 10 µF Figure 7. STV8130AD STV8130AD typical application te le RESET Ce 5 RESET V IN1 1 INPUT1 V IN2 0.1 µF so Ob - 3 DELAY CAPACITOR OUTPUT1 8 2 INPUT2 (s) t ro P R1 + R2 V O2 = V REF -R1 R1 Value (typ.) = 10 k V OUT1 STV8130AD STV8130AD uc d C1 ro P e let o C1 to C4 = 10 µF bs O 8/14 C2 Pins 9 to 16 GROUND OUTPUT2 7 DISABLE 6 V OUT2 PROGRAM 4 C4 R2 C3 DISABLE s) t( R1 VREF = 2.44 V STV8130AD STV8130AD 5 Power dissipation and layout indications Power dissipation and layout indications The power is mainly dissipated by the two device buffers. It can be calculated by the equation: P = (VIN1-VOUT1) x IOUT1 + (VIN2-VOUT2) x IOUT2 The following table lists the different RthJA values of these packages with or without a heat sink and the corresponding maximum power dissipation assuming: Maximum ambient temperature = 70° C Maximum Junction temperature = 140° C Table 5. Power dissipation Device Heat sink RthJA in °C/W PMAX in W No 50 1.4 Yes 20 3.5 No 56 to 40 1.25 to 1.75 Yes STV8130A STV8130A# 32 2.2 uc d STV8130AD STV8130AD Figure 8. ro P Thermal resistance (junction-to-ambient) of DIP16 DIP16 package without heatsink To optimize the thermal conductivity of the copper layer and the exchanges with the air, the solder must cover the maximum amount of this area te le 60 RthJA °C/W s) t( 55 50 (s) ct 45 40 0 2 du o 6 4 8 10 so Ob - Test board with "on board" square heat sink area. 12 Pr e Copper area (cm²) (35 µm plus solder) board is face-down let o Figure 9. Metal plate mounted near the STV8130AD STV8130AD for heatsinking bs O Top View Bottom View 9/14 Package mechanical data 6 STV8130AD STV8130AD Package mechanical data Figure 10. 9-pin plastic single in-line package uc d Table 6. te le so mm Min. Typ. A ct du 0.5 ro P e b3 C 0.85 let o bs O (s) 2.7 b1 c2 Ob Max. Min. Inches Typ. 7.1 B c1 ro P 9-pin plastic single in-line package dimensions Dim. a1 3 0.106 0.118 24.8 0.976 0.020 1.6 0.033 0.063 0.130 0.43 0.017 1.32 0.052 21.2 0.835 d1 14.5 0.571 e 2.54 0.100 e3 20.32 0.800 3.1 1.122 L1 3 0.116 L2 10/14 Max. 0.280 3.3 D L s) t( 17.6 0.693 STV8130AD STV8130AD Package mechanical data Table 6. 9-pin plastic single in-line package dimensions (continued) mm Inches Dim. Min. Typ. Max. L3 Min. Typ. Max. 0.25 0.010 M 3.2 0.126 N 1 0.039 Figure 11. 16-pin plastic dual in-line package, 300-mil width uc d te le Table 7. (s) ct mm Min. Typ. A A1 A2 2.92 ro P e 0.38 let o b2 bs c D O ro P 16-pin plastic dual in-line package dimensions Dim. b so Ob - s) t( 0.36 du 3.30 Max. Min. Typ. 5.33 Max. 0.210 0.015 4.95 0.115 0.56 0.014 1.52 1.78 0.20 0.25 0.36 18.67 19.18 19.69 e Inches 0.130 0.195 0.022 0.060 0.070 0.008 0.010 0.014 0.735 0.755 0.775 2.54 0.100 E1 6.10 6.35 7.11 0.240 0.250 0.280 L 2.92 3.30 3.81 0.115 0.130 0.150 11/14 Package mechanical data 6.1 STV8130AD STV8130AD Environmentally-friendly packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. uc d te le (s) ct du o Pr e let o bs O 12/14 so Ob - ro P s) t( STV8130AD STV8130AD 7 Revision history Revision history Table 8. Document revision history Date Revision Changes August 2001 1.8 General Update; DISABLE pin renamed DISABLE (function remains unchanged) September 2001 1.9 Thermal Data updated September 2001 2.0 Addition of DIP16 DIP16 package October 2001 2.1 Thermal Data updated. Figure 2 and Figure 3 updated 31 January 2002 2.2 Order code changed from STV8130A STV8130A and STV8130D STV8130D to STV8130A STV8130A# and STV8130AD STV8130AD. Update of VO1RST values in Section 2 05-Mar-2009 3 Preliminary data banner removed, template updated and Section 6.1 added uc d te le (s) ct s) t( ro P so Ob - du o Pr e let o bs O 13/14 STV8130AD STV8130AD Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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