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STS-48/STM16

Catalog Datasheet MFG & Type PDF Document Tags

STM-16

Abstract: · Supports STS-12/STM-4 to STS-48/STM-16 Mux/Demux functions · 8-bit LVDS data path for STS-48/STM-16 , chip is a fully integrated STS-12/STM-4 to STS-48/STM-16 Mux/Demux device. The S3045 performs all , -12/ STM-4 data streams into/from a single STS-48/STM16 data stream. The S3045 functions in conformance , / demultiplex four STS-12/STM-4 data streams into a single STS-48/STM-16 data stream. Each of the four STS , compatibility with industry standard network interface processors. The STS-48/STM-16 data stream uses an 8
Applied Micro Circuits
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OC-12 OC-48 STS-48/STM-16 S3041/S3042 PM5355 PM5312

PEB2757AE

Abstract: STM-16 PEB2757AE TETHYSTM II 4 STS-192/STM-64, 16 STS-48/STM-16, MUX/DEMUX OCT 2009 REV. 1.0.0 GENERAL DESCRIPTION · Processes SONET/SDH sixteen STS-48/STM-16 or a TethysTM II PEB2757AE is , -192/STM64 or mix of sixteen MUX/DEMUX channels of STS-48/STM-16 or STS-12/STM-4 or STS-3/STM-1 (in groups , direction, TethysTM II PEB2757AE accepts either two STS-192/ STM-64 or sixteen STS-48/ STM-16, or a mix of , accepts sixteen STS-48/STM-16 signals in serial 2.5 Gbit/s format. TethysTM II PEB2757AE further
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SFI4 STS-192/STM64 STS-48/ STM-12/STM-4 GR-253 GR-1377 GR-253-CORE

S4805CBI11

Abstract: danube DANUBE Product Brief Part Number S4805CBI11, Revision 1.5, January 2003 SONET/SDH STS-48/STM-16 , Pointer Processors for STS-48/STM-16 and up to 4 x STS-12/STM-4 or 16 x STS-3/STM-1s. · TOH can be , Supports a single STS-48/STM-16 input. Multiplex Direction: · Provides parallel STS-48/STM-16, serial 4xSTS-12/STM-4 or serial 16xSTS-3/STM-1 outputs. · Supports parallel STS-48/STM-16 or serial 4xSTS-12 , -48c/ AU-4-16c, STS-12c/AU-4-4c, STS-3c/AU4, or STS-1/AU-3 signals. · Provides a single STS-48/STM-16
Applied Micro Circuits
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S4805 S4805CBI danube STS-12 AU-4-16 S3024 S3455 622DATA

6 to 64 demux

Abstract: STM-64 /STM-16s. · Multiplexes 4 STS-48/STM-16 tributaries into an STS-192/ STM-64 or bypass for STS , . · Non-Intrusive TOH Monitoring for all inputs: STS-192/STM-64 or 4x STS-48/STM-16. · STS-192/STM , Low-speed side supports a 622 MHz 16-bit STS-192/STM-64 interface or four 622 MHz 4-bit STS-48/STM-16 interfaces. · Demultiplexes an STS-192/STM-64 into 4 STS-48/STM-16 connections or supports a bypass mode , transparently passed-through the device on a per function basis. · STS-192/STM-64 or 4 x STS-48/STM-16 framer
Applied Micro Circuits
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S19223CBI11 STS-192 6 to 64 demux 64 to 4 Mux s19235 xcvr STS-192/STM-64- OC-192 S19223

SDVB

Abstract: PM5312 Supports STS-12/STM-4 to STS-48/STM-16 Mux/Demux functions · 8-bit LVDS data path for STS-48/STM-16 data , -4 to STS-48/STM-16 Mux/Demux device. The S3045 performs all necessary byte interleave and byte , single STS-48/STM16 data stream. The S3045 functions in conformance with SONET/SDH transmission , / demultiplex four STS-12/STM-4 data streams into a single STS-48/STM-16 data stream. Each of the four STS , compatibility with industry standard network interface processors. The STS-48/STM-16 data stream uses an 8
Applied Micro Circuits
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SDVB STS-12/

S3047

Abstract: U311D STS-48/STM-16 Mux/Demux functions · 8-bit LVDS data path for STS-48/STM-16 data · 8-bit LVTTL data , The S3045 SONET/SDH byte interleave chip is a fully integrated STS-12/STM-4 to STS-48/STM-16 Mux/Demux , multiplexing and de-multiplexing of four STS-12/ STM-4 data streams into/from a single STS-48/STM16 data stream , OC-48 M UX/D EM U X 7. Frame synchronous scrambling. 8. B1 calculation and insertion. 9. STS-48/STM-16 , streams into a single STS-48/STM-16 data stream. Each of the four STS-12/STM-4 transmit/receive data
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OCR Scan
S3047 U311D XS-3045 STS-121 311CLKINP 311DATIN 311CLKIN

S4802

Abstract: STS-48 /SDH STS-48/STM-16 Framer/Pointer Processor Features Features Demultiplex Direction: ·SONET/SDH Mux/Demux,Transport Overhead Terminating Transceiver, & Pointer Processors for STS-48/STM-16 and , -1) tributaries from an STS-48/STM-16 or bypass for STS-48/STM-16-to-STS-48/STM-16 connection. ·Serial STS , : ·Multiplexes 4 x (STS-12/STM-4 or 4 STS-3/STM-1) tributaries into an STS-48/STM-16 or bypass for STS-48/STM-16-to-STS-48 , STS-1/AU-3 signals. ·STS-48/STM-16 Framer. ·Configurable selector for choosing low-speed
Applied Micro Circuits
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S4802 Fiber Optic regenerator STS-48/STM-16- FRGEN48 S3063/3064

SFP EVAL BOARD

Abstract: power supply tester schematic diagram EVM-91L82 STS-48/STM-16 SONET/SDH XRT91L82 Evaluation Board User Manual Jul 25, 2006 2.488/2.667 GBPS STS-48/STM-16 SONET/SDH XRT91L82 Transceiver Evaluation Board User Manual 1 EVM-91L82 STS-48/STM-16 SONET/SDH XRT91L82 Evaluation Board User Manual Jul 25, 2006 Figure 1.0 XRT91L82 , . 26 2 EVM-91L82 STS-48/STM-16 SONET/SDH XRT91L82 Evaluation Board User Manual Jul 25 , . 41 3 EVM-91L82 STS-48/STM-16 SONET/SDH XRT91L82 Evaluation Board User Manual Jul 25, 2006
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SFP EVAL BOARD power supply tester schematic diagram OC-48/STM-16

sd 4841 p

Abstract: · Supports STS-12/STM-4 to STS-48/STM-16 Mux/Demux functions · 8-bit LVDS data path for STS-48/STM-16 , chip is a fully integrated STS-12/STM-4 to STS-48/STM-16 Mux/Demux device. The S3045 performs all , -12/ STM-4 data streams into/from a single STS-48/STM16 data stream. The S3045 functions in conformance , multiplex/ demultiplex four STS-12/STM-4 data streams into a single STS-48/STM-16 data stream. Each of the , maintain compatibility with industry standard network interface processors. The STS-48/STM-16 data stream
Applied Micro Circuits
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sd 4841 p

STS-48

Abstract: GR-253 Preliminary PEB1756E TETHYSTM 448 16 STS-48/STM-16 MUX/DEMUX REV. P1.0.0 GENERAL DESCRIPTION TethysTM 448 is optimized for SONET/SDH applications as a full-duplex sixteen STS-48/STM-16 or a , demultiplex ingress direction, TethysTM 448 accepts either sixteen STS-48/ STM-16, or a mix of sixteen STS , overhead transparency. In the multiplex direction, TethysTM 448 accepts sixteen STS-48/STM-16 signals in , -48c/ STM-16 · Supports STS-1 level pointer processing of STS-48/ STM-16 or STM-12/STM-4 or STS-3/STM
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to48c 4x2 mux 105-2000-193R2 3/93-005RI

STM-16 chips

Abstract: S19201 demultiplexing of STS-48/STM-16 SONET/SDH signals into an STS-192/STM-64 SONET/SDH signal. · SONET/SDH low speed side interfaces compatible with AMCC's STS-48/STM-16 devices. · Supports the transfer of up to four STS-48/STM-16 data streams, carrying any valid combination of STS-48c/AU-4-16c, STS-12c/AU , highly-integrated VLSI device that provides for the multiplexing and demultiplexing of STS-48/STM-16 SONET/SDH , four STS-48/STM-16 signals in each direction. On the multiplex side the S19201 generates section
Applied Micro Circuits
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STM-16 chips STS-48/STS-12/STS-3 STS-192/AU-4-64 S3091/S3092
Abstract: · Supports STS-12/STM-4 to STS-48/STM-16 Mux/Demux functions · 8-bit LVDS data path for STS-48/STM-16 , chip is a fully integrated STS-12/STM-4 to STS-48/STM-16 Mux/Demux device. The S3045 performs all , -12/ STM-4 data streams into/from a single STS-48/STM16 data stream. The S3045 functions in conformance , / demultiplex four STS-12/STM-4 data streams into a single STS-48/STM-16 data stream. Each of the four STS , compatibility with industry standard network interface processors. The STS-48/STM-16 data stream uses an 8 Applied Micro Circuits
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AU4-64c

Abstract: processor cross reference Monitoring for all inputs: STS-192/STM-64 or 4x STS-48/STM-16. · SONET/SDH Mux/Demux, Transport Overhead , 4-bit STS-48/STM-16 interfaces. · Demultiplexes an STS-192/STM-64 into 4 STS-48/STM-16 , interface, low-speed interfaces or from APS inputs. · Multiplexes 4 STS-48/STM-16 tributaries into an STS , bypass (frame generation enabled) are provided. · STS-192/STM-64 or 4 x STS-48/STM-16 framer(s). · , function basis. · Configurable TOH Generators for STS-192/STM-64 or STS-48/ STM-16 outputs. · Selector
Applied Micro Circuits
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S19204CBI12 AU4-64c processor cross reference FRGN192 AU44 192x192 S19204 S3485

S3485

Abstract: GR-253 Sales and Support Danube (S4805) SONET/SDH STS-48/STM-16 Framer/Pointer Processor Features q , Processors for STS-48/STM-16 and up to 4 x STS-12/STM-4 or 16 x STS-3/STM-1s. Serial STS-12/STM-4 and STS , Supports parallel STS-48/STM-16 or serial 4xSTS-12/STM-4 or serial 16xSTS-3/STM-1 inputs. Provides a single STS-48/STM-16 output. Pointer Processors for all valid input combinations of STS-48c/ AU , Supports a single STS-48/STM-16 input. Provides parallel STS-48/STM-16, serial 4xSTS-12/STM-4 or serial
Applied Micro Circuits
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S3076 S4806 S1208 S-G16 STS-12/STS-3

PEB1757AE

Abstract: GR-253-CORE PEB1757E TETHYSTM 2 STS-192/STM-64, 16 STS-48/STM-16, MUX/DEMUX MARCH 2008 REV. 1.0.2 , is optimized for SONET/SDH applications as a full-duplex two STS-192/STM64 or sixteen STS-48/STM-16 , , TethysTM PEB1757E accepts sixteen STS-48/STM-16 signals in serial 2.5 Gbit/s format. TethysTM PEB1757E , of STS-48/STM16 or STM-12/STM-4 or STS-3/STM-1 streams · Provides interfaces for dropping alarm , Provides 2 SFI4.1 interfaces for STS-192/STM-64 links · Provides serial STS-48/STM-16, STS-12/STM-4 or STS
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PEB1757AE Exar cross SDH ADM sfi4.1 STM64 multiplex STS48/ STS-48/STM16

TSOT1610GP-YB21

Abstract: MARS10G termination/generation: - On the line side SFI-4 interface: " One STS-192/STM-64 " Four STS-48/STM-16 - On the MARS10G TD-Pro system interface: " One STS-192/STM64 or " Four STS-48/STM-16 Path processing: - , -12/ STM-3s or a single STS-48/STM-16. - The TD-Pro system receive (drop) data path provides one 1 × 16/4 , ). 222 MARS10G T-Pro Backplane STS-48/STM-16 or STS-12/STM-4 Framing, Descrambling, and TOH , . 238 STS-48/STM-16 Processors
Agere Systems
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TSOT1610G TSOT1610GP-YB21 el12n 1724-pin TSOT1610GP 0AA00 TSOT1610GP/GPD DS02-154SONT DS03-065SONT

STS-192

Abstract: STM-64 for combining four STS-48/STM-16 data streams at the drop side interface into a single STS-192/STM , ANSI, Bellcore, and ITU specifications, 4x4 cross-connection of any of the STS-48/STM-16 data streams in both transmit and receive direction, enhanced buffer capabilities for de-skewing STS-48/STM-16 data streams, SONET/SDH section generation and termination of the STS-48/STM-16 drop signals, four 4 , -64 section/line overhead access of line interface data stream, dedicated ports for STS-48/STM-16 section
Vitesse Semiconductor
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VSC9116 BIMX192 stm-64 controller STS48/STM-16 STS192/STM-64 RISOP48 TLOP192 TSOP192

STM-64

Abstract: STM64 PHYSICAL LAYER PRODUCT TIMESTREAM® PRODUCT FAMILY VSC9186 VSC9186 Killington - Quad STS-48/STM-16 , SPLITTER/COMBINER MODE (DWDM): F E AT U R E S : 4Bidirectional Quad STS-48/STM-16 or STS-192/ STM , Quad Independent STS-48/ STM-16 or a Single STS-192/STM-64 4Pointer Processing of all Concatenation , local clock. The signal is crossconnected at the STS-1 level and then demultiplexed to four STS-48/STM-16 , bidirectional interfaces allow loopback of all four STS-48/STM-16 and the STS-192/ STM-64 interfaces
Vitesse Semiconductor
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STM64 XC2V1000-4FG256C RSLOP-48 RSLOP-192 TSLOP-48 TSLOP-192 BACKPLANE/OC-192

624-Pin

Abstract: S19202CBI30 single STS-192/STM-64 or quad STS-48/STM16 line interfaces on the line side and on the protection port. Each STS-48/STM-16 can support a concatenated payload or can be channelized down to STS-12c/AU , STS-48/STM-16. It supports framing, scrambling and descrambling, alarm signal insertion and detection , and receive directions. · Supports independent loop timing when in quad STS-48/ STM-16 mode. · , traffic type in SONET/SDH STS-192/ STM-64 and STS-48/STM-16 payloads · 16-bit synchronous
Applied Micro Circuits
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S19202CBI30 624-Pin hdlc S19202 622MH S3091/92

S8710

Abstract: s19203 between redundant core stage switches. · 48 x 48 serial STS-48/STM-16 or STS-12/STM-4 phase compensated , combinations of STS-48c/AU-416c, STS-12c/AU-4-4c, STS-3c/AU-4, or STS-1/AU-3 signals within an STS-48/STM-16 , , non-blocking architecture allowing any STS-Nc tributary from any of the STS-48/STM-16 serial-input streams to be switched to any STS-Nc tributaries in any of the STS-48/STM-16 serial-output streams. Any number , S8710 implements SONET/SDH framing and monitoring functions for up to 48 STS-48/STM-16 data streams. It
Applied Micro Circuits
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S8710PBGA s19203 STM-16 intel Architecture amcc 783 non-blocking STS-1 switching architecture AU-4-64c S3098 S3097 S19203

TMPRFE2G5

Abstract: MARS2G5 STS48/STM16 4 x STS12/STM4 4 x STS3/STM1 SONET/SDH Receive Path (RP) Mate Device P2S MATE_TP STMA_TP
Agere Systems
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TMPRFE2G5 MARS2G5 bey34 DIODE BA40 LVTTL25 STS48/STM16 DS04-011MPIC
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