STM6520 ID15953 AM00434 AM00435 AM00436 AM00437 AM00624 AM00625 JESD22-A114-B - Datasheet Archive

 

TM Smart Reset Dual push-button with push-button controlled output delay Features Dual Smart ResetTM push-button inputs, with

 

STM6520 STM6520 TM Smart Reset Dual push-button with push-button controlled output delay Features Dual Smart ResetTM push-button inputs, with user-selectable extended reset setup delay (by two-state input logic): tSRC = 6, 10 s (min.) Push-button controlled reset pulse duration (no fixed nor minimum pulse width guaranteed) No power-on reset Dual reset outputs ­ RST1 - active-low, open-drain ­ RST2 - active-high, push-pull Fixed Smart ResetTM input logic voltage levels Broad operating voltage range 1.65 V to 5.5 V, inactive reset output levels valid down to 1.0 V TDFN8 (DG) 2 mm x 2 mm Applications Mobile phones, smartphones Low supply current 1.5 µA e-books Operating temperature: ­30 °C to +85 °C MP3 players TDFN8 package: 2 mm x 2 mm x 0.75 mm Games RoHS compliant Portable navigation devices May 2010 Doc ID15953 ID15953 Rev 4 1/23 www.st.com 1 Contents STM6520 STM6520 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 Smart reset inputs (SR0, SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.4 User-selectable smart reset delay (DSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.5 Reset outputs (RST1, RST2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 Package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10 Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 12 Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/23 Doc ID 15953 Rev 4 STM6520 STM6520 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating and measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TDFN ­ 8-lead 2 x 2 x 0.75 mm, 0.5 mm package mechanical data . . . . . . . . . . . . . . . . . 15 Parameter for landing pattern - TDFN ­ 8-lead 2 x 2 mm package . . . . . . . . . . . . . . . . . . 16 Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Doc ID 15953 Rev 4 3/23 List of figures STM6520 STM6520 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. 4/23 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 RST1 output used for microcontroller reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 RST2 used for interrupting system power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Undervoltage condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply current (ICC) vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Smart reset delay (tSRC) vs. temperature, DSR = VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TDFN - 8-lead, 2 x 2 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Landing pattern - TDFN ­ 8-lead 2 x 2 mm without thermal pad . . . . . . . . . . . . . . . . . . . . 16 Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Package marking area, top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Doc ID 15953 Rev 4 STM6520 STM6520 1 Description Description The smart reset devices provide a useful feature that ensures inadvertent short reset pushbutton closures do not cause system resets. This is done by implementing extended smart reset input delay time (tSRC) and combined push-button inputs, which together ensures a safe reset and eliminates the need for a specific dedicated reset button. This reset configuration provides versatility and allows the application to discriminate between a software generated interrupt and a hard system reset. When the input pushbuttons are connected to microcontroller interrupt inputs, and are closed for a short time, the processor will only be interrupted. If the system still does not respond properly, continuing to keep the push-buttons closed for the extended setup time tSRC causes a hard reset of the processor through the reset outputs. The STM6520 STM6520 has two combined delayed smart reset inputs (SR0, SR1) with two userselectable delayed smart reset setup time (tSRC) options of 7.5 s and 12.5 s typ., selected by a dual-state smart reset DSR input pin. When DSR is connected to ground, tSRC = 7.5 s, when connected to VCC, tSRC = 12.5 s (typ.). There are two reset outputs, both going active simultaneously after both of the smart reset inputs were held active for the selected tSRC delay time. The outputs remain asserted until either or both inputs go to inactive logic level (for this device the output reset pulse duration is fully push-button controlled, meaning neither fixed nor minimum reset pulse width, nor power-on reset pulse is implemented). The first reset output, RST1, is active-low, open-drain; the second reset output, RST2, is activehigh, push-pull. The device fully operates over a broad VCC range 1.65 to 5.5 V. Below 1.575 V typ. the inputs are ignored and outputs are deasserted; the deasserted reset output levels are then valid down to 1.0 V. Figure 1. Logic diagram VCC SR0 RST1 STM6520 STM6520 SR1 RST2 DSR VSS Figure 2. AM00434 AM00434 Pin connections RST2 1 8 VCC VSS 2 7 SR0 SR1 3 6 NC RST1 4 5 DSR STM6520 STM6520 AM00435 AM00435 Doc ID 15953 Rev 4 5/23 Device overview 2 STM6520 STM6520 Device overview Table 1. Signal names Symbol Input/output RST1 Output First reset output, active-low, open-drain. RST2 Output Second reset output, active-high, push-pull. SR0 Input Primary push-button smart reset input. Active-low. SR1 Input Secondary push-button smart reset input. Active-low. Input A dual-state smart reset input delay selection pin. When connected to ground, tSRC = 7.5 s; when connected to VCC, tSRC = 12.5 s (typ.). DSR is a DC-type input, intended to be either permanently grounded or permanently connected to VCC. DSR Description VCC Positive supply voltage for the device. A 0.1 µF decoupling ceramic Supply voltage capacitor is recommended to be connected between VCC and VSS pins. VSS Supply ground Ground NC 6/23 No connect (not bonded; should be connected to VSS). Doc ID 15953 Rev 4 STM6520 STM6520 Pin descriptions 3 Pin descriptions 3.1 Power supply (VCC) This pin is used to provide power to the smart reset device. A 0.1 µF ceramic decoupling capacitor is recommended to be connected between the VCC and VSS pins. 3.2 Ground (VSS) This is the ground pin for the device. 3.3 Smart reset inputs (SR0, SR1) Push-button smart reset inputs, active-low. Both inputs need to be asserted simultaneously for at least tSRC to activate the reset outputs. 3.4 User-selectable smart reset delay (DSR) An input that allows the user to program the setup time (tSRC) for which both the pushbuttons need to be pressed to activate the reset outputs. Controlled by different voltage levels on the DSR pin: when connected to ground, tSRC = 7.5 s, when connected to VCC, tSRC = 12.5 s (typ.). DSR is a DC-type input, intended to be either permanently grounded or permanently connected to VCC. 3.5 Reset outputs (RST1, RST2) RST1 is active-low, open-drain, RST2 active-high, push-pull. Neither fixed nor minimum output reset pulse duration, nor power-on reset is implemented. Releasing any of the pushbuttons while reset outputs are active, will cause both outputs to deassert. Figure 3. SR0 Block diagram Smart reset logic SR1 tSRC Output logic RST1 RST2 DSR tSRC selector two-state logic Oscillator AM00436 AM00436 Doc ID 15953 Rev 4 7/23 Typical application diagram 4 STM6520 STM6520 Typical application diagram Figure 4. RST1 output used for microcontroller reset VBAT C1 0.1 µF STM6520 STM6520 DSR(1) RST2 SR0 SR1 RST1 Sys_Reset Reset Power_on Powerkey System ASIC MCU AM00440b 1. DSR pin (pin 5) must be tied to VCC or VSS. Figure 5. RST2 used for interrupting system power VBAT Regulator EN C1 0.1 µF System power output VSYS VSYS STM6520 STM6520 DSR(1) RST2 SR0 SR1 RST1 Sys_Reset Power_on Powerkey System ASIC MCU AM00439b 1. DSR pin (pin 5) must be tied to VCC or VSS. 8/23 Doc ID 15953 Rev 4 STM6520 STM6520 Typical application diagram Figure 6. Timing waveforms 1.65 V VBAT 1.65 V 1.0 V 1.0 V Start timer End Push-button timer controlled output N seconds SR0 Glitch immunity tSRC SR1 RST1 RST2 AM00437 AM00437 Figure 7. Undervoltage condition 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V Note: If undervoltage occurs (VCC drops below 1.575 V typ.) while reset outputs are active, both outputs are released and go inactive Doc ID 15953 Rev 4 9/23 Typical operating characteristics 5 STM6520 STM6520 Typical operating characteristics Figure 8. Supply current (ICC) vs. temperature 3 2.5 2 ICC [µA] 1.5 1 0.5 0 ­40 ­20 0 20 40 60 80 100 120 140 Temperature [°C] 5.5 V 3.3 V 2V AM00624 AM00624 Figure 9. Smart reset delay (tSRC) vs. temperature, DSR = VSS 9 8.5 8 tSRC [s] 7.5 7 6.5 6 ­40 ­20 0 20 40 60 80 100 120 140 Temperature [°C] 5.5 V 3.3 V 2V AM00625 AM00625 10/23 Doc ID 15953 Rev 4 STM6520 STM6520 6 Maximum rating Maximum rating Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 2. Absolute maximum ratings Symbol Value Unit ­55 to +150 °C 260 °C 149.0 °C/W ­0.3 to VCC+0.3 V ­0.3 to 7 V Electrostatic discharge protection, human body model, all pins (JESD22-A114-B JESD22-A114-B level 2) 2 kV VRCDM Electrostatic discharge protection, charged device model, all pins 1 kV VMM Electrostatic discharge protection, machine model, all pins (JESD22-A115-A JESD22-A115-A level A) 200 V TSTG Parameter Storage temperature (VCC off) TSLD(1) Lead solder temperature for 10 seconds JA Thermal resistance (junction to ambient) VIO Input or output voltage VCC Supply voltage TDFN8 ESD VHBM Latch-up (VCC pin, reset input pins) EIA/JESD78 EIA/JESD78 1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds. Doc ID 15953 Rev 4 11/23 DC and AC parameters 7 STM6520 STM6520 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics table that follow, are derived from tests performed under the Measurement Conditions summarized in Table 3: Operating and measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 3. Operating and measurement conditions Parameter Value Unit VCC supply voltage 1.65 to 5.5 V Ambient operating temperature (TA) ­30 to +85 °C 5 ns Input pulse voltages 0.2 to 0.8 VCC V Input and output timing ref. voltages 0.3 to 0.7 VCC V Input rise and fall times Figure 10. AC testing input/output waveforms 0.8 VCC 0.2 VCC 12/23 Doc ID 15953 Rev 4 0.7 VCC 0.3 VCC AM00478 AM00478 STM6520 STM6520 Table 4. DC and AC parameters DC and AC characteristics Symbol Parameter VCC Supply voltage range ICC Supply current Test conditions(1) Operating voltage(2) Min. Typ. Units 5.5 1.65 Max. V 2.5 µA VCC = 5.0 V 2 3 µA 0.3 V VCC 3.3 V, sinking 2.5 mA 0.3 V VCC 1.65 V, sinking 1 mA Reset output voltage low 1.5 VCC 4.5 V, sinking 3.2 mA VOL VCC = 3.0 V 0.3 V VCC 4.5 V, ISOURCE = 0.8 mA ILO Reset output voltage high Output leakage current, RST1 V VCC 2.7 V, ISOURCE = 0.5 mA 0.8 VCC V VCC 1.65 V, ISOURCE = 0.25 mA 0.8 VCC VOH 0.8 VCC V Open-drain, VRST1 = 5.5 V ­0.1 0.1 µA Smart reset tSRC Smart reset delay DSR = VSS 6 7.5 9 s DSR = VCC 10 12.5 15 s VIL SR0, SR1 input voltage low VSS ­ 0.3 0.3 V VIH SR0, SR1 input voltage high 0.85 VCC + 0.3 V ILI Input leakage current (SR0, SR1, DSR pins) ­1 1 µA Input glitch immunity Corresponds to the actual tSRC tSRC s 1. Valid for ambient operating temperature: TA = ­30 to +85 °C; VCC = 1.65 to 5.5 V (except where noted). 2. Reset outputs are deasserted below 1.575 V typ. and will remain deasserted down to VCC = 1 V. Doc ID 15953 Rev 4 13/23 Package mechanical data 8 STM6520 STM6520 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 11. TDFN - 8-lead, 2 x 2 mm package outline D A B PIN 1 INDEX AREA E 0.10 C 2x 0.10 C 2x TOP VIEW 0.10 C C A1 A SEAT ING PLANE SIDE VIEW 0.08 C e b PIN 1 INDEX AREA 1 4 0.10 C A B Pin#1 ID L 5 8 BOTTOM VIEW 8070540_A 14/23 Doc ID 15953 Rev 4 STM6520 STM6520 Package mechanical data Table 5. TDFN ­ 8-lead 2 x 2 x 0.75 mm, 0.5 mm package mechanical data Dimension (mm) Dimension (inches) Symbol Min. Nom. Max. Min. Nom. Max. A 0.70 0.75 0.80 0.028 0.030 0.031 A1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.15 0.20 0.25 0.006 0.008 0.010 D BSC 1.9 2.00 2.1 0.075 0.079 0.083 E BSC 1.9 2.00 2.1 0.075 0.079 0.083 e L 0.50 0.45 0.55 0.020 0.65 Doc ID 15953 Rev 4 0.018 0.022 0.026 15/23 Package footprint 9 STM6520 STM6520 Package footprint Figure 12. Landing pattern - TDFN ­ 8-lead 2 x 2 mm without thermal pad D P E E1 L b Table 6. AM00441 AM00441 Parameter for landing pattern - TDFN ­ 8-lead 2 x 2 mm package Dimension (mm) Parameter Description Min. Nom. Max. L 1.05 - 1.15 b Contact width 0.25 - 0.30 E Max. land pattern Y-direction - 2.75 - E1 Contact gap spacing - 0.65 - D Max. land pattern X-direction - 1.75 - P 16/23 Contact length Contact pitch - 0.5 - Doc ID 15953 Rev 4 STM6520 STM6520 10 Tape and reel information Tape and reel information Figure 13. Carrier tape P0 D P2 T E A0 F Top cover tape W B0 Center lines of cavity K0 P1 User direction of feed AM03073v2 Table 7. Carrier tape dimensions Package W D TDFN8 8.00 +0.30 ­0.10 1.50 +0.10/ ­0.00 E P0 P2 F 1.75 4.00 2.00 3.50 ±0.10 ±0.10 ±0.10 ±0.05 A0 B0 K0 P1 T 2.30 ±0.05 2.30 ±0.05 1.00 ±0.05 4.00 ±0.10 0.250 ±0.05 Doc ID 15953 Rev 4 Unit Bulk qty. mm 3000 17/23 Tape and reel information STM6520 STM6520 Figure 14. Reel dimensions T 40 mm min. acces hole at slot location B D C N A Full radius Tape slot in core for tape start 25 mm min width G measured at hub AM00443 AM00443 Table 8. Reel dimensions Tape sizes B min. C D min. N min. G T max. 8 mm 18/23 A max. 180 (7 inches) 1.50 13.0 +/­ 0.20 20.20 60 8.4 +2/­0 14.40 Doc ID 15953 Rev 4 STM6520 STM6520 Tape and reel information Figure 15. Tape trailer/leader End Top cover tape Start No components Components 100 mm min. T RA IL ER No components L EA D ER 160 mm min. 400 mm min. Sealed with cover tape User direction of feed AM00444 AM00444 Figure 16. Pin 1 orientation User direction of feed Note: 1 Drawings are not to scale. 2 AM00442 AM00442 All dimensions are in mm, unless otherwise noted. Doc ID 15953 Rev 4 19/23 Ordering information 11 STM6520 STM6520 Ordering information Table 9. Ordering information scheme Example: STM6520 STM6520 A Q R R DG 9 F Device type STM6520 STM6520 Reset (VCC monitoring threshold) voltage VRST A = no VCC monitoring feature Smart reset setup delay (tSRC) Q = 7.5 or 12.5 s typ., user-selected (two-state); input comparator on SR0, SR1, no input pull-ups Outputs type R = RST1 active-low, open-drain, no pull-up; RST2 active-high, push-pull Reset pulse timeout period (tREC) R = push-button controlled (no defined tREC, no power-on reset) Package DG = TDFN8 2 x 2 x 0.75 mm, 0.5 mm pitch Temperature range 9 = ­30 °C to +85 °C Shipping method F = ECOPACK® package, tape and reel For other options, voltage threshold values etc. or for more information on any aspect of this device, please contact the ST sales office nearest you. 20/23 Doc ID 15953 Rev 4 STM6520 STM6520 12 Package marking information Package marking information Table 10. Package marking Part number Package Topmark STM6520AQRRDG9F STM6520AQRRDG9F TDFN8 2 x 2 x 0.75 mm, 0.5 mm pitch DRM Figure 17. Package marking area, top view A B C D E Topmark A = dot (pin 1 reference) B = assembly plant (P) C = assembly year (Y, 0-9): 9 = 2009 etc. D = assembly work week (WW, 01 to 52): 20 = WW20 etc. E = marking area (topmark) AM00479 AM00479 Doc ID 15953 Rev 4 21/23 Revision history 13 STM6520 STM6520 Revision history Table 11. Document revision history Date 08-Jul-2009 1 Initial release. 20-Oct-2009 2 Document reformatted, updated Section 1: Description, Table 1, Figure 4, Figure 5, Table 4, renamed Section 2: Device overview, added Section 5: Typical operating characteristics, updated supply voltage range in Table 4. 20-Jan-2010 3 Updated Section 1: Description, Table 1. 06-May-2010 22/23 Revision Changes 4 Updated title, Features, Applications, Table 5. Doc ID 15953 Rev 4 STM6520 STM6520 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 15953 Rev 4 23/23