STM16 OM5801 AN96051 CQF910/D OQ2541 OQ2535 OQ2545 CREF19 OQ2536 CIC100 OQ2538 - Datasheet Archive

 

Fiber optic transceiver demo board STM16 OM5801 AN96051 Philips Semiconductors Philips Semiconductors OM5801 Application Note

 

APPLICATION NOTE Fiber optic transceiver demo board STM16 STM16 OM5801 OM5801 AN96051 AN96051 Philips Semiconductors Philips Semiconductors OM5801 OM5801 Application Note AN96051 AN96051 2 Philips Semiconductors Fiber optic transceiver demo board STM16 STM16 Application Note AN96051 AN96051 APPLICATION NOTE Fiber optic transceiver demo board STM16 STM16 OM5801 OM5801 AN96051 AN96051 Author: Marcel J.M. Geurts Product Concept & Application Laboratory Eindhoven, The Netherlands Keywords Telecom Optical networks SDH/Sonet STM16 STM16 OC48 CML Noise immunity Low Power Balanced Built in loop ITU Date: 1st august 1996 1 Philips Semiconductors OM5801 OM5801 Application Note AN96051 AN96051 2 Philips Semiconductors Application Note Abstract The STM16 STM16 fiber optic frontend chipset is capable of transmitting and receiving 32 digital channels simultaniously over one fiber optic link. The low side datarate is 78 Mbps, the high side datarate is 2448 Mbps. The chipset consists of a multiplexer, laserdriver, transimpedance amplifier, main amplifier, clock recovery, clock multiplier and demultiplexer. The main advantage of the chipset is the use of Current Mode Logic interface for the high rate channels. This guarentees low power consumption combined with high interference immunity. Furthermore the chipset has a built in loop capability: received signals can directly be fed to the laser driver, and multiplexed signals can directly be demultiplexed. This feature simplifies testing during production and maintenance. The demoboard can be used for system and IC evaluation. Additional guard circuits for operational conditions have been implemented. © Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. 1 Philips Semiconductors Application Note INTRODUCTION This application note describes the use of the Philips' STM16 STM16 chipset. First general items are discussed, interfaces are described. After this, the functional blocks are discussed. Finally the evaluation results of key characteristics of the board are given. The schematics, layout, partslist, manufacturer data and the lenghts of critical lines are given in the appendices. Also the use of Current Mode Logic is explained in an appendix. 2 Philips Semiconductors Application Note Contents 1. General . . . . . . . . . . . . 1.1 Goal. . . . . . . . . . 1.2 Acronyms . . . . . . . 1.3 Layout considerations 1.4 Optical components . 1.5 ITU recommendations . . . . . . . . . . . . 2. Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1 Interface description list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 3. Multiplexer . . . . . . . . . . . 3.1 Block diagram . . . . . 3.2 Circuit setup . . . . . . 3.3 Layout . . . . . . . . . 3.4 Operational information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-1 3-1 3-3 3-3 4. Laserdriver . . . . . . . . . . . . . . 4.1 Block diagram . . . . . . . . 4.2 Circuit setup . . . . . . . . . 4.3 Layout . . . . . . . . . . . . 4.4 Alignment procedure . . . . . 4.4.1 Bias setting . . . . 4.4.2 Modulation setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-1 4-1 4-2 4-2 4-2 4-3 5. Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Block diagram . . . . . . . . . . . . . . . . . . . 5.2 Circuit setup . . . . . . . . . . . . . . . . . . . . 5.2.1 Photo diode bias monitor and guard . . 5.2.2 Calculations for photo diode bias guard. 5.2.3 Matlab program . . . . . . . . . . . . . 5.2.4 Matlab program output . . . . . . . . . 5.2.5 Example setting APD guard. . . . . . . 5.2.6 Electrical input. . . . . . . . . . . . . . 5.2.7 Offset control loop. . . . . . . . . . . . 5.2.8 LOS detection . . . . . . . . . . . . . . 5.2.9 Level detection . . . . . . . . . . . . . 5.2.10 Photodiode bias . . . . . . . . . . . . . 5.2.11 Transimpedance amplifier. . . . . . . . 5.2.12 Noise lowpass filter . . . . . . . . . . . 5.3 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 . 5-1 . 5-1 . 5-1 . 5-2 . 5-4 . 5-6 . 5-6 . 5-9 . 5-9 . 5-9 . 5-9 . 5-9 . 5-9 5-10 5-10 6. Data and clock recovery . . . . . . . . . . 6.1 Block diagram . . . . . . . . . . . . 6.2 Circuit setup . . . . . . . . . . . . . 6.3 Layout . . . . . . . . . . . . . . . . 6.4 Operational information . . . . . . . . 6.4.1 Reference oscillator signal 6.4.2 Phase Detector Output . . 6.4.3 Loss Of Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-1 1-1 1-3 1-3 1-3 6-1 6-1 6-1 6-2 6-2 6-2 6-3 6-3 Philips Semiconductors Application Note 6.4.4 6.4.5 6.4.6 6.4.7 Output Amplitude Reference . . . Global frequency acquisition (FLL) LOCK signal. . . . . . . . . . . . Data recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6-3 6-3 6-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-1 7-1 7-2 7-2 7. Demultiplexer . . . . . . . . . 7.1 Block diagram . . . . . 7.2 Circuit setup . . . . . . 7.3 Layout . . . . . . . . . 7.4 Operational information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8. Evaluations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Possible modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1 Normal mode, measurements at optical side . . . . . . . . . . 8.1.2 Normal mode, measurements and generation at 78 Mbps side 8.1.3 Optical loop mode: transmitter measurement . . . . . . . . . . 8.1.4 Optical loop mode: receiver measurement . . . . . . . . . . . 8.1.5 Electrical loop mode: high data rate input. . . . . . . . . . . . 8.1.6 Electrical loop mode: lowdata rate input . . . . . . . . . . . . 8.2 Performance measurements . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.1 Receiver transfer . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2 Bit Error Rate versus input power . . . . . . . . . . . . . . . . 8.3.3 Eye diagram of transmitted signals . . . . . . . . . . . . . . . 8.4 Measurement results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.1 Receiver transfer . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 Bit Error Rate versus input power . . . . . . . . . . . . . . . . 8.4.3 Eye diagram of transmitted signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 . 8-1 . 8-2 . 8-3 . 8-4 . 8-5 . 8-6 . 8-7 . 8-7 . 8-9 . 8-9 . 8-9 8-10 8-12 8-12 8-14 8-16 2 Philips Semiconductors 1. General 1. Application Note General 1.1 Goal The demoboard has been designed to demonstrate the capability of the Philips' STM16 STM16 chip set, designed for SDH or SONET systems, bitrate: 2.5 Gbps. The board has been set up such that individual evaluation of each IC is possible, with an exception for the transimpedance amplifier. No attempts have been made to design advanced peripheral circuitry: · The power supplies are therefore simple, discrete DC voltage regulators. · Standard a temperature stabilized laser must be mounted. A Peltier temperature stabilizing loop is included. Modulation control is a fixed setting. · A laser bias control is included. · A simple 2 state photo diode guard circuit is included in the board. The transition voltage and -current can be adjusted. 1.2 Acronyms · If a text is placed between quotes, this text is placed on layer 1 (top) of the demoboard. · On all places where STM16 STM16 (SDH) also OC48 (SONET) can be read · 19 MHz 19,440 kHz · 19 Mbps 19,440 kbps · 2.5 GHz 2,488,320 kHz · 2.5 Gbps 2,488,320 kbps · 2G5 2.5 GHz · 39 MHz 38,880 kHz · 39 Mbps 38,880 kbps · 78 MHz 77,760 kHz · 78 Mbps 77,760 kbps · AGC Automatic Gain Control · AGC Automatic Gain Control, signal output · AGCDC Automatic Gain Control, reference output · ALS Automatic Laser Shutdown · APD Avalanche Photo Diode · BTL Backplane Transceiver Logic · BW Bandwidth · Buf Buffer · CLK Clock · CML Current Mode Logic · CREF Reference clock · Conv Converter (for conversion of 622 MHz clock to 2.5 GHz) · Cu Copper 1-1 Philips Semiconductors 1. General Application Note · DCR Data and Clock Recovery · EL Electrical · EXT External · ITU International Telecommunication Union · JUMA Jumper A · JUMB Jumper B · JUMC Jumper C · LAB Buffered laser output · LAQ Inverted laser output · LDR Laser driver · LOS Los Of Signal (main amplifier), signal output · LOSDC Los Of Signal (main amplifier), reference output · MS Microstrip · MUX Multiplexer · N4V5 -4.5 Volt · N6V5 -6.5 Volt · OP Optical · Op1 Optical connector no. 1 (Output) · Op2 Optical connector no. 2 (Input) · P3V3 +3.3 Volt · P5V +5 Volt · PCB Printed Circuit Board · PLL Phase Locked Loop · PRBS Pseudo Random Bit Sequence · RCV Receiver · REF Reference · RF Radio Frequency, in this document 2.5 Gbps data 2.5 GHz clock signals · SDH Synchronous Digital Hierarchy · SMD Surface Mount Devices · SONET Synchronous Optical Networks · STM16 STM16 Synchronous Transport Module no. 16 · TRL Transmission Lines · TTI Transistor buffered Transimpedance output · TTL Transistor Transistor Logic · Te Ternary · Transimp Transimpedance · bps bits per second 1-2 Philips Semiconductors 1. General 1.3 Application Note Layout considerations · The layout for the demoboard is designed on a 8 layer PCB. The layers are 35 micrometer thick, the space between two layers is 0.2 ± 0.02 mm, the thickness of a carrier layer is 0.2 ± 0.038 mm. The material is FR4, with a relative dielectric constant is 4.3. No buried vias are used. The used layout process has an underetching for all but outer layers of 20 micrometer. The use of layers is ordered as follows: layer 1 layer 2 layer 3 layer 4 layer 5 layer 6 layer 7 layer 8 Signal; Microstrip transmission lines (Single ended: 1 mm width; Coupled: 0.35 mm width / 0.15 mm spacing) Signal; Local ground; Where microstrip transmission lines are placed on layer 1: nothing Global ground. At RF parts no thermal releases are used VEE (N4V5); Signal; Where triplate transmission lines are placed on layer 5: nothing Triplate transmission lines (Single ended: 0.3 mm; Coupled: 0.25 mm width / 0.25 mm spacing) VCC (P5V; P3V3). Where triplate transmission lines are placed on layer 5: nothing Global ground. At RF parts no thermal releases are used Signal A schematic view is drawn on the next page. · The microstrip transmission lines and triplate transmission lines are guarded with vias, to enhance interference immunity. The spacing is 1 mm minimum between line and via. No thermal releases were made in this vias. · All positive power lines and ground are 1 mm wide. All negative power lines 2 mm. The width has also been used for those lines on layer 1 and 8. · The RF decoupling capacitors are placed as close as possible to the ICs. · The loading of the ICs has been layed out as symmetrical as possible. · Whenever necessary the 50 ohms lines were placed in the triplate layer. · The SMA connectors have been placed with a 20 mm centre distance apart from each other. This gives enough space to properly connect the SMA connectors with a torque key. 1.4 Optical components Standard, the board is delivered with a 1550 nm Distribueted Feedback (DFB) Laser and Ternary avalanche diode. The manufacturer and type numbers are: Laser: Diode: 1.5 Philips Optoelectronics Centre - CQF910/D CQF910/D ATT- ATT 127E ITU recommendations ITU recommendations G.957 and G.958 apply to the chipset described in this document. 1-3 Philips Semiconductors 1. General Application Note Build up of multilayer PCB TOP Layer 1 Units: µm Signal, (MS single: 1000) (MS differential: W=350, Clearance = 150) 17.5 + 3/-5 Cu 200 ±38 200 ±20 Layer 2 Signal, local ground 35 + 3/-5 Cu 200 ±38 Layer 3 GND 35 + 3/-5 Cu 200 ±20 Layer 4 N4V5, local supply, Signal 35 + 3/-5 Cu 200 ±38 Layer 5 35 + 3/-5 Cu TRL: W=250, Clearance = 250) 200 ±20 Layer 6 P5V,P3V3 35 + 3/-5 Cu 200 ±38 Layer 7 GND 35 + 3/-5 Cu 200 ±20 200 ±38 Layer 8 Signal 17.5 + 3/-5 Cu MS = Microstrip transmission line TRL= Triplate transmission line BOTTOM 1-4 Philips Semiconductors FUNCTIONAL BLOCK DIAGRAM STM16 STM16 DEMOBOARD x4 CLK CONV in 622 MHz MUX CLK in 2.5 GHz JUMC 32 JUMB 78 Mbps 78 MHz Application Note OQ2541 OQ2541 STM16 STM16 Outputs 2.5 GHz LAB SIMOD 32 : 1 Mux clock clock Laserdriver LAB OQ2535 OQ2535 data OQ2545 OQ2545 LA data Op1 peltier RCV-DCR I/O ALS LASER_EAM OPT _DCR OPT_LDR 4x PI CREF19 CREF19 CLK out 78 MHz DMUX 4x OL (Optical Loop) EL_DMUX 78 MHz MUX CLK out EL (Electrical Loop) EL_MUX DMUX_LS (BTL/TTL out) SIBIAS 1550 nm Temp Stabilized DFB Laser Temperature Control STM 16 Inputs 78 MHz JUMB JUMA 32 1 : 32 Dmux 78 Mbps OQ2536 OQ2536 LOS LOS Detection data data clock clock Transimp + Main Amp CIC100 CIC100 OQ2538 OQ2538 Data & Clock Recovery OQ2541 OQ2541 DCR_LOCK DCR_LOS Offset Photo diode bias + guard EXT REF Input_Level Ext 19 or 39 MHz C39_EN +8V GND Power Supply -8V JUMB Input_Level DCR_LOCK LOS_DCR LOS Dip switches OPT DCR EL DMUX DCR at 19 MHz 39 MHz XTAL EAM/LASER BTL/to MUX OPT EL CONV ALS - Op2 39 MHz OSC Signal Names OPT_DCR~ EL_DMUX~ LOS_DCR LOS_D CREF19 CREF19 C39_EN EAM_LASER MUX_LS DMUX_LS OPT_LDR~ EL_MUX~ CONV_ON~ ALS LOCK CONV_LOCK 1 EL in LEVEL LEDs OPT DCR EL DMUX LOS-DCR LOS DCR at 19 MHz 39 MHz XTAL on LASER EAM DMUX to MUX at BTL OPT LDR EL MUX Conv on ALS DCR-lck Conv-lck + Photo diode bias voltage - Philips Semiconductors Application Note 2. 2.1 Interface Interface description list TABLE 1 SMA Connectors Name Portno. EL-CLK-OUT ST621 ST621 EL-CLK-OUT ST622 ST622 EL-DATA-OUT ST623 ST623 EL-DATA-OUT ST624 ST624 EL-CLK-IN ST625 ST625 EL-CLK-IN ST626 ST626 EL-DATA-IN ST627 ST627 EL-DATA-IN ST628 ST628 OL-CLK-OUT ST631 ST631 OL-CLK-OUT ST632 ST632 OL-DATA-OUT ST633 ST633 OL-DATA-OUT ST634 ST634 OL-CLK-IN ST635 ST635 OL-CLK-IN ST636 ST636 OL-DATA-IN ST637 ST637 OL-DATA-IN ST638 ST638 I/O ST642 ST642 I/O ST641 ST641 LA ST651 ST651 LAB ST652 ST652 LAB ST653 ST653 78 MHz DMUX CLK out ST661 ST661 Netname EL_CLK_OUT EL_CLK_OUT~ EL_DATA_OUT EL_DATA_OUT~ EL_CLK_IN EL_CLK_IN~ EL_DATA_IN EL_DATA_IN~ OL_CLK_OUT OL_CLK_OUT~ OL_DATA_OUT OL_DATA_OUT~ OL_CLK_IN OL_CLK_IN~ OL_DATA_IN OL_DATA_IN~ RCV_DCR_I_O RCV_DCR_I_O~ LA~ LAB LAB~ C78R_BTL I/O O O O O I I I I O O O O I I I I I/O I/O O O O O 78 MHz MUX CLK out ST662 ST662 C78T_BTL O EXT REF EL in Conv in MUX CLK in ST671 ST671 ST672 ST672 ST673 ST673 DT674 DT674 CREF EL_IN CLK_CONV_IN CMUX_IN I I I I TABLE 2 Dipswitches and LEDs Dipswitch Line LED no OPT DCR OPT_DCR~ OT611 OT611 EL DMUX EL_DMUX~ OT612 OT612 LOS_DCR OT622 OT622 LOS_D OT621 OT621 DCR at 19 MHz CREF19 CREF19 OT632 OT632 LED name OPT DCR EL DMUX LOS-DCR LOS DCR at 19 MHz 2 Description Electrical loop clock output, CML Electrical loop clock output, CML, inverted Electrical loop data output, CML, Electrical loop data output, CML, inverted Electrical loop clock input, CML Electrical loop clock input, CML, inverted Electrical loop data input, CML Electrical loop data input, CML, inverted Optical loop clock output, CML Optical loop clock output, CML, inverted Optical loop data output, CML Optical loop data output, CML, inverted Optical loop clock input, CML Optical loop clock input, CML, inverted Optical loop data input, CML Optical loop data input, CML, inverted Attenuated path signal-path RCV-DCR Attenuated path signal-path RCV-DCR Inverted laser driver output Buffered laser driver monitor output Buffered laser driver monitor output, inverted Received 78 MHz clock - 50 ohm source Transmit 78 MHz clock - 50 ohm source (Derived from Mulitplexer/converter clock) External 19 MHz or 38 MHz reference clock for DCR Electrical input Converter clock(622 MHz) Multiplexer clock (2.5 GHz) Colour Yellow Yellow Red Red Yellow Description DCR in optical loop mode DMUX in electrical loop mode LOS detected by DCR LOS detected by main RCV DCR is in 19 MHz reference clock mode Philips Semiconductors Application Note TABLE 2 Dipswitches and LEDs Dipswitch Line LED no 39 MHz XTAL C39_EN OT631 OT631 EAM/LASER EAM_LASER OT642 OT642 OT641 OT641 LED name 39 MHz XTAL on LASER EAM Colour Yellow Yellow Yellow BTL/to MUX MUX_LS OT651 OT651 DMUX to MUX Yellow OPT EL CONV ALS - DMUX_LS OPT_LDR~ EL_MUX~ CONV_ON~ ALS LOCK CONV_LOCK OT652 OT652 OT601 OT601 OT602 OT602 OT603 OT603 OT604 OT604 OT623 OT623 OT624 OT624 at BTL OPT LDR EL MUX Conv on ALS DCR lck Conv lck Yellow Yellow Yellow Yellow Yellow Green Green TABLE 3 I/O Jumpers Name Portno Line JUMA1 ST601 ST601 D_C78RBUS C78RBUS JUMA2 ST602 ST602 D_C78RBUS C78RBUS JUMA3 ST603 ST603 D_C78RBUS C78RBUS JUMA4 ST604 ST604 D_C78RBUS C78RBUS LEVEL LOS_DCR LOS_D JUMB ST609 ST609 LOCK C78TB C78TB C78RB C78RB JUMC1 JUMC2 JUMC3 JUMC4 ST605 ST605 ST606 ST606 ST607 ST607 ST608 ST608 D_C78TBUS C78TBUS D_C78TBUS C78TBUS D_C78TBUS C78TBUS D_C78TBUS C78TBUS Description Board crystal oscillator is on LDR in in Laser mode LDR is in EAM mode Enables MUX/DMUX communication possiblitie (amplitude only, needs extra level shift) DMUX is in `BTL' mode LDR is in optical loop mode MUX is in electrical loop mode Clock converter is enabled Automatic Laser shutdown is enabled DCR is in lock Clock convertor is in lock Level BTL BTL BTL BTL Description Received data, bits 0-7 Received data, bits 8-15 Received data, bits 16-23 Received data, bits 24-31 Analog TTL TTL TTL TTL TTL Input level detektor (main amp) output signal. Buffered Loss of signal from DCR Loss of signal from RCV Lock output DCR 78 MHz transmitted data clock 78 MHz received data clock Transmitted data, bits 0-7 (threshold input comperators 1.5 V) Transmitted data, bits 8-15 (threshold input comperators 1.5 V) Transmitted data, bits 16-23 (threshold input comperators 1.5 V) Transmitted data, bits 24-31 (threshold input comperators 1.5 V) TTL TTL TTL TTL TABLE 4 Control jumpers/PADs Portno Name Description Closing this jumper will close the bias loop of RCV and DCR. ST212 ST212 RCV-DCR bias ST202 ST202 should be left open. Closing this jumper will close the bias network at the receiver. ST213 ST213 RCV bias ST201 ST201 should be left open. 5V bias enabling ST281 ST281 5V Diode bias Enables the use of 5 V for photo diode bias. The APD bias voltage input pins should be left open 3 Philips Semiconductors Application Note TABLE 4 Control jumpers/PADs Portno Name Description Laser bias adjustment. R820 Laser bias By adding a resistor to this point, the laser bias current can be controlled Laser Laser modulation adjustment. R857 modulation By adding a resistor to this point, the laser modulation current can be controlled. TABLE 5 M-no. Voltage, signal M1 P8V M2 N8V M11 P5V M12 P5V M13 P5V M14 P5V M15 P8V M21 P3V3 M22 P3V3 M24 P3V3 M25 P8V M31 N4V5 M32 N4V5 M33 N4V5 M34 N4V5 M35 N4V5 M41 N6V5 M42 N6V5 M43 N6V5 M44 N6V5 M45 N6V5 M202 M203 M204 M206 MC_VREF M207 M209 M210 M211 M241 UPH_KAP M242 EL_IN M303 U_PH M343 Description +8 V -8 V +5 V +5 V +5 V +5 V +8 V +3.3 V +3.3 V +3.3 V +8 V -4.5 V -4.5 V -4.5 V -4.5 V -4.5 V -6.5 V -6.5 V -6.5 V -6.5 V -6.5 V REF (pin 21) Main Amplifier IC202 IC202 (pin 1), differential amplifier output LOS detector IC203 IC203 (pin 5), switch level LOS detector Reference voltage IC203 IC203 (pin 7), output level of LOS dectector LEVEL detector output signal (equal to JUMB, pin 1) IC204 IC204 (pin 7), differential amplifier output LEVEL detector DC voltage a offset DC bias voltage of photo diode Electrical input Photo diode bias voltage, after guard circuit IC304 IC304 (pin 6), guard circuit voltage measurement opamp output 4 Philips Semiconductors Application Note TABLE 5 M-no. Voltage, signal M401 M207 M403 M504 M508 M516 LOCK M517 M592 VEE_DCR M594 M595 M596 M598 M701 M751 M752 M754 M755 M758 CONV_LOCK M831 M832 M834 M835 M901 P8V M902 P8V M903 P8V M904 N8V M905 N8V M906 N8V Description IC400 IC400 (pin 32), demultiplexer, Diode-anode IC400 IC400 (pin 33), output level of LOS dectector IC400 IC400, (pins 13,14,36,37,63,85,86), demultiplexer VTT input -3.3 V supply voltage Data and Clock recovery IC400 IC400 (pin 48), AREF, (0.5 x output level voltage) DCR IC400 IC400 (pin 12), LOCK, (VCO is at 2488320 kHz) IC400 IC400 (pin 37), PC, power supply control signal IC400 IC400, VEE, -3.3 V Input voltage power supply regulator, IC400 IC400, DCR Input voltage power supply regulator, IC400 IC400, DCR T551 emitter voltage (power supply regulator, IC400 IC400, DCR) T552 emitter voltage (power supply regulator, IC400 IC400, DCR) IC701 IC701 (pin 74), diode-anode Converteroutput signal Converter output signal, inverted IC751 IC751 (pin 48), AREF, (0.5 x output level voltage) Conv IC751 IC751, -3.3 V IC751 IC751 (pin 12), LOCK, (VCO is at 2488320 kHz) Laser bias alignment, signal side Laser bias alignment, reference side - input PI control opamp laser bias loop Laser driver temperature monitor (diode), anode side. +8 V +8 V +8 V -8 V -8 V -8 V 5 Philips Semiconductors Application Note 6 Philips Semiconductors 3. Multiplexer Block diagram x4 CLK CONV in 622 MHz MUX CLK in 2.5 GHz JUMB 32 78 Mbps 78 MHz 32 : 1 Mux clock OQ2535 OQ2535 data 78 MHz MUX CLK out 3.2 2.5 GHz EL_MUX JUMC OQ2541 OQ2541 EL (Electrical Loop) 3.1 Multiplexer DMUX_LS (BTL/TTL out) 3. Application Note 4x Circuit setup The multiplexer block consists of the following circuits: -Multiplexer, OQ2535A OQ2535A, (IC701 IC701) -Clock converter OQ2541C3 OQ2541C3 (IC751 IC751). -78 MHz clock buffer The multiplexer and clock converter are drawn on schematics page "OTM/1.drw", the buffer is drawn on page "CONNECTORS/2.drw". The schematics can be found in appendix 1, "Schematics". The multiplexer is connected as in the datasheet. The boundary scan inputs are not used, and are pulled up internally. The input level threshold can be modified slightly by sinking current out of pin 38. This possibility can be turned on by turning T719 on through MUX_LS. The signal is controlled by switch S635-4 S635-4,5 "BTL/to MUX". LED OT651 OT651 "DMUX to MUX' will light up when active. The data inputs are directly connected to connectors JUMC1.4. The selection of the output path (either "normal" or "Electrical loop") is done by signal EL_MUX~ (active low). EL_MUX~ is controlled by switch S601-7 S601-7,2 "EL". When enabled, OT602 OT602 "EL-MUX" will light up. Mind that the same control switch is used to modify the demultiplexer output voltages. Selection which ICs will be controlled is implemented by mounting a FET on the appropriate place. Either T719 (multiplexer) or T459 (demultiplexer). The multiplexer needs a 2.5 GHz clock. The clock can either be applied to connector ST674 ST674, "MUX CLK in" as a 2.5 GHz signal, or as 622 MHz signal to connector ST673 ST673, "CONV in". The 622 MHz signal is multiplied by 4 in IC751 IC751, a OQ2541C3 OQ2541C3 setup in transmit mode. In order to avoid transport of the clock signal over a jumper, a combiner has been used for the selection of the signal source. Therefore, only one clock source should be active at the same time. The layout details of the combiner are shown on the next page. 3-1 Philips Semiconductors 3. Multiplexer Application Note The power supply filtering is so dimensioned that the quality factor of the used components is low. This guarentees no oscillation when the transmitted data contains frequency components at the resonance frequency of the power supply filters. S1,C1,C2: from Conv Zo=50 MUX CLK in Zo=50 x+/2 S1 100 x C2 C1 Zo=71 L=/4 to Mux (a) Zo=50 (b) oq2541 (in clock conversion mode) from Conv C2 S1 x+/2 bottom top C1 to Mux (c) (d) Fig.1 Used splitter circuits and layouts. The 2.5 GHz Multiplex clock signal can be taken from either the MUX CLK in connector or the converted 622 MHz signal. In order to avoid transport of the clock signal over a jumper, a combiner has been used for the selection of the signal source. Therefore, only one clock source should be active at the same time.The two signals are combined in two Wilkinson combiners C1 and C2. The 2.5 GHz signal is made differential by splitting it in a Wilkinson splitter and delaying one branche /4. The circuit is shown in (a), the splitter circuit in (b). The several individual layouts in (c) and the complete layout in (d). 3-2 Philips Semiconductors 3. Multiplexer Application Note The multiplexer has a high frequency input clock. The data is triggered by the low frequency clock. This clock has TTL level. To be able to drive 50 ohm, two buffers are used. First, the TTL signal is buffered by IC671 IC671 (74ABT244 74ABT244). After this, it is boosted by 1/2 IC 681 (3205). Three outputs have been connected via resistors R671, R672 and R673, in order to sink enough current to reach TTL level. The networks R674-C674 R674-C674 and R676C676 R676C676 have been added to compensate for overshoot 3.3 Layout The following considerations have been taken into account in the generation of the layout: · The multiplexer IC has an extra ground plane on layer 1 and 8. This plane is not a must, but it helps reducing interference. · The TTL lines (from JUMC1.4, bus D_78TBUS 78TBUS) are thin lines (0.3 mm). The lines are kept short, to reduce the load capacitance. · The clock combiner circuit is shown in the figure on the previous page. · The lines to the clock inputs of both multiplexer and clock converter are symmetrical 50 ohm microstrips. · The transmission lines for the clock have been placed on layer 1. · The transmission lines for the electrical loop signals have been placed on layer 5. · The spacing between the electrical loop - SMA connectors depicts the distance between multiplexer and demultiplexer. The SMA connectors have been distributed equally between multiplexer and demultiplexer. The lines to the SMA connectors are symmetrical triplate lines. · IC671 IC671 is placed close to the multiplexer. This is done to keep the unbuffered clock line short. The booster IC681 IC681 is placed near JUMB. · Lengths of transmission lines to laserdriver and demultiplexer are shown in appendix 5, "Critical line lengths". 3.4 Operational information The input stage of the multiplexer consists of the circuit shown below. V3.3 23k 15k3 IN 1.3V 13k to next stage 5k 1.3V VEE Fig.2 Input stage of multiplexer. 3-3 5k Philips Semiconductors 3. Multiplexer Application Note 3-4 Philips Semiconductors 4. Laserdriver 4. 4.1 Application Note Laserdriver Block diagram STM16 STM16 Outputs LAB SIMOD clock clock Laserdriver LAB data OQ2545 OQ2545 LA data 4.2 4x ALS LASER_EAM OPT_LDR 4x OL (Optical Loop) EL (Electrical Loop) SIBIAS PI Op1 peltier 1550 nm Temp Stabilized DFB Laser Temperature Control Circuit setup The laserdriver circuit consists of the following subcircuits: -Laserdriver -Temperature stabilized laser, with control circuit -Control circuitry for the bias- and modulation current of the laserdriver The circuit of the laserdriver is drawn on schematics page "OTM/2.drw". The temperature control of the laser is drawn on page "OTM/3.drw".The schematics can be found in appendix 1, "Schematics". The laserdriver has two inputs: the `normal' signal from the multiplexer (TRANS_BUS) and the optical loop signals (OL_BUS). The selection is done by signal OPT_LDR~ (active low). OPT_LDR is controlled by switch S6018 S6018,1 "OPT". When enabled, OT601 OT601 "OPT LDR" will light up. To the adjustment pins AMPADJ (16) and EFADJ (15) a current can be applied. This has been prepared with pads for resistors R802, R803, R807 and R808. On the boards, only R802 is mounted. In the demoboard no modulation control loop has been implemented. The user can set a DC current with adjusting R857 "Laser mod setting". R857 is mounted on the bottom of the board. The bias current is controlled by a loop consisting of the monitor photo diode, IC820 IC820 and T831. The output power is monitored and converted to voltage with 1/2 2904 (IC820 IC820, pins 1,2,3). This voltage is fed to the integrator around the other half of IC820 IC820 (pins 5,6,7). The bias setting can be adjusted by R820 "Laser bias setting". The Automatic Laser Shutdown (ALS) signal from switch S601-4 S601-4,5 "ALS" controls LED OT604 OT604 "ALS" . It is fed to the laserdriver and the integrator. This guarentees a soft start of the laser after automatic laser shutdown. 4-1 Philips Semiconductors 4. Laserdriver Application Note The polarity of the output signal can be changed by switching the laserdriver in "Laser" or "Electro Absorbing Modulator" (EAM) mode. This can be done by switch S631-3 S631-3,6 "EAM/LASER". LED OT641 OT641 "EAM" or LED OT642 OT642 "LASER" will indicate the mode. The control signal EAM_LASER is connected to pin 17. The temperature control for the laser consist of a resistor bridge around the lasers' NTC resistor (R954, R955 and R956), a differential integrator (1/2 2904, IC951 IC951) and a booster (T958 and T958). The unused output (LA) is terminated with 50 ohms and made available at connector ST651 ST651 "LA". For proper functioning of the laserdriver this connector should be terminated with 50 ohms. This guarentees an equal load of 25 ohm on LA and LA output of the laserdriver. When problems occur, the path can be disconnected by removing R810. Termination R811 should then changed to 25 ohm. The laser buffer outputs are available at connectors ST652 ST652 "LAB" and ST653 ST653 "LAB". 4.3 Layout The following considerations have been taken in the generation of the layout: · The laserdriver is mounted on layer 8. This is to minimize line lengths to the laser and to have space for the cooling fins. · The corner pins have been enlarged to copper planes to work as heat spread. The corner pins are in the package connected with the die. · A -6.5V copper plane has been made on layer 1 and 4 to enhance heat transport from the IC to the heat spreader of the laser. · An extra ground plane has been placed at layer 2 to enhance heat transport from the IC to the heat spreader of the laser. · On layer 1 and 2 planes have been added. No thermal releases were made in the vias in the area between laserdriver and laser. · No signals were placed on top of the input pins of the laserdriver. · The components around the laserdriver were placed as close as possible to the laser. · The driving line, to the laserdiode is a 25 ohm line. (The laser diode has an input impedance of 25 ohm). The lines from the multiplexer to the laserdriver have equal length and are 50 ohm coupled transmission lines. · The lines to the buffer outputs are differential 50 ohm lines on layer 8. · The termination of the output LA is done as close to the laserdriver as possible. · Lengths of data and clock lines from multiplexer and data and clock recovery are shown in appendix 5, "Critical line lengths". 4.4 Alignment procedure The alignment procedure adjusts the control circuitry to the used laser. The bias is set first, with modulation current = 0. (R857 not yet mounted) · The used optical connectors are cleaned and checked. 4.4.1 Bias setting · The output power at the laser connector is applied to an optical power meter. · A resistor decade is connected to pad R820 "Laser bias setting". · The resistor value is adjusted until the optical power is 1 mW. · R820 is chosen within 1% of the found resistor value (nearest E96 resistor value). 4-2 Philips Semiconductors 4. Laserdriver 4.4.2 Application Note Modulation setting According to ITU recomendation G.957 (03/93) section 3.2.4, "Measurement methods for the extinction ratio" are under study. The board has been aligned with the following procedure: · The laser is modulated with a 27-1 Pseudo Random Bit Sequence (PRBS). · A resistor decade is connected to pad R857 "Laser mod setting" (bottom of board). · The output signal is fed via a O/E transducer and STM16 STM16 filter to an oscilloscope. · A histogram of the Y value is made. · The highest peak around optical 0 and 1 are taken as mean values. (If not one real maximum can be found, the average between the two highest peaks is taken). · The resistor value is adjusted until the extinction ratio (Low/High) is 10%. · R852 is chosen within 1% of the found resistor value (nearest E96 resistor value). 4-3 Philips Semiconductors 4. Laserdriver Application Note 4-4 Philips Semiconductors 5. Receiver 5. Application Note Receiver 5.1 Block diagram RCV-DCR I/O STM 16 Inputs Transimp + Main Amp CIC100 CIC100 OQ2538 OQ2538 Op2 Offset Photo diode bias + guard Input_Level LEVEL 5.2 EL in + Photo diode bias voltage - Circuit setup The receiver circuit consists of the following subcircuits: -Photo diode bias monitor and guard -Electrical input. This can only be used when the photo diode is not mounted. A resistor of 4.7 kohm needs to be mounted between input pin and M242 (see appendix 6) -Photo diode. This can be a PIN diode or an APD -Transimpedance amplifier -Main amplifier -Offset control loop/offset adjustment The circuit of the transimpedance- and main amplifier is drawn on schematics page "ORM/1.drw", the LOS and Level detect circuits on page "ORM/2.drw" and the guard circuit is drawn on page "PDCM/1.drw". The schematics can be found in appendix 1, "Schematics". 5.2.1 Photo diode bias monitor and guard In order to guard a mounted avalanche photo diode from voltage breakdown, a simple guard circuit has been implemented on the board. The principle is based on the following assumptions: · Voltage breakdown occurs only when the photo diode bias voltage is high. This means a high avalanche multiplication factor. Still, the total photo current will be low. So a high photo diode bias voltage will cause a low current limit. 5-1 Philips Semiconductors 5. Receiver Application Note · When the photo diode bias voltage is low, it means that the avalanche multiplication factor is also low. Thus for a low bias voltage a high current limit will be taken. The guard circuit measures the photo diode voltage and current. The current limit is dependent on the measured voltages. If the current limit is reached, the photo diode bias voltage is shorted by a MOSFET. The current limits and transition voltages can be adjusted. A Matlab program is given to calculate the set values. The photo diode bias circuit is secured to misconnection by diode GR301 GR301. The current monitor is build up around 1/2 IC304 IC304 (pins 1,2,3). The photo current causes a positive voltage at the output of the transimpedance amplifier. This voltage is compared with the reference voltage at the output of analog switch IC305 IC305. The selection of the reference voltage is done by comparing the photo diode bias voltage with a set value. This is achieved via voltage divider R306, R305 (photo diode voltage) and R391, R392 (set voltage). The set voltage can be changed for different diodes by adding resistors on pads R379 and R378. The ratiod photo diode voltage is buffered by 1/2 IC301 IC301 (pins 1,2 and 3) and compared by the rest of IC301 IC301 (pins 5,6 and 7) in a Schmitt trigger. The output voltage is clamped between -0.2 and 5 volt with R394 and GR321 GR321. The current limit is determined from voltage MC_VREF (4.04V) by voltage dividers R377,R376 and R375,R374. The bias voltage line is filtered with RC combinations R203,C261,C262, R263,C201 and R202,C202. If a PIN diode is used, the bias guard can be left open. Closing jumper ST264 ST264 will bias the photo diode. GR264 GR264 has been added for safety measures, if the jumper has been left closed. The photocurrent can be measured at ST264 ST264. For accurate measurements prevent current flow in guard circuit by removing R203. 5.2.2 Calculations for photo diode bias guard Voltage ratio photo diode bias voltage: R306 V PDMeas = - V PD R306 + R305 (1) R391//R379 R391//R379 V PDMeas = - V MC_VREF R392//R378 R392//R378 + R391//R379 R391//R379 (2) Transition voltage input from high to low: R380 R388 + R380 R391//R379 R391//R379 V PDMeas = - - V MC_VREF ­ - V P5V R388 R388 R392//R378 R392//R378 + R391//R379 R391//R379 (3) Transition voltage input from low to high R388 + R380 R391//R379 R391//R379 R380 V PDMeas = - - V MC_VREF ­ - V PN4V5 - R388 R388 R392//R378 R392//R378 + R391//R379 R391//R379 (4) Equations 3 and 4 can be expressed in terms of VPD, giving: R380 R305+R306 R388 + R380 R391//R379 R391//R379 V PD,HtoL = - - V MC_VREF ­ - V P5V - R388 R306 R388 R392//R378 R392//R378 + R391//R379 R391//R379 (5) Transition voltage input from low to high R380 R305+R306 R388 + R380 R391//R379 R391//R379 V PD,LtoH = - - V MC_VREF + - V PN4V5 - R388 R306 R388 R392//R378 R392//R378 + R391//R379 R391//R379 5-2 (6) Philips Semiconductors 5. Receiver Application Note Gain of transimpedance amplifier: (7) A TransImp = R351 High photo diode voltage, bias current limit voltage: R377 V Lim,VPDHigh = - V MC_VREF R377 + R376 (8) Low photo diode voltage, bias current limit voltage: R375 V Lim,VPDLow = - V MC_VREF R375 + R374 (9) The current limit is equal to the voltage limit divided by the transimpedance gain: High photo diode voltage, bias current limit: R375 1 I Lim,VPDHigh = - - V R375 + R374 R351 MC_VREF (10) Low photo diode voltage, bias current limit: R377 1 I Lim,VPDLow = - - V MC_VREF R377 + R376 R351 (11) The values can be calculated with the given Matlab program. The program is shown on the next pages, followed by the calculated values. 5-3 Philips Semiconductors 5. Receiver Application Note 5.2.3 Matlab program % Matlab program for calculation of transition voltages % and current limit, determined by resistor settings % % Used variables % % Set values R305 = 1e6; % Photo diode voltage divider R306 = 34.8e3; R378 = 110e3;% Lower part Schmitt trigger voltage divider R392 = 38.3e3; R379 = 1e99;% Higher part Schmitt trigger voltage divider R391 = 10e3; R380= 10e3;% Smitt trigger input resistor R388 = 1e6;% Smitt trigger feedback resistor R376 = 4.64e3;% Photo diode bias current high limit R377 = 8.25e3; R375 = 1e3;% Photo diode bias current low limit R374 = 10e3; R351 = 3.32e3;% Transimpedance gain % R392a=1/(1/R392 1/R392 + 1/R378 1/R378); R391a=1/(1/R391 1/R391 + 1/R379 1/R379); % Voltages N4V5 = -4.5; P5V = 5; V_MC_VREF=4.05; % RatioPD = R306/ R306/(R306+R305); Hysteresis=R380/R388 R380/R388; Vmin_Smitt=(R391a/(R392a+R391a)*V_MC_VREF; ; ; RatioHighCurrentLim=R377/ R377/(R377+R376); RatioLowCurrentLim=R375/ R375/(R375+R374); ; 5-4 Philips Semiconductors 5. Receiver Application Note I_Lim_VPDLow =RatioHighCurrentLim*(1/R351 1/R351)*V_MC_VREF; % printout of values '); fprintf(Outfile,'Photo diode bias guard settings\n'); fprintf(Outfile,'Set values of resistors are\n'); fprintf(Outfile,'\t R305 = %g \t[ohm] \t Photo diode voltage divider\n',R305); fprintf(Outfile,'\t R306 = %g \t[ohm] \t Photo diode voltage divider\n',R306); fprintf(Outfile,'\t R378 = %g \t[ohm] \t Lower part Schmitt trigger voltage divider\n',R378); fprintf(Outfile,'\t R392 = %g \t[ohm] \t Lower part Schmitt trigger voltage divider\n',R392); fprintf(Outfile,'\t R379 = %g \t[ohm] \t Higher part Schmitt trigger voltage divider\n',R379); fprintf(Outfile,'\t R391 = %g \t[ohm] \t Higher part Schmitt trigger voltage divider\n',R391); fprintf(Outfile,'\t R380 = %g \t[ohm] \t Smitt trigger input resistor\n',R380); fprintf(Outfile,'\t R388 = %g \t[ohm] \t Smitt trigger feedback resistor\n',R388); fprintf(Outfile,'\t R376 = %g \t[ohm] \t Photo diode bias current high limit\n',R376); fprintf(Outfile,'\t R377 = %g \t[ohm] \t Photo diode bias current high limit\n',R377); fprintf(Outfile,'\t R375 = %g \t[ohm] \t Photo diode bias current low limit \n',R375); fprintf(Outfile,'\t R374 = %g \t[ohm] \t Photo diode bias current low limit \n',R374); fprintf(Outfile,'\t R351 = %g \t[ohm] \t -Transimpedance gain\n',R351); fprintf(Outfile,'\n'); fprintf(Outfile,'Results\n'); fprintf(Outfile,'\n'); fprintf(Outfile,'\t\t %g \t\t Division ratio photo diode bias voltage \n',1/RatioPD); fprintf(Outfile,'\t %g\t [V]\t Transition voltage current limit selection, High to low \n',V_PD_HtoL); fprintf(Outfile,'\t %g\t [V]\t Transition voltage current limit selection, Low to High \n',V_PD_LtoH); fprintf(Outfile,'\t %g\t [mA]\t Current limit at high voltage \n',I_Lim_VPDHigh*1000); fprintf(Outfile,'\t %g\t [mA]\t Current limit at low voltage \n',I_Lim_VPDLow*1000); fprintf(Outfile,' \n'); fprintf(Outfile,'\t %g\t [V]\t Voltage at high current limit \n',RatioHighCurrentLim*V_MC_VREF); fprintf(Outfile,'\t %g\t [V]\t Voltage at low current limit \n',RatioLowCurrentLim*V_MC_VREF); fprintf(Outfile,'\t %g\t [V]\t Voltage at (-) input Smitt trigger \n',Vmin_Smitt); fprintf(Outfile,' \n'); fprintf(Outfile,' \n'); fclose(Outfile); 5-5 Philips Semiconductors 5. Receiver Application Note 5.2.4 Matlab program output Photo diode bias guard settings Set values of resistors are R305 = 1e+06 [ohm] Photo diode voltage divider R306 = 34800 [ohm] Photo diode voltage divider R378 = 110000 [ohm] Lower part Schmitt trigger voltage divider R392 = 38300 [ohm] Lower part Schmitt trigger voltage divider R379 = 1e+99 [ohm] Higher part Schmitt trigger voltage divider R391 = 10000 [ohm] Higher part Schmitt trigger voltage divider R380 = 10000 [ohm] Smitt trigger input resistor R388 = 1e+06 [ohm] Smitt trigger feedback resistor R376 = 4640 [ohm] Photo diode bias current high limit R377 = 8250 [ohm] Photo diode bias current high limit R375 = 1000 [ohm] Photo diode bias current low limit R374 = 10000 [ohm] Photo diode bias current low limit R351 = 3320 [ohm] -Transimpedance gain 29.7356 Division ratio photo diode bias voltage 30.1815 [V] Transition voltage current limit selection, High to low 33.0064 [V] Transition voltage current limit selection, Low to High 0.110898 [mA] Current limit at high voltage 0.780761 [mA] Current limit at low voltage 2.59213 [V] Voltage at high current limit 0.368182 [V] Voltage at low current limit 1.05445 [V] Voltage at (-) input Smitt trigger Results 5.2.5 Example setting APD guard The APD mounted on board 01 has the following specifications: Device: Product: Device#: Wafer-ID: Vbr: V(12) V(4) ATT InGaAs Avalanche Photodetector 127E 18867 qe2899b1-93 69.6 V Breakdown voltage 64.2 V Voltage at M=12 53.6 V Voltage at M=4 5-6 Philips Semiconductors 5. Receiver V(2.7) Mmax Idp id(12) Id(0.9V) F(12) F(17) A BW(2.7) BW(12) TEMP(C) M(0.9Vbr) R Application Note 47.9 V 38 1.8 nA 31 nA 26 nA 4.9 6.4 65 V 2401 Mx 2059 Mx 27.9 9.34 0.85 Voltage at M=2.7 Maximum gain Primary dark current Dark current at M=12 Total dark current at 0.9 Vbr Excess noise factor at M=12 Excess noise factor at M=17 Gain coefficient Bandwidth at M=2.7 in MHz Bandwidth at M=12 in MHz Measurement temperature Calculated value of A, from value at 0.1 Vbr Responsivity at 1550 nm The temperature coefficient of the photodiode has the following temperature dependency: TCu[mV/K] TCu0 TCu1 TCu2 TCu3 -10 0 10 20 TCu4 30 40 TCu5 TCu6 50 TCu7 60 70 T[°C] Fig.3 The temperature coefficient TCu versus temperature. The curve can be approximated by a constant for 10 ° C intervals. To calculate the breakdown voltage at a set temperature, the following equation must be taken into account: V br ( T ) = V br ( T 0 ) + B n + ( T ­ T 0 )TC u n (12) The offset Bn and temperature coefficient TCun can be taken constant in 10 °C intervals. For the temperature range -10 °C . 70 °C, the values for the used photodiode are given in the table below. 5-7 Philips Semiconductors 5. Receiver Application Note TABLE 6 Temperature behaviour of APD type ATT127E ATT127E, Temperature -10.0 0.10 10.20 20.30 30.40 40.50 n 0 1 2 3 4 5 Bn 0.163 0.085 0.029 0 0 0.048 TCun 195.4 192.3 188.6 182.8 177.9 172.6 50.60 6 0.145 168.7 60.70 7 0.318 163.8 °C V mV/K Filled in, with the data of the mounted diode, gives for the photodiode at board 01 the following breakdown voltages: · 0.1954 = 62.01 V Vbr(+70°C)=69.6+0.318+(+70-27.9) · 0.1638 = 76.52 V Vbr(-10°C)=69.6+0.163+(-10-27.9) The settings for the guard circuit must be set at Vmax < 62.01 V. To find the value at which the photo diode should be biased, the photobias is varied, with optical input power constant. The optical power is chosed such that the bit errors are in the range 1E-10 1E-10 . 1E-4. The result is shown below. 10-3 BER vs photodiode bias voltage at Pin=-30 dBm 10-4 BER 10-5 10-6 10-7 10-8 10-9 10-10 55 60 Bias voltage [V] 65 70 Fig.4 .BER vs Bias voltage at Pin (optical) = -30 dBm. This measurment must be performed to distinguish the optimal bias voltage. 5-8 Philips Semiconductors 5. Receiver 5.2.6 Application Note Electrical input. This can only be used when the photo diode is not mounted. This input has been added to test the board without photo diode mounted. If it must be used mount a resistor from M242 to the photodiode pad. The resistor should be approximately 4.7 kohm. 5.2.7 Offset control loop The transimpedance amplifier needs no offset compensation. The only offset which should be compensated is the main amplifier, of the main amplifier-data and clock recovery combination. The main amplifier itself has a build in offset control loop. Adjustments can be made a the decoupling capacitor COFF (pins 44 and 45). Either the offset sense output of the data and clock recovery IC can be connected, or a set value. Both possibilities are availbable on the board. (Close ST213 ST213 for set value, close ST212 ST212 for DCR offset loop, or leave all jumpers open for internal compensation only). The set offset possibility can be used to gain 1 dB in sensitivity with very noisy optical signals. Resistors R228 and R235 should have values in the 10 kohm range. 5.2.8 LOS detection Los of signal is detected by amplifing and comparing the LOS/LOSDC outputs of the main amplifier. Amplification is done by 1/2 2272 (IC203 IC203, pins 1,2 and3), comparing by the other half (pins 5,6 and 7). ITU recommends LOS when the BER > 1E-3. However, with Avalanche Photo Diode, the dark-current, multiplicated with the APD factor gives approximately the same output level at the rectifiers as asignal will give, at the strength corresponding with a BER of 1E-3. Therefore, the rectifier circuit has been designed so that at an input signal corresponding to BER > 1E-5, LOS will be given. (M207). To distinguish between small signal or amplified noise, the DCR's LOS (LOS_DCR) has also been taken into account: the main amplifiers' LOS (M207) is ANDed with the DCRs' LOS. (LOS_DCR). The ANDed signal LOS_D controls LED OT621 OT621, "LOS" and JUMB, pin 5. 5.2.9 Level detection The input level detection circuit amplifies the AGC/AGCDC signals from the main amplifier in a 2272 (IC204 IC204). The output signal is clamped to prevent output underflow. The LEVEL signal is fed to JUMB, pin 1. 5.2.10 Photodiode bias The photodiode bias circuit has been build up with standard lumped components, except for the capacitor direct at the photodiode. This capacitance is a copper plane on layer 5, guarded with ground planes on layer 4 and 6. The plane measures 10.795x8.255 mm, yielding 33.7 pF. Alternative circuits should give values between 20 and 40 pF. 5.2.11 Transimpedance amplifier The transimpedance amplifier is a CIC100B CIC100B type. (equivalence of CGY2100 CGY2100). For proper functioning the following precautions should be taken: · VDD1 (pins 46 and 47) and VDD2 (pins 38, 39, 40 and 41) should have seperate power supply filtering. This to prevent parasitic feedback. · VDD1 (pins 46 and 47) needs a RC combination, to reduce resonances. This is achieved by R208-C207 R208-C207. · The unused pins (BW-ADJ, pin 21; G-ADJ, pin 19; REF, pin 43 and 44) are terminated with 51E1 resistors, 51E1 resistor + 10 nF capacitors respectively. This gives the least disturbance of the transfer function. · All power supply filtering has been done by double LC combinations. 5-9 Philips Semiconductors 5. Receiver Application Note 5.2.12 Noise lowpass filter To limit the bandwidth before the main amplifier, a lowpass filter has been implemented. This filter is optimized in conjunction with the main amplifier. The circuit and layout are shown below. /4 @2.5 GHz open stub 32 33 10E CIC100B CIC100B 28 29 2n 100n 3p3 10E 2n 215E 100n 6 OQ2538S1 OQ2538S1 8 GND /4 @2.5 GHz open stub (a) OQ2538S1 OQ2538S1 CIC100B CIC100B GND (c) (b) Fig.5 Lowpass filter for noise reduction. The filter is placed between transimpedance amplifier and main amplifier. The circuit is shown in (a). The enlarged layout in (b). The complete layout within the EMC shielding is shown in (c) 5.3 Layout The transimpedance- and main amplifier are placed in a metal shielding. · The lines from the photo diode have been made as short as possible. · The capacitance at the input has been reduced to the minimum: A CUTOUT HAS BEEN MADE IN THE GROUND PLANE AT LAYER 3. · An extra ground plane was placed at layer 1. · To minimize the plane-capacitance area, two ground layers are made as sandwich around the capactior. These planes are on layers 4 and 6 · No thermal releases were made in the vias at the ground planes on layers 1, 3, 4, 6, 7 and 8. · To enhance EMC immunity a complete ground plane was made on layer 8. · The path from transimpedance amplifier via main amplifier to data and clock recovery has been made as symmetrical as possible. · The transmission line to the data and clock recovery is a balanced 50 ohm line on layer 1. 5-10 Philips Semiconductors 6. Data and clock recovery data clock OPT_DCR 4x RCV-DCR I/O Block diagram CREF19 CREF19 6.1 Data and clock recovery OL (Optical Loop) 6. Application Note Data & Clock Recovery OQ2541C3 OQ2541C3 DCR_LOCK Offset LOS EXT REF Ext 19 or 39 MHz C39_EN 6.2 39 MHz OSC Circuit setup The data and clock recovery circuit is drawn on schematics page "DCR/1.drw". The schematics can be found in appendix 1, "Schematics". The data and clock recovery circuit consists of the following circuits: -DCR IC OQ2541 OQ2541 -39 MHz crystal oscillator The OQ2541 OQ2541 has been set up in DCR mode. The on-chip power supply needs a booster stage, which is build up with transistors T551, T552, R560, R559, R561, R563, and C561. In general, any transistor with DC current amplification over 100 can be used. Two transistors are used because the available type did not meet the current sink requirements. Alternative circuits should have a power supply rejection ratio of more than 60 dB for all frequencies. The data and clock recovery has two outputs: the `normal' signal to the demultiplexer (REC_BUS) and the optical loop signals (OL_BUS). The selection is done by signal OPT_DCR~ (active low). OPT_DCR~ is controlled by switch ST611-6 ST611-6.3 "OPT-DCR". When enabled, OT611 OT611 "OPT DCR" will light up. RF power supply filtering is achieved by C554-R571 C554-R571. The load impedance as seen by the power supply is 15 ohm, in series with two forward biased diodes. To maintain stability, series resistor R571 should be 2.15 ohm. Alternatively, R571 and C554 can be left away when C554 is changed to 47 nF. 6-1 Philips Semiconductors 6. Data and clock recovery Application Note The frequency locked loop reference frequency is applied on pins 21 and 22. The reference signal is fed by a 50 ohm differential transmission line from the boards' reference oscillator/external input. The source side of the reference is 50 ohm, made by attenuators R526, R558, R521 and R527. The setup guarentees a 50 ohm noise immune transport of the reference signals The LOS and LOCK outputs are open collector outputs. They have been pulled to +5V with 10k resistors. (R546 and R550). Both outputs are fed to a LED driver and to JUMB. The signal names are LOS_DCR and LOCK. The LOS is the output of an error detection circuit. This circuits uses the outputs of the Alexander phase detector. If both the previous sample (A) and the next sample (B) have the same state, no transition should have occurred between sample A and B. Thus, the sampling moment (T) should also have that state. If this is not the case, an error has occurred. If the error rate is higher then 10-3, LOS will become high. The LOCK is high when the onchip VCO is at 2488320 kHz. 6.3 Layout For the layout, the following considerations were taken into account: · An extra ground plane was placed at layer 1 and 8 · No signals were placed under the input lines of the IC · A row of vias was placed under the IC, to guarentee good RF ground · No thermal releases were made in the via connection in all layers · RF decoupling capacitors were placed as close as possible to the IC · Both input and output were build up as symmetric as possible · Lengths of data and clock lines to laserdriver and data and clock recovery are shown in appendix 5, "Critical line lengths". 6.4 6.4.1 Operational information Reference oscillator signal The reference signal for the OQ2541 OQ2541 can be taken from either the board oscillator or an external applied signal. The board oscillator can be turned on with the switch S661, "39 MHz XTAL on". OT660 OT660 "39 MHz XTAL on" will light up in this case. The OQ2541 OQ2541 is able to work with a 19 MHz reference signal. The mode is set by switch S661 "DRC at 19 MHz". When set, LED OT669 OT669 "DCR at 19 MHz" will lit up. The signal must be externally applied. The board oscillator must be turned off in this case. The reference signal possibilities are shown in table 9. TABLE 7 OQ2541 OQ2541 reference signal setup possibilities Mode S661/OT660 S661/OT660 S661/OT669 S661/OT669 "39 MHz XTAL on" "DRC at 19 MHz" 39 MHz board osc. On Off 39 MHz ext. osc Off Off 19 MHz Off On SMA "EXT REF DCR" Open 39 MHz signal 19 MHz signal FLL CAP value 100 nF 100 nF 200 nF Notes: 1) FLL CAP: Frequency locked loop capacitor. On the PCB pad space is reserved for an extra 100 nF capacitor. 2) If the external applied signal is not large enough to drive the OQ2541 OQ2541, R458 can be adjusted. 6-2 Philips Semiconductors 6. Data and clock recovery 6.4.2 Application Note Phase Detector Output For applications in which an external VCO is used, the output of the Alexander Phase detector is available. To prevent DC current, this output is biased with GR452 GR452 and R483. Outputs are availlable at measure point M459. 6.4.3 Loss Of Signal The loss of signal output (pin 39) can be measured at R471. 6.4.4 Output Amplitude Reference The output amplitude reference pin has been left open. This because the board is dimensioned to work with CML logic inputs at the demultiplexer and laserdriver. For operation with other levels, the loop connectors can be used. The output level can be adjusted, by adding an appropriate resistor value to ground or VEE, which should only be applied for test purposes. 6.4.5 Global frequency acquisition (FLL) The VCRO is designed to oscillate at a frequency of 2.5 GHz. The recovery of the different data rates is done by applying an appropriate setting to Frequency Divider 1. In order to keep the VCRO in a frequency window of 1 000 ppm around the set clock frequency, a frequency locked loop is included in the IC. The reference frequency needs to be as stable as 1 000 ppm. If the OQ2541 OQ2541 is out of lock and in recovery mode, the phase locked loop is disabled. Only the FLL is closed. The frequency detector consists of two counters and additional logic. After each count the output of the frequency window detector produces an output signal (either high or low), if the oscillator frequency is outside the set window. This is applied to the loop filter. The loopfilter controls the VCRO. If the reference frequency is 19 MHz, the count time of the FWD is double as long as with a 39 MHz reference clock. for stability reasons, the integrator capacitance must be kept inversely proportional with the reference frequency. 6.4.6 LOCK signal The lock signal (DCR pin 12, also measurable at M452) controls LED OT611 OT611 "DCR-lock". The lock is such implemented that it is frequency driven and not phase driven. LOCK indicates that the on-chip VCO is at 2488320 kHz. It gives no indication whether an input signal is applied or not. 6.4.7 Data recovery In the data recovery mode, the PLL is active. The PLL is build around the Alexander Phase detector, the loop filter, VCRO and frequency divider 1. The Alexander Phase detector is used to guarantee the best possible sampling moment. The detector has a non linear transfer characteristic. KD is depending on the amount of jitter of the inputsignal. The loop is therefore nonlinear. No simple equations can be given for the dynamic behaviour. The loop has been designed such that: · The pull-in range is larger than the FLL frequency window: therefore if the input signal has a spectral component which is within the FLL frequency window, direct pull in occurs. · The ITU jitter tolorance recommendation (G.958) is met. The proportional path input (PGAIN, pin 13) can be left open. 6-3 Philips Semiconductors 6. Data and clock recovery Application Note 6-4 Philips Semiconductors 7. Demultiplexer 78 MHz JUMB JUMA 7.2 32 1 : 32 Dmux 78 Mbps OQ2536 OQ2536 4x 4x OL (Optical Loop) CLK out 78 MHz DMUX EL (Electrical Loop) Block diagram DMUX_LS (BTL/TTL out) 7.1 Demultiplexer EL_DMUX 7. Application Note data data clock clock Circuit setup The demultiplexer circuit consists of the following subcircuits: -OQ2536A -OQ2536A demultiplexer -1.5/2.0 volt Pulse Width Modulator (PWM) voltage reference -78 MHz clock buffer -Power supply filtering The circuit of the demultiplexer is drawn on schematics page "DCR/2.drw", the buffer is drawn on page "CONNECTORS/2.drw". The schematics can be found in appendix 1, "Schematics". The selection of the input signal (either from REC_BUS or EL_BUS) is done by signal EL_DMUX~ (active low). EL_DMUX~ is controlled by switch ST611-4 ST611-4,5 "En EL-DMUX". When enabled, OT611 OT611 "EL-DMUX" will light up. The unused boundary scan inputs of the demultiplexer are left open. The output high voltage can be set by applying a voltage to pins 13, 14, 36, 37, 63, 85 and 86. This voltage is made from the +5 board voltage by a PWM IC MAXIM750 MAXIM750 (IC451 IC451). To change the output voltage, this voltage can be altered by switching T459. Switching occurs when DMUX_LS is high. DMUX_LS is controlled by switch S631-4 S631-4,5 "BTL/to MUX". LED OT651 OT651 "DMUX to MUX" will light up when enabled. Otherwise LED OT652 OT652 "BTL" will light up. Mind that the same control switch is used to modify the demultiplexer output voltages. Selection which ICs will be controlled is implemented by mounting a FET on the appropriate place. Either T719 (multiplexer) or T459 (demultiplexer). In "BTL" mode the voltage is 1.5 V, in "DMUX to MUX" state the voltage is 2.0 V. By changing the value of R458 other values can be achieved, when necessary. Keep in mind that the maximum current through the output transistors should not exceed 14 mA. Each data line has a 21.5 ohm series resistor to reduce ringing. 7-1 Philips Semiconductors 7. Demultiplexer Application Note The clock buffer is build up around IC661 IC661 (74ABT244 74ABT244) and IC681 IC681 (3205). The multiplexer clock output signal is amplified with an BFR92A BFR92A. 7.3 Layout The following considerations have been taken in the generation of the layout: · The demultiplexer IC has an extra ground plane on layer 1 and 8. This plane is not a must, but it helps reducing interference. · The TTL lines (from JUMA, signals D78R0 D78R0 . D78R7 D78R7) are thin lines. The lines are kept short, to reduce the load capacitance. · IC661 IC661 is placed close to the multiplexer. This is done to keep the unbuffered clock line short. The booster IC681 IC681 is placed near JUMB. · The spacing between the electrical loop - SMA connectors depicts the distance between multiplexer and demultiplexer. The SMA connectors have been distributed equally between multiplexer and demultiplexer. The lines to the SMA connectors are in symmetrical triplate lines. · No holes are made in the thermal releases of the ground planes · Lengths of data and clock lines from multiplexer and data and clock recovery are shown in appendix 5, "Critical line lengths". 7.4 Operational information The output stage of the demultiplexer consists of the circuit shown below. VTT 100E for data 50E for clock out from previous stage Fig.6 Output stage of demultiplexer. Maximum current through output transistor is 14 mA. 7-2 Philips Semiconductors 8. Evaluations 8. Application Note Evaluations 8.1 Possible modes The following performance tests can be executed: 1) Normal mode 2) Optical loop. 3) Electrical loop These setups are shown in the following figures: First the posibilities are shown, followed by the individual modes. Combinations of the shown setups are also possible, but not shown in the figures Attenuated inverted laser signal output LASER APD bias Laser driver 622 MHz clock buffered outputs Transmit data 32 bit, TTL LEVEL (pin 01) LOS_DCR (pin 04) LOS_D (pin 05) LOCK (pin 10) C78RB C78RB (pin 12) C78TB C78TB (pin 18) Supply: -8V GND +8V 50 C78T Electrical input 2.5 GHz clock Photodiode Electrical Loop C78R Receiver out/ DCR in conn's Received data 32 bit 0.3 - 1.5 V Optical loop 19 MHz DCR reference Fig.7 Board with main connectors designated, and high bitrate lines highlighted. Receive and transmit part can work independently. Signal flow is dependent on mode setting: each IC, when applicable, can be set in normal or loop mode. This enables various test possibilities. Various possibilities are shown in the following figures 8-1 Philips Semiconductors 8. Evaluations Application Note 8.1.1 Normal mode, measurements at optical side Attenuated inverted laser signal output LASER APD bias Laser driver 622 MHz clock buffered outputs Transmit data 32 bit, TTL Level shift LEVEL (pin 01) LOS_DCR (pin 04) LOS_D (pin 05) LOCK (pin 10) C78RB C78RB (pin 12) C78TB C78TB (pin 18) 50 C78T open Electrical input 50 Photodiode Electrical Loop C78R Receiver out/ DCR in conn's Supply: -8V GND +8V 622 MHz 0 dBm Received data 32 bit 0.3 - 1.5 V Optical Receiver Optical Transmitter Optical loop 19 MHz DCR reference Fig.8 Signal flow with board in normal mode, measurements at optical side. The input signal is generated in an optical transmitter. The signal is received, amplified, data and clock are seperated and demultiplexed. The demultiplexed data can be fed to the mux, but needs a level shift for proper working. The multiplexer needs a 2.5 GHz clock to drive. In this case the clock is converted from a 622 MHz clock. Signals as are received by the laserdriver can be monitored at LAB and LAB. The not used side of the laser driving stage is attenuated and fed to LA. This corresponds with the laser current. 8-2 Philips Semiconductors 8. Evaluations 8.1.2 Application Note Normal mode, measurements and generation at 78 Mbps side Attenuated inverted laser signal output LASER 50 APD bias Laser driver 622 MHz clock buffered outputs 78 Mbps Pattern Generator LEVEL (pin 01) LOS_DCR (pin 04) LOS_D (pin 05) LOCK (pin 10) C78RB C78RB (pin 12) C78TB C78TB (pin 18) Transmit data 32 bit, TTL 50 C78T open 622 MHz 0 dBm Electrical input 50 Photodiode Electrical Loop C78R Optical Path Receiver out/ DCR in conn's 78 Mbps Logic Analyzer Supply: -8V GND +8V Received data 32 bit 0.3 - 1.5 V Optical loop Optical Attenuator 19 MHz DCR reference Fig.9 Signal flow with board in normal mode, measurements at 78 Mbps side. The input signal is generated with a 78 Mbps pattern generator. The pattern generator is triggered by the divided 2.5 GHz multiplexer clock, which is converted from the applied 622 MHz clock. The signal is transmitted, fed to an optical path and attenuator and received. The received signal is demultiplexed and fed to a logic analyzer. 8-3 Philips Semiconductors 8. Evaluations Application Note 8.1.3 Optical loop mode: transmitter measurement Attenuated inverted laser signal output LASER APD bias Laser driver 622 MHz clock buffered outputs Electrical input 2.5 GHz clock LEVEL (pin 01) LOS_DCR (pin 04) LOS_D (pin 05) LOCK (pin 10) C78RB C78RB (pin 12) C78TB C78TB (pin 18) Photodiode 50 C78T C78R Receiver out/ DCR in conn's Supply: -8V GND +8V Optical Receiver Optical loop Electrical Transmitter Fig.10 Signal flow with board in optical loop mode, with the transmit part under test. The loop jumpers are removed and the CML level clock and data signal (differential) is applied to the loops' input connectors. The laser signal can be measurd at the laser buffer outputs (LAB and LAB) and at the inverted laser output (LA). 8-4 Philips Semiconductors 8. Evaluations 8.1.4 Application Note Optical loop mode: receiver measurement LASER 50 APD bias Laser driver buffered outputs Electrical input 2.5 GHz clock LEVEL (pin 01) LOS_DCR (pin 04) LOS_D (pin 05) LOCK (pin 10) C78RB C78RB (pin 12) C78TB C78TB (pin 18) Photodiode 50 C78T C78R Receiver out/ DCR in conn's Optical Transmitter Supply: -8V GND +8V Optical loop 19 MHz Electrical Receiver e.g. BER or sampling scope Fig.11 Signal flow with board in Optical loop mode, with the receiver part under test. Optically a signal is applied to the photodioe. The received signal can be monitored at the Receiver out/DCR in connectors. In the figure are the loop jumpers removed for connection of receiving equipment, e.g. a BER receiver or sampling scope 8-5 Philips Semiconductors 8. Evaluations Application Note 8.1.5 Electrical loop mode: high data rate input LASER 50 APD bias Laser driver buffered outputs Transmit data 32 bit, TTL Level shift LEVEL (pin 01) LOS_DCR (pin 04) LOS_D (pin 05) LOCK (pin 10) C78RB C78RB (pin 12) C78TB C78TB (pin 18) 50 C78T Electrical input 2.5 GHz clock Electrical Receiver e.g. BER or sampling scope Electrical Loop C78R Receiver out/ DCR in conn's Supply: -8V GND +8V Received data 32 bit 0.3 - 1.5 V Electrical Transmitter (Pattern Generator) Optical loop 19 MHz DCR reference Fig.12 Signal flow with board in Electrical loop mode. In the setup shown above, the input signal is at the high data rate channels. Connection of the demultiplexer to multiplexer needs a level shift. 8-6 Philips Semiconductors 8. Evaluations 8.1.6 Application Note Electrical loop mode: lowdata rate input LASER 50 APD bias Laser driver 622 MHz clock buffered outputs 78 Mbps Pattern Generator Transmit data 32 bit, TTL LEVEL (pin 01) LOS_DCR (pin 04) LOS_D (pin 05) LOCK (pin 10) C78RB C78RB (pin 12) C78TB C78TB (pin 18) 50 C78T open 622 MHz 0 dBm Electrical input 50 Electrical Loop C78R Receiver out/ DCR in conn's 78 Mbps Logic Analyzer Supply: -8V GND +8V Received data 32 bit 0.3 - 1.5 V Optical loop 19 MHz DCR reference Fig.13 Signal flow with board in Electrical loop mode. In the setup shown above, the input signal is at the low data rate channels. Connection of the multiplexer to demultiplexer is done by the SMA jumpers. 8.2 Performance measurements To illustrate the behaviour of the board, the following measurements are performed: · Bandwidth of receiver with PIN and APD diode · BER vs input power with PIN and APD diode · Transmitted signals The recorded measurements are performed at room temperature. The measurements are performed on board 01. Board 01 is was mounted with optical components with the folling data: 8-7 Philips Semiconductors 8. Evaluations Application Note Photo diode Device: Product: Device#: Wafer-ID: Vbr: V(12) V(4) V(2.7) Mmax Idp id(12) Id(0.9V) F(12) F(17) A BW(2.7) BW(12) TEMP(C) M(0.9Vbr) R ATT InGaAs Avalanche Photodetector 127E 18867 qe2899b1-93 69.6 V Breakdown voltage 64.2 V Voltage at M=12 53.6 V Voltage at M=4 47.9 V Voltage at M=2.7 38 Maximum gain 1.8 nA Primary dark current 31 nA Dark current at M=12 26 nA Total dark current at 0.9 Vbr 4.9 Excess noise factor at M=12 6.4 Excess noise factor at M=17 65 V Gain coefficient 2401 Mx Bandwidth at M=2.7 in MHz 2059 Mx Bandwidth at M=12 in MHz 27.9 Measurement temperature 9.34 Calculated value of A, from value at 0.1 Vbr 0.85 Responsivity at 1550 nm Laser diode Manufacturer: Philips Optoelectronics Centre Type: CQF910/D CQF910/D #4737 Wavelength: 1540.40 RMS Parameter vs. temperature behaviour: Temp Ith Ec Rs V30mA Iop Rntc Ipelt Ms -10 11.4 58 30.2 1.79 55.1 8.1 429 369 25 11.4 57 30.2 1.79 55.7 8.0 57 370 75 11.6 55 30.1 1.78 57.8 7.7 -751 381 Tracking Error max Tracking Erro min Wavelength Rpelt 0.5 -1.2 1538.10 1.282 % (relative to 25 °C) % (relative to 25 °C) nm ohm 8-8 °C mA mW/A Ohm mA mA kOhm mA uA/mW Philips Semiconductors 8. Evaluations 8.3 8.3.1 Application Note Measurement setup Receiver transfer The measurement of the receiver bandwidth has been executed under small signal conditions. The following equipement was used: · HP8702 HP8702 Lightwave component analyzer · HP85047 HP85047 300 kHz - 6 GHz S parameter testset · HP83402A HP83402A 300 kHz - 6 GHz Lightwave source 1300 nm The optical input power was -30 dBm with PIN diode and -40 dBm with Ternary APD. The setup is shown in the figure below. HP8702 HP8702 Lightwave Component Analyzer 50 Poptical I/O Optical STM16 STM16 DEMO BOARD Attenuator OAT I/O 50 HP83402A HP83402A Lightwave Analyzer -Source Fig.14 Frequency Response Measurement at the Receiver-Data & Clock recovery Input/Ouputs 8.3.2 Bit Error Rate versus input power The following equipment was used: · A standard STM16 STM16 system board · 2 x HP 8157A Optical attenuator (ATT) The measurement of the Bit Error Rate was performed with the equipment in the following configuration: -The standard STM16 STM16 system board was used as transmitter and receiver. The STM bit B1/B2 error count was used to measure the bit error rate. -The optical signal was attenuated and fed to the STM16 STM16 demo board. 8-9 Philips Semiconductors 8. Evaluations Application Note -The optical loop was enabled. -The oscilloscope was used to check the waveform at LA. -The output of the board was fed via an attenator to the system board. -The output attenuator was set such that the system board was not overloaded. -A PC was used to read out the value of B1/B2. . Standard STM16 STM16 board Poptical Optical Attenuator HP8157A HP8157A STM16 STM16 DEMO BOARD Optical Attenuator HP8157A HP8157A Optical Transmitter Fig.15 Bit Error Rate Measurement setup. 8.3.3 Eye diagram of transmitted signals The following equipment was used: · A Rohde & Schwarz 376.8011.52 signal generator · A HP83480A HP83480A Digital Cummunications Analyzer, with HP83485A HP83485A optical module · A HP16500A HP16500A logic analyzer with 16520A Pattern generator. The measurement of the output eye diagram was performed with the following setup: -The multiplexer and laser driver were set in "normal" mode. -The signal generator was used to clock the multiplexer at 2.5 GHz and to trigger the Digital Cummunications Analyzer -The pattern generator was triggered with the 78 MHz clock output (JUMB). It applied 32 bit wide 27-1 PRBS to the multiplexer -The optical output signal of the STM16 STM16 demoboard was fed to the Digital Cummunications Analyzer. -The measurement setup is shown in the following figure. 8-10 Philips Semiconductors 8. Evaluations Application Note HP16500/16530A HP16500/16530A Pattern Generator 27-1 PRBS 32 x 78 Mb/s DATA Rhode & Schwarz 376.8011.52 Signal Generator HP3480A HP3480A HP83485A HP83485A 2488.322 MHz Trig OUT Trig splitter JUMB, pin18 32 STM16 STM16 DEMO BOARD Fig.16 Output eye diagram measurement setup. 8-11 CH2 Philips Semiconductors 8. Evaluations Application Note 8.4 8.4.1 Measurement results Receiver transfer PIN Fig.17 Small signal bandwidth, measured at board 01, with PIN photodiode. 8-12 Philips Semiconductors 8. Evaluations Application Note APD Fig.18 Small signal bandwidth, measured at board 01, with APD photodiode. Fig.19 Small signal bandwidth, measured at board 01, results of PIN and APD photodiode measurement. 8-13 Philips Semiconductors 8. Evaluations Application Note Bit Error Rate versus input power 10-3 PIN 10-4 10-5 BER 8.4.2 10-6 10-7 10-8 10-9 10-10 -27 -26.5 -26 -25.5 -25 -24.5 -24 10-11 -23.5 receiver sensitivity/dBm Fig.20 Bit Error Rate (BER), with PIN detector (responsivity diode 0.94 A/W), extinction ratio 10%. 8-14 Philips Semiconductors 8. Evaluations Application Note 10-3 APD 10-4 BER 10-5 10-6 10-7 10-8 10-9 10-10 -35 -34.5 -34 -33.5 -33 -32.5 -32 10-11 -31.5 receiver sensitivity/dBm Fig.21 Bit Error Rate (BER), with APD detector (bias voltage 66.8V), extinction ratio 10%. 8-15 Philips Semiconductors 8. Evaluations Application Note 8.4.3 Eye diagram of transmitted signals Fig.22 Eye diagram of transmitted signal, after reference receiver 8-16 Philips Semiconductors APPENDIX 1 Schematics APPENDIX 1 Application Note Schematics The schematics of the board are hierarchically build up, as shown below. The schematics of the different blocks are shown on the next pages. The original A3 sized schematics are spread over 2 opposite pages, or compressed at one A4 page When applicable, these opposite pages should be read as one schematic. The number of pages indicate how many A4 pages compromise one schematic. b indicates that the part is mounted on the bottom side of the PCB Photo Diode Control Module PDCM A1-2, A1-3 Optical Receive Module ORM A1-4 A1-5 A1-6 Data and Clock Recovery DCR A1-7 A1-8 A1-9 Connectors A1-10 A1-10 A1-11 A1-11 A1-12 A1-12 A1-13 A1-13 A1-14 A1-14 A1-15 A1-15 A1-16 A1-16 Power Supply Module PSM A1-21 A1-21 Optical Transmit Module OTM A1-17 A1-17 A1-19 A1-19 A1-18 A1-18 A1-20 A1-20 A1-1 Philips Semiconductors APPENDIX 1 Schematics Application Note Photo Diode Control Module PDCM/1.drw page 1 of 2 A1-2 Philips Semiconductors APPENDIX 1 Schematics Application Note Photo Diode Control Module PDCM/1.drw page 2 of 2 A1-3 Philips Semiconductors APPENDIX 1 Schematics Application Note b b b Optical Receiver Module ORM/1.drw page 1 of 2 A1-4 Philips Semiconductors APPENDIX 1 Schematics Application Note b b b b A1-5 Optical Receiver Module ORM/1.drw page 2 of 2 Philips Semiconductors APPENDIX 1 Schematics Application Note b Optical Receiver Module ORM/2.drw page 1 of 2 A1-6 Philips Semiconductors APPENDIX 1 Schematics b Application Note b b b Data and Clock Recovery DCR/1.drw page 2 of 2 A1-7 Philips Semiconductors APPENDIX 1 Schematics Application Note Data and Clock Recovery DCR/2.drw page 1 of 2 A1-8 Philips Semiconductors APPENDIX 1 Schematics Application Note b b b b b b b b b b b b b b b b Data and Clock Recovery DCR/2.drw page 2 of 2 A1-9 Philips Semiconductors APPENDIX 1 Schematics Application Note CONEECTORS/1.drw page 1 of 1 A1-10 A1-10 Philips Semiconductors APPENDIX 1 Schematics Application Note CONNECTORS/2.drw page 1 of 2 A1-11 A1-11 Philips Semiconductors APPENDIX 1 Schematics Application Note CONNECTORS/2.drw page 2 of 2 A1-12 A1-12 Philips Semiconductors APPENDIX 1 Schematics Application Note A1-13 A1-13 CONNECTORS/3.drw page 1 of 1 Philips Semiconductors APPENDIX 1 Schematics Application Note CONNECTORS/4.drw page 1 of 2 A1-14 A1-14 Philips Semiconductors APPENDIX 1 Schematics Application Note A1-15 A1-15 CONNECTORS/4.drw page 2 of 2 Philips Semiconductors APPENDIX 1 Schematics Application Note b Optical Transmitl Module OTM/1.drw page 1 of 2 A1-16 A1-16 Philips Semiconductors APPENDIX 1 Schematics Application Note A A lines which do not have an indication "A" or "B" have equal length (e.q. CIN_MUX and CIN_MUX~) A A A B A Linetype "A" Zo=71 length=/4@2.5GHz Linetype "B" Zo=50 length=/2@2.5GHz b A1-17 A1-17 Optical Transmitl Module OTM/1.drw page 2 of 2 Philips Semiconductors APPENDIX 1 Schematics Application Note b b b b b b b Optical Transmit Module OTM/2.drw page 1 of 2 A1-18 A1-18 Philips Semiconductors APPENDIX 1 Schematics Application Note b b b b A1-19 A1-19 Optical Transmit Module OTM/2.drw page 2 of 2 Philips Semiconductors APPENDIX 1 Schematics Application Note b Optical Transmitl Module OTM/3.drw page 1 of 1 A1-20 A1-20 Philips Semiconductors APPENDIX 1 Schematics Application Note b b b b b b b A1-21 A1-21 b Power Supply Module PSM/1.drw page 1 of 1 Philips Semiconductors APPENDIX 1 Schematics Application Note A1-22 A1-22 Philips Semiconductors APPENDIX 2 CML APPENDIX 2 Application Note CML CML, Current Mode Logic, is used in the STM16 STM16 chipset as high speed point to point logic standard. CML has been chosen above ECL, E2CL and PECL for its high immunity against interference in combination with low power consumption. Current Mode Logic is a differential logic standard, defined in a 50 ohm environment. Load impedance is matched to 50 ohm, source is set to 100 ohm, to meet both matching and power consumption recommendations. The main characteristic of this logic standerd are: 1 - Ground plane as reference voltage 2 - Adapted to 50 ohm 3 - Completely differential transport of signals 4 - Low voltage swing The reason for these choices are the following: 1 - Ground plane as reference voltage CML is defined against ground, and not against a bias voltage, as is with ECL. This guarantees a good ground plane, thus high interference immunity. 2 - Adapted to 50 ohm characteristic impedance transmission line CML is defined in a 50 ohm environment. Sources are differential stages with 100 ohm collector resistors. This guarentees a broadband VSWR lower than 3:1. 100 ohm has been chosen to meet both matching- and power consumption requirements. Inputs are on-chip terminated with 50 ohm resistors, guarenteeing a matched broadband load. Due to this good termination, reflection will not travel back to the output of the previous stage. Internal matching guarentees also no parasitic influences of termination resistor pad capacitance. 50 ohm enables the use of standard transmission lines, or coupled (microstrip) transmission lines. 3 - Completely differential transport of signals CML is a completely differential logic. Therefore it has a `built in' high interference immunity. 4 - Low voltage swing Following this high immunity, the voltage swing can be low: 200 mVpp, compared with 800 mVpp for ECL. This reduces the power consumption of the driver stages. A2-1 Philips Semiconductors APPENDIX 2 CML Application Note A2-2 Philips Semiconductors APPENDIX 3 Partslist APPENDIX 3 TABLE 8 Name C11 C12 C13 C21 C22 C24 C31 C32 C33 C41 C42 C43 C202 C203 C204 C205 C206 C207 C208 C209 C210 C211 C212 C213 C214 C215 C216 C217 C218 C219 C220 C221 C226 C227 C228 C229 C230 C231 C232 Application Note Partslist Mounted components Description C EL 7343 # 22M 20 % 35V C EL 7343 # 22M 20 % 35V C 0805H 0805H C0G# 100P 2 % 200V C EL 7343 # 22M 20 % 35V C EL 7343 # 22M 20 % 35V C 0805H 0805H C0G# 100P 2 % 200V C EL 6032 # 10M 20 % 16V C EL 7343 # 22M 20 % 35V C EL 7343 # 22M 20 % 35V C EL 6032 # 10M 20 % 16V C EL 7343 # 22M 20 % 35V C EL 7343 # 22M 20 % 35V C 0805H 0805H X7R# 0M01 10 % 50V C 0805H 0805H X7R# 4700P 4700P 10 % 50V C 0805H 0805H X7R# 0M01 10 % 50V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M01 10 % 50V C 0805H 0805H X7R# 0M01 10 % 50V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M01 10 % 50V C 0805H 0805H X7R# 0M01 10 % 50V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M01 10 % 50V C 0805H 0805H X7R# 0M01 10 % 50V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 1000P 1000P 10 % 50V C 0805H 0805H X7R# 0M01 10 % 50V C 0805H 0805H HQ # 3P3 0,1P 50V C 0805H 0805H X7R# 0M01 10 % 50V C 0805H 0805H C0G# 470P 2 % 50V C 0805H 0805H C0G# 470P 2 % 50V C 0805H 0805H X7R# 0M01 10 % 50V C 0805H 0805H X7R# 0M01 10 % 50V C 0805H 0805H C0G# 47P 2 % 50V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V Name C243 C245 C246 C247 C248 C249 C251 C252 C261 C263 C281 C282 C283 C285 C301 C321 C322 C351 C389 C391 C392 C393 C397 C398 C400 C401 C402 C403 C404 C406 C407 C408 C409 C410 C451 C452 C453 C454 C455 A3-1 Description C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H C0G# 470P 2 % 50V C 0805H 0805H C0G# 470P 2 % 50V C EL 6032 # 10M 20 % 16V C EL 6032 # 10M 20 % 16V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M01 10 % 50V C 1206H 1206H X7R# 4700P 4700P 10 % 200V C 1206H 1206H X7R# 4700P 4700P 10 % 200V C 1206H 1206H X7R# 4700P 4700P 10 % 200V C 0805H 0805H C0G# 100P 2 % 200V C 0805H 0805H X7R# 1000P 1000P 10 % 200V C 0805H 0805H C0G# 100P 2 % 200V C 0805H 0805H C0G# 470P 2 % 50V C 0805H 0805H X7R# 0M01 10 % 50V C 0805H 0805H C0G# 100P 2 % 200V C EL 6032 # 10M 20 % 16V C EL 6032 # 10M 20 % 16V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C EL 6032 # 10M 20 % 16V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M01 10 % 50V C 0805H 0805H X7R# 0M01 10 % 50V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C EL 6032 # 10M 20 % 16V C EL 6032 # 10M 20 % 16V C EL 7343 # 220M 20 % 10V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M01 10 % 50V C 1206H 1206H C0G# 330P 10 % 200V C 0805H 0805H X7R# 0M1 10 % 25V Philips Semiconductors APPENDIX 3 Partslist Application Note TABLE 8 Name C457 C458 C505 C506 C508 C510 C512 C521 C550 C552 C554 C581 C591 C661 C662 C664 C671 C674 C676 C681 C682 C687 C689 C701 C702 C703 C704 C705 C706 C707 C708 C709 C710 C711 C712 C752 C753 C754 C759 C771 Mounted components Description C 0805H 0805H X7R# 0M1 10 % 25V C EL 7343 # 220M 20 % 10V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 1000P 1000P 10 % 50V C 0805H 0805H X7R# 4700P 4700P 10 % 50V C 0805H 0805H X7R# 1000P 1000P 10 % 50V C 0805H 0805H X7R# 1000P 1000P 10 % 50V C 0805H 0805H X7R# 0M1 10 % 25V C EL 3528 # 1M 20 % 35V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H C0G# 100P 2 % 200V C EL 3528 # 1M 20 % 35V C 0805H 0805H HQ # 10P 1 % 50V C 0805H 0805H HQ # 10P 1 % 50V C EL 3528 # 1M 20 % 35V C 0805H 0805H HQ # 10P 1 % 50V C 0805H 0805H HQ # 10P 1 % 50V C EL 3528 # 1M 20 % 35V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C EL 6032 # 10M 20 % 16V C EL 6032 # 10M 20 % 16V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M01 10 % 50V C 0805H 0805H X7R# 0M01 10 % 50V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C EL 6032 # 10M 20 % 16V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C EL 3528 # 1M 20 % 35V C 0805H 0805H X7R# 4700P 4700P 10 % 50V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 1000P 1000P 10 % 50V C 0805H 0805H C0G# 100P 2 % 200V Name C775 C801 C802 C803 C805 C807 C808 C809 C817 C817 C818 C820 C821 C822 C824 C825 C951 C952 C953 C954 C955 C956 C957 EM201 EM201 EM202 EM202 GR1 GR2 GR11 GR21 GR31 GR41 GR201 GR201 GR281 GR281 GR301 GR301 GR321 GR321 GR351 GR351 GR371 GR371 GR451 GR451 GR553 GR553 GR682 GR682 A3-2 Description C 0805H 0805H C0G# 15P 0,25P 50V C EL 7243 # 22M 20 % 20V C EL 6032 # 10M 20 % 16V C EL 7243 # 22M 20 % 20V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H HQ # 1P 0,1P 50V C 0805H 0805H C0G# 100P 2 % 200V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 1000P 1000P 10 % 50V C 0805H 0805H X7R# 0M022 0M022 10 % 50V C 0805H 0805H X7R# 1000P 1000P 10 % 50V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 0805H 0805H X7R# 0M1 10 % 25V C 2220H 2220H X7R# 1M 10 % 50V C 2220H 2220H X7R# 1M 10 % 50V C 0805H 0805H X7R# 0M1 10 % 25V C 2220H 2220H X7R# 1M 10 % 50V C 2220H 2220H X7R# 1M 10 % 50V EMC SHIELD EMC SHIELD TOP SI DIODE # MBRS 340 SI DIODE # MBRS 340 REF-ELEMENT# TL 431AID 431AID REF-ELEMENT# TL 431AID 431AID REF-ELEMENT# TL 431AID 431AID REF-ELEMENT# TL 431AID 431AID 2SI DIODE # BAT 64-07 SI DIODE # BAV 103 SI DIODE # BAV 103 2SI DIODE # BAT 64-07 2SI DIODE # BAT 64-07 REF-ELEMENT# TL 431AID 431AID SI DIODE # MURS 120 SI DIODE # BAV 99 SI DIODE # BAV 99 Philips Semiconductors APPENDIX 3 Partslist TABLE 8 Name GR687 GR687 GR689 GR689 GR801 GR801 GR820 GR820 IC201 IC201 IC202 IC202 IC203 IC203 IC204 IC204 IC205 IC205 IC301 IC301 IC304 IC304 IC305 IC305 IC306 IC306 IC400 IC400 IC451 IC451 IC501 IC501 IC651 IC651 IC661 IC661 IC671 IC671 IC681 IC681 IC701 IC701 IC751 IC751 IC801 IC801 IC820 IC820 IC951 IC951 L202 L203 L204 L205 L206 L207 L251 L252 L261 L262 L281 L391 L392 L401 L402 Mounted components Description SI DIODE # BAV 99 SI DIODE # BAV 99 2SI DIODE # BAT 64-07 2SI DIODE # BAT 64-07 TRIMP-AMP # CIC 100BCP 100BCP GAAS MAIN-AMP # OQ 2538S1CP 2538S1CP BIPO 2OP-AMP # 2272AEP 2272AEP CMOS 2OP-AMP # 2272AEP 2272AEP CMOS 4NAND-2INP # 74ACT00EP 74ACT00EP CMOS 2OP-AMP # 2272AEP 2272AEP CMOS 2OP-AMP # 2272AEP 2272AEP CMOS 4SWI BILATR# 74HC4066EP 74HC4066EP CMOS 4NAND-2INP # 74ACT00EP 74ACT00EP CMOS DMUX 1:32 # OQ 2536EP 2536EP BMOS VLG RGT PWM# 750EP 750EP BIPO DCR/VCO-16 DCR/VCO-16 # OQ 2541-C3CP 2541-C3CP BIPO 2OP-AMP # 2272AEP 2272AEP CMOS 8BU-DRV TST# 74ABT244EP 74ABT244EP BMOS 8BU-DRV TST# 74ABT244EP 74ABT244EP BMOS BTL BUS TRC# 3205EP 3205EP BMOS MUX 32:1 # OQ 2535C4EP 2535C4EP BMOS DCR/VCO-16 DCR/VCO-16 # OQ 2541-C3CP 2541-C3CP BIPO LD-16 LD-16 # OQ 2545CP 2545CP BIPO 2OP-AMP # 2272AEP 2272AEP CMOS 2 OP-AMP # 2904EP 2904EP BIPO INDUCTOR # 1U 10 % 1A8 CHOKE-CHIP# 1206 INDUCTOR # 1U 10 % 1A8 CHOKE-CHIP# 1206 INDUCTOR # 1U 10 % 1A8 CHOKE-CHIP# 1206 INDUCTOR # 100U 10 % 0A25 INDUCTOR # 10U 10 % 0A69 INDUCTOR # 1U 10 % 1A8 CHOKE-CHIP# 1206 CHOKE-CHIP# 1206 INDUCTOR # 100U 10 % 0A25 INDUCTOR # 100U 10 % 0A25 INDUCTOR # 10U 10 % 0A69 INDUCTOR # 10U 10 % 0A69 Application Note Name L403 L404 L451 L452 L550 L581 L661 L671 L681 L682 L701 L702 L703 L704 L750 L801 L802 L803 L807 L818 M221 M222 M223 M224 OT201 OT201 OT201 OT201 OT601 OT601 OT602 OT602 OT603 OT603 OT604 OT604 OT611 OT611 OT612 OT612 OT621 OT621 OT622 OT622 OT623 OT623 OT624 OT624 OT631 OT631 OT632 OT632 OT641 OT641 OT642 OT642 A3-3 Description INDUCTOR # 1U 10 % 1A8 INDUCTOR # 1U 10 % 1A8 INDUCTOR # 100U 10 % 0A25 INDUCTOR # 100U 10 % 0A25 CHOKE-CHIP# 1206 CHOKE-CHIP# 1206 CHOKE-CHIP# 1206 CHOKE-CHIP# 1206 CHOKE-CHIP# 1206 CHOKE-CHIP# 1206 INDUCTOR # 10U 10 % 0A69 INDUCTOR # 10U 10 % 0A69 INDUCTOR # 1U 10 % 1A8 CHOKE-CHIP# 1206 CHOKE-CHIP# 1206 INDUCTOR # 100U 10 % 0A25 INDUCTOR # 10U 10 % 0A69 INDUCTOR # 10U 10 % 0A69 CHOKE-CHIP# 1206 CHOKE-CHIP# 1206 WRAPSTIFT WRAPSTIFT WRAPSTIFT WRAPSTIFT PHOTODIODE PHASE SIU SCHIRMNR PHOTODIODE PHASE SIU SCHIRMNR LED # LYT 670-JK 670-JK GE LED # LYT 670-JK 670-JK GE LED # LYT 670-JK 670-JK GE LED # LYT 670-JK 670-JK GE LED # LYT 670-JK 670-JK GE LED # LYT 670-JK 670-JK GE LED # LST 670-HK 670-HK RT LED # LST 670-HK 670-HK RT LED # LGT 670-JK 670-JK GN LED # LGT 670-JK 670-JK GN LED # LYT 670-JK 670-JK GE LED # LYT 670-JK 670-JK GE LED # LYT 670-JK 670-JK GE LED # LYT 670-JK 670-JK GE Philips Semiconductors APPENDIX 3 Partslist Application Note TABLE 8 Name OT651 OT651 OT652 OT652 OT801 OT801 OT801 OT801 Q581 R11 R12 R13 R21 R22 R23 R24 R31 R32 R33 R34 R35 R36 R37 R41 R42 R43 R44 R45 R46 R47 R48 R201 R203 R204 R208 R210 R211 R212 R213 R215 R216 R217 R218 R220 Mounted components Description LED # LYT 670-JK 670-JK GE LED # LYT 670-JK 670-JK GE LASERDIODE PHASE 2.5GB/S SCHIRM LASERDIODE PHASE 2.5GB/S SCHIRM Q-OSZILLATOR 38M88 38M88 VCXO R 0805 100# 825E 1 % 0W1 R 0805 100# 2K15 1 % 0W1 R 0805 100# 2K15 1 % 0W1 R 0805 100# 1K 1 % 0W1 R 0805 100# 53E6 1 % 0W1 R 0805 100# 634E 1 % 0W1 R 0805 100# 2K15 1 % 0W1 R 0805 100# 464E 1 % 0W1 R 0805 100# 51E1 1 % 0W1 R 0805 100# 147E 1 % 0W1 R 0805 100# 33E2 1 % 0W1 R 0805 100# 33E2 1 % 0W1 R 0805 100# 261E 1 % 0W1 R 0805 100# 205E 1 % 0W1 R 0805 100# 464E 1 % 0W1 R 0805 100# 51E1 1 % 0W1 R 0805 100# 147E 1 % 0W1 R 0805 100# 33E2 1 % 0W1 R 0805 100# 33E2 1 % 0W1 R 0805 100# 121E 1 % 0W1 R 0805 100# 75E 1 % 0W1 R 0805 100# 121E 1 % 0W1 R 0805 100# 10K 1 % 0W1 R 0805 100# 51E1 1 % 0W1 R 0805 100# 51E1 1 % 0W1 R 0805 100# 51E1 1 % 0W1 R 0805 100# 215E 1 % 0W1 R 0805 100# 75E 1 % 0W1 R 0805 100# 5K62 1 % 0W1 R 0805 100# 5K62 1 % 0W1 R 0805 100# 10K 1 % 0W1 R 0805 100# 10K 1 % 0W1 R 0805 100# 82K5 1 % 0W1 R 0805 100# 82K5 1 % 0W1 R 0805 100# 10K 1 % 0W1 Name R221 R222 R223 R224 R225 R226 R227 R228 R228 R229 R230 R231 R232 R235 R235 R241 R242 R243 R261 R262 R263 R264 R265 R266 R267 R268 R281 R282 R283 R284 R285 R301 R302 R303 R304 R305 R306 R306 R307 R321 A3-4 Description R 0805 100# 147K 1 % 0W1 R 0805 100# 10K 1 % 0W1 R 0805 100# 147K 1 % 0W1 R 0805 100# 1K 1 % 0W1 R 0805 100# 10K 1 % 0W1 R 0805 100# 2K74 1 % 0W1 R 0805 100# 4K64 1 % 0W1 ALIGN R 100 # 211 3711 1 % 0805 ALIGN R 100 # 211 3711 1 % 0805 R 0805 100# 4K64 1 % 0W1 R 0805 100# 27K4 1 % 0W1 R 0805 100# 27K4 1 % 0W1 R 0805 100# 4K64 1 % 0W1 ALIGN R 100 # 211 3711 1 % 0805 ALIGN R 100 # 211 3711 1 % 0805 R 0805 100# 10E 1 % 0W1 R 0805 100# 10E 1 % 0W1 R 0805 100# 51E1 1 % 0W1 R 0805 # 0E R 0805 # 0E R 0805 # 0E R 0805 # 0E R 0805 100# 464E 1 % 0W1 R 0805 100# 56E2 1 % 0W1 R 0805 100# 464E 1 % 0W1 R 0805 100# 56E2 1 % 0W1 R 0805 100# 1K21 1 % 0W1 R 0805 100# 1K 1 % 0W1 R 0805 100# 2K15 1 % 0W1 R 0805 100# 100E 1 % 0W1 R 0805 100# 51E1 1 % 0W1 R 0805 100# 21K5 1 % 0W1 R 0805 # 0E R 0805 100# 1K 1 % 0W1 R 0805 100# 332E 1 % 0W1 R MINI-M 50# 1M 1 % 0W25 R MINI-M 50# 34K8 1 % 0W25 R MINI-M 25# 100K 0,25% 0W25 R 0805 # 0E R 0805 100# 10K 1 % 0W1 Philips Semiconductors APPENDIX 3 Partslist TABLE 8 Name R322 R323 R329 R331 R351 R370 R371 R372 R373 R374 R375 R375 R376 R377 R378 R378 R379 R379 R380 R388 R391 R391 R392 R392 R394 R401 R411 R412 R413 R414 R415 R416 R417 R418 R419 R420 R421 R422 R423 R424 Mounted components Description R 0805 100# 1M 1 % 0W1 R 0805 100# 10K 1 % 0W1 R 0805 100# 10K 1 % 0W1 R 0805 100# 10K 1 % 0W1 R 0805 100# 3K32 1 % 0W1 R 0805 100# 82K5 1 % 0W1 R 0805 100# 100E 1 % 0W1 R 0805 100# 8K25 1 % 0W1 R 0805 100# 12K1 1 % 0W1 R 0805 100# 10K 1 % 0W1 R 0805 100# 562E 1 % 0W1 R 0805 100# 1K 1 % 0W1 R 0805 100# 4K64 1 % 0W1 R 0805 100# 8K25 1 % 0W1 ALIGN R 100 # 211 3711 1 % 0805 ALIGN R 100 # 211 3711 1 % 0805 ALIGN R 100 # 211 3711 1 % 0805 ALIGN R 100 # 211 3711 1 % 0805 R 0805 100# 10K 1 % 0W1 R 0805 100# 1M 1 % 0W1 R 0805 100# 27K4 1 % 0W1 R 0805 100# 10K 1 % 0W1 R 0805 100# 38K3 1 % 0W1 R 0805 100# 10K 1 % 0W1 R 0805 100# 4K64 1 % 0W1 R 0805 100# 21E5 1 % 0W1 R 0805 100# 21E5 1 % 0W1 R 0805 100# 21E5 1 % 0W1 R 0805 100# 21E5 1 % 0W1 R 0805 100# 21E5 1 % 0W1 R 0805 100# 21E5 1 % 0W1 R 080