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STM-3/STS-12

Catalog Datasheet MFG & Type PDF Document Tags

STM-16

Abstract: DD1043 between the PM5312 STTX (STM-l/STS-3 to STM-3/STS-12 mux/demux) or the PM5355 S/UNI-622 User Network , -48c Mode (User Controlled) · Optionally Combines Four STM-4/STS-12 Data Streams into One Serial STM-16/STS , Separates One Serial STM-16/STS-48 Data Stream into Four STM-4/STS-12 Data Streams According to the SDH , ierra P M 5 3 IV P M S3SS P M 53I V P M S3 5 5 P M C -S ierra PM S3W PM S3SS S T M -l/S T S -3 or A T M /U N I Interface PMC-Sierra P M S3J2/ P M 53S3 S T M -l/S T S -3 or A T M A JN I in te rfa c e
-
OCR Scan
STM-16 DD1043 STM-16 book dd1041 PM5312/5355 STS-48 STM-4/STS-12 VSC8023/8024 16/STS-48 VSC8023
Abstract: STM-3/STS-12 mux/demux) or the PM5355 S/UNI-622 User Network Inter­ face device and a SDH/SONET , frame pulses are con­ nected to TXFPIN[3:0] and are used for verifying that the four STS-12/STM -4 , buffering. The frame pulses RXFPIN[3:0] (active high) associated with each of the four STS-12/STM-4 data , ) VSC8023 (MUX) â'¢ SDH/SONET compliant multiplexing of four by te-wide STM-4/STS-12 data streams into one , -48 data stream into four byte-wide STM-4/STS-12 data streams â'¢ Frame Synchronous Scrambling -
OCR Scan
VSC8023/VSC8024 VSC8024 STM-3/STS-12 G-52129-0

DA1042

Abstract: DA1041 chipset is designed to provide a SDH/SONET compliant interface between the PM5312 STTX (STM-1/STS-3 to STM-3/STS-12 mux/demux) or the PM5355 S/UNI-622 User Network Interface device and a SDH/SONET compliant , connected to TXFPIN[3:0] and are used for verifying that the four STS-12/STM-4 input data streams are , four STS-12/STM-4 input frames (refer to Synchronous Reset Timing Diagram, Figure 3). The `reset , /SONET compliant multiplexing of four byte-wide STM-4/STS-12 data streams into one serial STM-16/STS
Vitesse Semiconductor
Original
DA1042 DA1041 DA1043 PM5312/ G52129-0

DA1041

Abstract: vsc8024 (STM-1/STS-3 to STM-3/STS-12 mux/demux) or the PM5355 S/UNI-622 User Network Interface device and a SDH , connected to TXFPIN[3:0] and are used for verifying that the four STS-12/STM-4 input data streams are , TXFPIN[3:0] (active high) associated with each of the four STS-12/STM-4 data streams are used to , ) · SDH/SONET compliant multiplexing of four byte-wide STM-4/STS-12 data streams into one serial STM , into four byte-wide STM-4/STS-12 data streams · Frame Synchronous Scrambling (optional) · Frame
Vitesse Semiconductor
Original
demux ic pdf of 741 ic T14 N03
Abstract: interface between the PM5312 STTX (STM-l/STS-3 to STM-3/STS-12 mux/demux) or the PM5355 S/UNI-622 User , Input Synchronization below). TXFPIN[3:0] is captured on the rising edge of TXCLKIN. The four STS-12 , the four STS-12/STM-4 input frames (refer to Synchronous Reset Timing Diagram, Figure 3). The , four byte-wide STM-4/STS-12 data streams into one serial STM-16/STS-48 data stream â'¢ SDH/SONET compliant demultiplexing of one serial STM-16/STS-48 data stream into four byte-wide STM-4/STS-12 data -
OCR Scan
PMS312J PM53S5 PM5312J VSC8023A/SC8024

DA1042

Abstract: MIAL capacitor STM-3/STS-12 mux/demux) or the PM5355 S/UNI-622 User Network Inter face device and a SDH/SONET , [3:0] and are used for verifying that the four S T S-12/ST M -4 input data stream s are synchronized , frame pulses TXFPIN[3:0] (active high) associated with each of the four STS-12/STM-4 data streams are , compliant multiplexing of four byte-wide STM-4/STS-12 data streams into one serial STM-16/STS-48 data stream , -4/STS-12 data streams · Frame Acquisition · Frame Synchronous Descrambling (optional) · B 1 Error
-
OCR Scan
MIAL capacitor BL DC 80 M02 192TBGA

TSOT1610GP-YB21

Abstract: MARS10G from STS-3/STM-1 to STS-192c/STM-64c. ! ! * In this document, receive is used to indicate the , concatenated payloads must begin on an STS-3/ STM-1 boundary. n x m @ z Mbits/s = n groups of m lines are , port is an STS-12/STM-4. Each line of a 2.5 Gbits/s backplane port is either an aggregate of four STS-12 , loopback on the secondary line interface. Self-test: - Built-in PRBS generator and monitor with STS-12 , LS TRIB CARD MARS10G T-Pro Figure 3. Mate-Port Connect Using 622 MHz Interface with Cross
Agere Systems
Original
TSOT1610G TSOT1610GP-YB21 el12n 1724-pin TSOT1610GP 0AA00 TSOT1610GP/GPD STS-192/STM-64 DS02-154SONT DS03-065SONT

HP8560

Abstract: XRT91L30IQ xr XRT91L30 PRELIMINARY STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER JANUARY 2006 , SONET/SDH 622.08 Mbps STS-12/ STM-4 or 155.52 Mbps STS-3/STM-1 applications. The transceiver includes , FIGURE 1. BLOCK DIAGRAM OF XRT91L30 STS-12/STM-4 or STS-3/STM-1 TRANSCEIVER 8x9 FIFO WP TXDI[7:0 , ALOOP DLOOP RLOOPS LOOPTIME Reset STS-12/STS-3 CAP2N CAP2P CAP1N CAP1P , /STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER xr REV. P1.0.8 FEATURES · Targeted for SONET STS-12
Exar
Original
HP8560 XRT91L30IQ 736XR GR-253 GR-253-CORE P1596 STS-12/STM-4 STS-12/

STM-1

Abstract: XRT91L30IQ xr XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER DECEMBER 2006 REV. 1.0.1 , STS-12/ STM-4 or 155.52 Mbps STS-3/STM-1 applications. The transceiver includes an on-chip Clock , DIAGRAM OF XRT91L30 STS-12/STM-4 or STS-3/STM-1 TRANSCEIVER PISO (Parallel Input Serial Output , www.exar.com XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER xr REV. 1.0.1 FEATURES · Targeted for SONET STS-12/STS-3 and SDH STM-4/STM-1 Applications · Selectable full duplex operation
Exar
Original
STM-1 826XR
Abstract: Termination of a single 622 Mbits/s STS-12/ STM-4, or single 155 Mbits/s STS-3/STM-1. I Framing for 84 , recovery circuit at 622 Mbits/s STS-12/STM-4 interface, or at 155 Mbits/s STS-3/STM-1 (can be deselected , -1 into STS-3/STS-12 via pointer processing. I Maps T1/E1/J1 into VT/TU (including DS1 into TU-12 , structures into STS-1, STS-3/STM-1, and STS-12/STM-4: â'" STS-12/STM-4 â'" STS-3/STS-1/SPE/VTG/VTx â , either an OC-12/STM-4 or OC-3/STM-1 optical signal directly or to allow for modular growth in terminal Agere Systems
Original
TMXF84622 M13/E13 30L-15P-BA PB01-092PDH PB01-053PDH

PEB2757AE

Abstract: STM-16 -192/STM64 or mix of sixteen MUX/DEMUX channels of STS-48/STM-16 or STS-12/STM-4 or STS-3/STM-1 (in groups , sixteen STS-12/STM-4 and STS-3/ STM-1 signals in serial 2.5 Gbit/s or serial 622 Mbit/s or serial 155 , provides corresponding functionality in the DEMUX direction. mix of sixteen STM-12/STM-4 and STS-3/STM , of STS-48/STM16 or STM-12/STM-4 or STS-3/STM-1 streams · Provides interfaces for dropping alarm , /12/3 APPLICATION FIGURE 2. PEB2757AE IN 16 X OC48/12/3 APPLICATION 2 REV. 1.0.0
Exar
Original
STM-64 SFI4 STS-192/STM64 STS-192/ STS-48/ STM-12/STM-4 GR-1377

STM-16

Abstract: four bytes at a time, where as STS-3/STM-1 and STS-12/STM-4 is accomplished one byte at a time , / Revision F SONET/SDH OC-12 TO OC-48 MUX/DEMUX 3. The SYNCRSTB will be removed (de-asserted high) from , transmitted over the number one STS-12/STM-4 data stream. The other 3 STS-12/STM-4 M1 bytes will be inserted , , 2001 / Revision F SONET/SDH OC-12 TO OC-48 MUX/DEMUX Table 3. Transmitter Output Pin Assignment , ] 311DATOUTP[6] 311DATOUTN[7] 311DATOUTP[7] VSS VDD PULSEN PULSEP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Applied Micro Circuits
Original
OC-12 S3045 S3041/S3042 D264/R477
Abstract: XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER JULY 2008 REV. 1.0.2 GENERAL , Switch/Routers · DSLAMS · SONET/SDH Test Equipment · DWDM Termination Equipment STS-12/STM-4 or STS-3 , CA, 94538 · (510) 668-7000 · FAX (510) 668-7017 · www.exar.com STS-12/STS-3 CDRREFSEL LOOPTIME PIO_CTRL RLOOPS DLOOP ALOOP Reset XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER FEATURES REV. 1.0.2 · Targeted for SONET STS-12/STS-3 and SDH STM-4/STM Exar
Original
OC-12/3 XRT91L31IQ-F XRT91L31IQ QFP64

TMXE84622

Abstract: e1 E2 e3 liu transceiver LOPOH 6 CHI/PSB High-Speed IF 622 Mb/STS-12/STM-4 155 Mb/STS-3/STM-1 Clock and Data 8 TMUX Clock/Sync CG 5 Protection Link 622 Mb/STS-12/STM-4 155 Mb/STS-3/STM-1 Clock and Data 8 STS-12/ STM-4/ STS-3/ STM-1 42 S T S X C CDR (x3) 24 MPU (x3) x28/x21 VTMPR 24 DS1/J1/E1 DS2/E2 DS3/E3 JTAG IF 49 12 MPU IF STS-3/STM-1 Mate , STS-12/STM-4/STS-3/STM-1/STS-1 selectable scrambler/descrambler functions. s Provides B1/B2/B3
Agere Systems
Original
TMXE84622 e1 E2 e3 liu transceiver S8064 AI84 stm tpm febe 4e 4e DS03-190MPIC

91L31

Abstract: capacitor 102 STM xr XRT91L31 Preliminary STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER DEC 2006 REV , 622.08 Mbps STS-12/ STM-4 or 155.52 Mbps STS-3/STM-1 applications. The transceiver includes an on-chip , DIAGRAM OF XRT91L31 STS-12/STM-4 or STS-3/STM-1 TRANSCEIVER PISO (Parallel Input Serial Output , CMUFREQSEL LOSEXT DLOSDIS Clock Control OOF FRAMEPULSE LOOPTIME Reset STS-12/STS-3 , www.exar.com XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER xr REV. 1.0.2 FEATURES ·
Exar
Original
91L31 capacitor 102 STM

S4802

Abstract: STS-48 up to 4 x STS-12/STM-4 or 16 x STS-3/STM-1s. ·Demultiplexes 4 x (STS-12/STM-4 or 4 STS-3/STM , : ·Multiplexes 4 x (STS-12/STM-4 or 4 STS-3/STM-1) tributaries into an STS-48/STM-16 or bypass for STS-48/STM , Sections) Generators for STS-12/STM-4 and/or STS-3/STM-1 outputs. ·Built In 48x48 cross-connect for STS-1 level cross-connection or add/drop. ·STS-12/STM-4 and/or STS-3/STM-1 frame synchronous scramblers. ·4 x (STS-12/STM-4 or 4 STS-3/STM-1) or STS-48/STM-16 framers. Applications: ·STS-48/STM
Applied Micro Circuits
Original
S4802 Fiber Optic regenerator XCVR STS-48/STM-16- FRGEN48 S3024
Abstract: .12 4.5 Single-Chip Dual OC-3 with MSP 1 + 1 Protection Application , .12 Figure 3-5. Single-Chip Dual OC-3 with MSP 1 + 1 Protection Application , ), and loss-of-clock (LOC) detection. s Provides STS-12/STM-4/STS-3/STM-1/STS-1 selectable scrambler/descrambler functions. s Provides B1/B2/B3 generation/detection for STS-12/ STM-4/STS-3/STM-1/STS-1. s Provides STS-12/STM-4/STS-3/STM-1/STS-1 pointer interpretation. s Complies with Agere Systems
Original
TMXL33625 622/155M DS03-078BBAC-3 DS03-078BBAC-2

XRT91L30IQ

Abstract: GR-253 XRT91L30 JUNE 2007 Rev. 1.0.2 STS-12/STM-4 or STS-3/STM-1 SONET/SDH TRANSCEIVER Network & Transmission Products XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER NOTES: II REV. 1.0.2 XRT91L30 REV. 1.0.2 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER TABLE OF CONTENTS , . 12 1.1 STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION , . 12 TABLE 3: DATA INGRESS TO DATA EGRESS LATENCY
Exar
Original
optical receiver datasheet STM 1 optical transceiver datasheet STM 1 serial to parallel data converter of 23 pins Cross Reference to Exar

24C024

Abstract: RD237 Intel® WB1510 SDH/SONET 2 × STM-4/STS-12 or STM-1/STS-3 Framer Datasheet Order Number , -4/STS-12 or STM-1/STS-3 Framer may contain design defects or errors known as errata which may cause the , . 66 3.9.1.2 Example 2: 8 bit × 77.76 MHz STM-4/STS-12 DROP Bus Carrying AU-3/STS-1 only . 67 3.9.1.3 Example 3: 8 bit × 77.76 MHz STM-4/STS-12 DROP Bus Carrying AU-4-4c/STS , . 72 3.9.2.2 Example 2: 8 bit × 77.76 MHz STM-4/STS-12 ADD Bus Carrying AU-3/STS-1 only
Intel
Original
24C024 RD237 298029 5/99-064R2 5/99-066R1 5/00-126R2 5/00-129R1

GR-253-CORE

Abstract: TMXA84622 High-Speed IF 6 Protection Link 622 Mb/STS-12/STM-4 155 Mb/STS-3/STM-1 Clock and Data 8 STS-12 , /E1 VT/TU DS2/E2 DS3/E3 (x3) x28/x21 VTMPR 5 49 12 (Total of 3 STS-1 Max) 344 , LOPOH 622 Mb/STS-12/STM-4 155 Mb/STS-3/STM-1 Clock and Data 8 6 1 6 1 E2, DS2 , ), loss-of-frame (LOF), and loss-of-clock (LOC) detection. s Provides STS-12/STM-4/STS-3/STM-1/STS , -4/STS-3/STM-1/STS-1. s Provides STS-12/STM-4/STS-3/STM-1/STS-1 pointer interpretation. s
Agere Systems
Original
TMXA84622 VC12 DS03-075BBAC-1 DS03-075BBAC
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