STLC3040 PLCC44 STLC3040-TR SEL24 L3000N L3000S STLC3170 D94TL161D D95TL204B - Datasheet Archive

 

® SUBSCRIBER LINE INTERFACE CODEC FILTER, COFISLIC PRELIMINARY DATA November 1998 PLCC44 ORDERING NUMBERS: STLC3040

 

STLC3040 STLC3040 ® SUBSCRIBER LINE INTERFACE CODEC FILTER, COFISLIC PRELIMINARY DATA November 1998 PLCC44 PLCC44 ORDERING NUMBERS: STLC3040 STLC3040 STLC3040-TR STLC3040-TR SEL24 SEL24 TS2 TS1 STR3 TS0 DGND VDD FSC DCL DD DU Figure 1: Pin Connection (Top view) 6 5 4 3 2 1 44 43 42 41 40 IO1 7 39 O1 IO2 8 38 I1 C1 9 37 SIR2 C2 10 36 MR VL1 VL2 11 12 35 34 IDH VCC SIR0 13 33 VEE CAP 14 32 IDM IL 15 31 IDL RAC 16 30 STR2 SIR1 17 29 EXT PDO VOUT AGND STR1 VBIM REF RDC CAC ACDC IT 18 19 20 21 22 23 24 25 26 27 28 STR0 Single chip CODEC and FILTER including all LOW-VOLTAGE SLIC functions. Advanced 12V BJT, 5V CMOS 0.8um technology. Low external component count. Over-sampling A/D and D/A conversion. No functional trimming or adjustments required. Serves a wide range of specifications; i.e. ITUT, LSSGR. A-law, and µ-law PCM and Linear voice coding, sw selectable GCI compatible interface. Programmable Digital-Filters for impedancematching, hybrid-balance, frequency-response and gain. Programmable Feeding-Resistance (2 x 50 to 2 x 400) and current-limiting (0-69.3mA). Programmable voltage-drop according to transmission needs. 12kHz/16kHz Teletax Generation with Programmable Level 0-10 Vrms in 40mV steps including shaping and filtering. Integrated Ring-Generator with Zero-Crossing. Programmable frequency from 16.6Hz to 60Hz, programmable level up to 85Vrms, Integrated auto ring-trip. Signalling functions ON/OFF - Hook, Gnd-key with filter and Programmable persistence check. Advanced test capabilities: On-board line tests and circuit tests. Signalling tests for meterpulse TTX and Ringing. Tone generator for circuit test. 3 Loop-back paths. Three operating conditions: Power Down, Active, Ringing. Off-hook programmable threshold-level in each of these conditions. Interface to High-Voltage SLIC to select modes, provide hard or soft Polarity-Reversal and sense HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) High Thermal condition. On-hook transmission capability. Selectable 2/4MHz backplane clock. Standard PLCC 44 package. D94TL161D D94TL161D On chip Line-card identification. DESCRIPTION The subscriber line codec-filter, STLC3040 STLC3040, is fabricated in BiCMOS (12V bipolar / 5V CMOS) technology. It uses Digital-Signal-Processing(DSP) to implement central-office telephone interface features: DC-feed, Supervision, PCMCodec-Filter, Ring, Teletax metering (TTX) and Test functions. The STLC3040 STLC3040 is fully programmable and needs few external resistors and capacitors. The STLC3040 STLC3040 interfaces the subscriber's line via the High-Voltage (HV) (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) device and the central-office back1/49 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. STLC3040 STLC3040 DESCRIPTION (continued) plane via a GCI compatible interface (see fig.2). The GCI handles all STLC3040 STLC3040 control and voice channel. The STLC3040 STLC3040 processes the transversal linecurrent sensed by the ST HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) Line Driver Circuit and generates voltage-drive to the line via the HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170), thus synthetizing the impedances required by various world administrations . Line impedances as well as the two-to-four wire conversion synthesis are software programmable. Also Transmit (Tx) and Receive(Rx) AC frequency­response, determined by DSP-filters, guarantee voice-band flat-response. Tx and Rx Gains are programmable as well. Digitized voice can be encoded on A-law or u-law. The DC characteristic is obtained by selecting limit-current value, DC-feed resistance (2 X 50 steps) and Drop-voltage. It also permits On-hook transmission and TTX pulse injection with filtering and shaping. TTX metering pulse generation (12 or 16kHz) has programmable amplitude up to 10 Vrms. Off-hook detection with programmable thresholds is possible in all operating modes as described in section 4. Ring-signal with zero-crossing start/stop injection is generated on chip with programmable frequency and amplitude. In addition, when Ringtrip is detected, the Ring-signal is automatically disconnected at the next zero-crossing. Power consumption is kept low by providing a "Power-Down" mode where the HV-SLIC is switched off (Power Denial). A set of internal resistors connected to the line allows Off-hook detection in this mode. Overall power dissipation is around 50mW (max.) in Power Down mode. Several testing features are included in the STLC3040 STLC3040, both for self-test and to test line leakage, capacitance .etc, thus saving on test equipment and relays. Measured DC quantities are digitized and sent via the B1 voice channel to the backplane. With proper software selection each signal can be modulated by a 1KHz carrier before being sent to B1 voice channel. Programmable linear code, software selectable, boosts the calculation resolution. Sigma-Delta converters (ASD: Analog, DSD: Digital) make the conversion independent of technology parameters (fig. 3). Figure 2: Functional Diagram. LV STLC3040 STLC3040 HV L3000N L3000N FSC DCL DIGITAL SIGNAL PROCESSOR GCI INT. DU VOUT VIN TIP DD RING RP2 A=-20 Iline IT IT IL ANALOG FRONT END IL PDO C2 HV CONTROL C1 CURRENT SENSORS REF C2 C1 VBIM CDVB ACDC CAP RAC CAC RDC REF VCC D95TL204B D95TL204B STLC3040 STLC3040 PIN DESCRIPTION (This list is grouped according to Function) N. Symbol Type (*) POWER SUPPLY 1 DGND PS 2 VDD PS 27 AGND PS 33 VEE PS 34 VCC PS 2/49 RP1 A=20 Description Digital Ground +5V Digital Supply Voltage Analog Ground -5V Analog Supply Voltage +5V Analog Supply Voltage ITIP IRING STLC3040 STLC3040 STLC3040 STLC3040 PIN DESCRIPTION (continued) N. GCI 40 Symbol Type (*) SEL24 SEL24 DI 43,42, TS0,TS1, DI 41 TS2 3 FSC DI 4 DCL DI 5 DD DI 6 DU OD INTERFACE TO HV SLIC 9 C1 AI/O 10 C2 AO 28 PDO AO 11,12 VL1, VL2 AI 15 19 25 26 IL IT VBIM VOUT AI AI AI AO Description Select Clock Frequency for GCI Interface 2MHz/4MHz not affecting the data rate (2Mbit/s) If SEL24 SEL24 = 0, Clock Frequency = 2048KHz If SEL24 SEL24 = 1, Clock Frequency = 4096KHz GCI Select Time Slot Identifier Pins Frame Sync 8kHz GCI Interface Master Data Clock GCI Interface Data Down link GCI Interface Data Up link GCI Interface (Open Drain Driver) State Control Signal 1. Combination of C1 and C2 defines HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) operating mode. Current sense for thermal indication. State Control Signal 2. Combination of C1 and C2 defines HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) operating mode. Power down output. Proper bias current is provided toHV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) by this pin. When the current is 0 the HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) goes in Power Denial (high impedance). Proper combinations of PDO with C1, C2 set additional operating modes for STLC3170 STLC3170 High Voltage Interface. Comparator Input. These are inputs of the comparator that senses the line voltage in Power Denial allowing Off/Hook detection in this mode. Longitudinal Line-Current input IL = (ITIP - IRING)/100. Transversal Line-Current input IT=(ITIP + IRING)/100. Battery image monitor. Output feeding the line voltage (DC, AC, RING, TTX) through H.V. HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170). I/O 7, 8 IO1, IO2 DI/O Programmable GCI controlled I/O. 39 O1 DO Digital output written via GCI. 38 I1 DI Digital input read via GCI. MISCELLANEOUS FUNCTION 29 EXT DI External Ring Sync. Input. 36 MR DI Master Reset Input. Active High. The STLC3040 STLC3040 is forced in Loop-open and internal registers are preset to default values. 31,32 IDL, IDM AI Identification Code Signals, M+L ternary digits 35 IDH DI H most significant bit, L least significant bit. 14 CAP AI/O Capacitor must be connected to this pin. Its value defines the Soft Battery Reversal slope. 16 RAC AI/O AC-Synthesis Reference Resistor. 20 ACDC AI/O AC/DC Line Split. Scaled line-current output, DC feedback input. 21 CAC AI Splitter Capacitor. Scaled AC line-current input. 22 RDC AI DC-Synthesis Reference Resistor. 23 REF AI/O Reference Voltage Output. A resistor on this pin sets the internal reference current. UNUSED 18,24 STR0,STR1 DI/O Reserved for testing, must be shorted to DGND. 30,44 STR2,STR3 13,17 SIR0, SIR1 DI/O Must be left open. 37 SIR2 DI/O Can be left open (*) Type AI AO AI/O Description Analog Input Analog Output Analog Input/Output Type DI PS DI/O Description Digital Input Chip Power/Ground Digital Input/Output Type DO OD Description Digital Output Open Drain Output 3/49 STLC3040 STLC3040 different conditions are present and depend on loop resistance. a) Resistive Feed Region: the SLIC kit operates as a voltage source with a series resistance equal to (2Rp+n 2 50), where n can be programmed from 1 to 8 via CR8 register. Various values of voltage drops are possible as shown in Fig. 4. b) Constant current region: when IL reaches the programmed limiting current value (from 0 to 69.3mA; 1.1mA step via CR6 register), the Kit operates as a proper constant current source. (see Fig. 4). Concerning AC Processing the AC current-signal is converted to voltage on the reference resistor RAC (1620). Line impedance (real or complex) synthesis is carried out thanks to programmable filters. All the filters are integrated in the digital side of COFISLIC except the so called KA filter that is in the Analog Front End. KD and Z (in digital side) filters allow to match the line impedance if properly programmed. Furthermore KA ensures stability to impedance synthesis loop. In the Receive direction (Rx), the Analog Front End (AFE) receives a 1-bit modulated composite signal, which represents part of the voltage to be forced into the line. It performs DAC and filtering 4 FUNCTIONAL DESCRIPTION The STLC3040 STLC3040 is implemented by a combination of analog and digital circuits, merging the best available analog and digital processing performances of the BiCMOS technology. In particular two main blocks of the STLC3040 STLC3040 can be identified: an analog front end interfacing the HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) and a programmable DSP. (See fig. 3) 4.1 - Signal processing. The line-current signal received in pin IT from the HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) is mirrored out of pin ACDC. On its way, its value is sensed to determine Off-Hook signalling. While in active conversation this istantaneous sensing is used for fast Hook signalling such as numbering. Then line-current AC and DC parts are splitted by RDC and CAC. The signal is processed to realize AC and DC impedance synthesis. Indeed IT pin carries the AC current due to voice signals present at line terminals and the DC current related to the specific V-I operating point. During Stand-By mode signal is created by the DC current after AC part has been removed. This filtered Hook produces robust signalling in Standby mode or pause-period during reduced-power Ring mode. As far as the DC characteristic is concerned, two Figure 3: Block Diagram. DIGITAL SIGNAL PROCESSOR A/u exp. GR + R ANALOG FRONT END Post Filter DSD LB1 LB3 Rx FSC DCL DU TTX RING TEST Echo Canc. B GCI INT. DD Tx LB1 LB2 A/u Comp. GX + VOUT Z + + X KD KA LB3 DEC ASD ANTIALIAS FILTER Ilim TTX Canc. DC Char Curr. buff. RDC IT RDC D95TL205D D95TL205D 4/49 ACDC CAC CAC RAC RAC STLC3040 STLC3040 Figure 4. IL VDROP = 9.6V + VdTTX .40 (see ILIM: 0-70mA 1.1mA step ILIM par 4.3.2.1) VDROP RFEED = 2 * RP + n * 100 VBAT VL VOL IL 100mA (typ) RING MODE RFEED = 2RP VL VBAT -22V IL ILIM STAND-BY MODE ILIM: 0-70mA 1.1mA step RFEED = 2 * RP + n * 100 VBAT -5.85V functions. This voltage is then combined with the AC and DC analog impedance signals, plus a TTX pulse, in a summing buffer that feeds the Vin pin of the HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170). The architecture of the digital section is based on Digital Signal Processor which synthetises 7 digital filters (B, Z, X, R, KD, GX, GR). KA uses the some register value as KD. In Table 1 you can find the number of coefficients and their bit width for each filter. Table 1: FILTER B R X GR GX KA, KD Z NUMBER OF COEFFICIENTS 8 4 4 1 1 1 3 COEFFICIENT WIDTH 14 BITS 14 BITS 14 BITS 8 BITS 8 BITS 8, 14 BITS (*) 14 BITS (*) KA is a subset of KD = most significant bits, (5-12) but sign bit, of KD register. Filter coefficients can be programmed by 14 bits D95TL208D D95TL208D VL deep registers. These internal filters can be enabled setting the most significant 5 bits of CR4 register and CR11 (1). PCM encoding and ITU-T high/lowpass-filtering are done by dedicated state machines. Setting the bit 0 of CR4 register A-law or µ-law can be selected. In order to match the complex line impedance, both amplitude and phase can be programmed using Filter Z. The two to four wires echo cancellation is implemented thanks to programmable echo canceler (B Filter) with Gain and Group-delay equalizer. Two programmable FIR filters X and R, can be set in order to guarantee the best overall line frequency response in the frequency domain, according to the local specifications. In this way the signal distorsion can be reduced with 14-bits resolution. Gain Setting, both in transmission and in receive, is done by two FIR filters (GX for transmission, GR for Receive). A coefficient optimization software let the users calculate GX and GR filters coefficients. In transmission the maximum achievable gain without distortion is 3dB. 5/49 STLC3040 STLC3040 In receive the maximum programmable gain is 0dB. Gain step resolution in both sides (Rx and Tx) depends on the value of the gains. See table below to gain/step accuracy. Table 3: PDO = 50µA pin 9 (C1) (*)Vhv (*)Vhv Table 2. Tx & Rx Gain Step accuracy Xmax - 6dB (1/128) 0.070dB Xmax - 12dB (1/64) RING OPEN CONV.NP BB.NP RING NP CONV.RP BB.RP RING RP 0.27dB Xmax - 24dB (1/16) 0.56dB Xmax - 30dB (1/8) 1.16dB Xmax - 36dB (1/4) 2.5dB Xmax - 42dB (1/2) 6.0dB Tx: Xmax = 3dB; Rx: Xmax = 0dB The Voice Signal Processing is shown in Block diagram in Fig.3. In the RX direction, after being decoded, the voice sample passes through a set of interpolator and correction filters. The signal is finally oversampled to a high-rate of 256kHz before being summed to the feed-back impedance synthesis signal. Analog circuits performs Off-Hook sense and allows On-Hook Signaling. The longitudinal line current provided by the HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) is sensed at pin IL; Ground Key signalling is activated when the absolute longitudinal current on IL pin exceeds threshold. A low pass filter and programmable persistance filter (register CR3) elaborates the detection. The Vbim pin receives from the HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) an information on the actual battery voltage (Vbim = Vbat/40), this voltage is then compared with the line voltage and one bit is set in the upstream data flow if Vline < (VOL/2). This allows the system to be tailored for different line requirements. Line and circuit-test functions are discussed in detail in the appendix. The HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) is driven by the STLC3040 STLC3040 through two ternary pins C1 and C2 (pin 9 & 10 of STLC3040 STLC3040) that define the operating state of the HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) (Table 3). C1 and C2 are set according to the content of the bytes received by STLC3040 STLC3040 at DD pin (pin 5) of the GCI Interface. C1 pin is internally tied to a current-sensing circuit. It senses an extra current that the HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) issues when in thermal overload conditions. 6/49 (*)Vlv TIP OPEN 0.14dB Xmax - 18dB (1/32) pin 10 (C2) (*)Vmv (*)Vlv (*)Vmv ST-BY PDO = 0µA pin 9 (C1) (*)Vhv (*)Vmv (*)Vhv Ext. Indication Ext. Indication pin (*)Vmv Ext. Indication 10 (C2) (*)Vlv Ext. Indication (*)Vlv Ext. Indication Ext. Indication Ext. Indication Ext. Indication Loop Open (HV Internal Resistors disconnect) (*) Vhv, Vmv, Vlv see digital interface electrical characteristics. Through PDO pin (pin 28) the STLC3040 STLC3040 forces the HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) in Power Denial if the current at this pin is 0. When the STLC3040 STLC3040 sinks 50µA the HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) will be turned on. In Power Denial, TIP and RING wires are disconnected from the HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) driver (Power Denial). Table 3 related to PDO = 0µA is valid only for STLC3170 STLC3170. VL1, VL2 pins sense, the Off-Hook when HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) is in power denial, allowing very low power consumption in On-Hook condition. Other important features, which usually require external circuitry, like Test Tones, Ringing, Metering Impulse Injection are programmable via software. Ring signals can be programmed both in Amplitude and Frequency via CR9 register. The Metering Pulse Injection Level can be set by the CR10 register. Ring-Trip detection is performed by a dedicated internal circuitry. 4.3 Slic Kit Operating Modes STLC3040/HV STLC3040/HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) kit can work in three main modes: - POWER DOWN - ACTIVE - RING Each mode is selected by Command-Indicate (C/I) and Monitor GCI channels. Line State changes are signalled through either upstream C/I or SR register. During the switching between any two modes the indication is frozen for 10msec in addition to the programmed persis- STLC3040 STLC3040 tance. All operating modes with related C/I command bits and CR register bits are shown in table 13 pag 45. 4.3.1 POWER DOWN In this condition SLIC Kit reduces strongly its power consumption allowing Off-Hook detection. Only the internal circuitry dedicated to the OffHook detection is switched on. C/I and CR1 register configuration (programmed by Monitor) defining Power Down Submodes are here below shown: Table 4: Power Down Submodes SLIC KIT MODE C/I (7) C/I (6) C/I (5) CR1 CR1 CR1 (7) (3) (2) EXTERNAL INDICATION 0 0 0 0 X X LOOP OPEN 0 0 1 X X X STAND BY 0 0 0 1 0 0 GROUND START 0 0 0 1 1 1 4.3.1.1 - External Indication When this mode is selected both STLC3040 STLC3040 and HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) are set in Power Denial. STLC3040 STLC3040 cuts the bias current, sunk by the HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) via the PDO pin. In this mode the HV (L3000N L3000N, L3000S L3000S) shows a high impedance on TIP and RING pins; theHV shows on TIP pin the RT impedance and on RING pin the RR impedance if it integrates the 2 external resistors RT and RR (STLC3170 STLC3170). This mode is used to get a low power consumption obtaining supervision only via the STLC3040 STLC3040 and a resistive sensing network. The total power consumption of the SLIC Kit in this mode is under to 50mW (being almost 0 the consumption from battery). 4.3.1.2 - Loop Open This mode can be selected only if the High Voltage integrates the two external resistors (RR, RT see fig. 5) of the feeding and sensing circuitry. This is implemented on the STLC3170 STLC3170 high voltage device. 4.3.1.3 - Stand-By SLIC behaves like a constant current source with typical 7mA feeding current. Open loop voltage is equal to (Vbat - 5.85V). COFISLIC power consumption is reduced to 150mW typical. Current limit and Off-Hook threshold are programmable by register CR7. Both off-hook and ground-key detectors are operating. 4.3.1.4 - Ground Start The SLIC is set in Stand-By with the TIP wire (the most positive wire) in high impedance. The current feeding is equal to Stand-By mode current feeding. Figure 5: Application Diagram. BGND AGND VCC RT VB+ VCC VIN TIP PDO IT RP RING Power SO20 RR SEL24 SEL24 DU/DD(2) IL C1 L3000S L3000S EXT IT IL MNT VEE AGND DGND VOUT REF RP VDD C1 C2 VBIM DCL FSC TSn(3) STLC3040 STLC3040 44PLCC 44PLCC C2 O1 I1 VBIM MR IDn(3) CDVB STRn/SIRn(7) DS VB- BGND VL2 CAP VL1 REF RAC RDC REF D95TL203B D95TL203B IOn(2) RAC RDC ACDC CAC CAC CAP V CC 7/49 STLC3040 STLC3040 4.3.2 - ACTIVE This operating mode is selected by the card processor after an Off-Hook detection in order to allow signal transmission on the line. Both Off-Hook and ground-key detectors are operating. GCI Command - Indicate channel and CR1 register configuration (programmed by GCI Monitor) defining Active modes are herebelow shown: Table 5: SLIC MODE C/I (7) C/I (6) C/I (5) CR1 (*)CR1 (*)CR1 (7) (3) (2) ACTIVE 0 1 0 X 1/0 1/0 ACTIVE + TTX 0 1 1 X 1/0 1/0 (*) This condition refers to STLC3040 STLC3040 only. If CR1.3 and CR1.2 are equal (either 0 or 1) both STLC3040 STLC3040 and HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) are in Active State. If CR1.3 and CR1.2 are different, one of two line wires will be set in high impedance, while the STLC3040 STLC3040 will still be in Active mode. Current Limit and Off-Hook threshold are programmable by CR6 register. If the fifth bit of the Command-Indicate channel is set to 1 the Teletax Signal is superimposed to the voice signal. 4.3.2.1 - DC feeding As far as DC characteristic is concerned, SLIC is basically working as a constant current device. It turns automatically into a resistive feeding when the programmed current limitation value cannot be held due to high line resistance. In active mode the constant current value is programmable in 1.1mA steps ranging from 0mA to 69.3mA. In resistive feeding region SLIC kit operates like a constant voltage source with a series impedance Rfeed = 2Rp+n 2 50 (being Rp the external protection resistor and n a value set from 1 to 8 via CR8 register). Voltage drop (Fig. 4) can be programmed in order to optimize voltage feeding characteristic, according to AC signal swing requested (ex: voice, voice + 2Vrms TTX, voice + 5Vrms TTX): VDROP = Vd3000 + 40 (VdAC + VdTTX) Vd3000 = drop due to internal HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) architecture (2.8V typ.) VdAC = AC headroom on Vout (170mV typ.) VdTTX = TTX headroom on Vout (from 0 to 465mV (15x31) typ. depending on programmed TTX level). At HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) two wires the following equation must be used: VDROP(TIP/RING) = 9.6V + CR10 [7.3] 15mV 40. 4.3.2.2 - Metering Generation TTX signal is internally generated, filtered and shaped. Shaping is carried out by a gradual increase of metering pulse level of a level step (see CR10 register) per signal half period (please see Fig. 6). TTX can be programmed both in frequency (12 or 16 KHz ) and open loop amplitude (from 0 to 10Vrms in 255 steps). The output impedance at TTX frequency is just 2 x Rp; therefore the proper value should consider the drops Figure 6: TTX Shaping VS VSS TIM D96TL265A D96TL265A VS 2 CR10 LSB VSS PROGRAMMED VOLTAGE AS PROG IN CR10 8/49 STLC3040 STLC3040 across the 2Rp. Filtering is performed inside the device without external circuitry. Feeding voltage polarity can be reversed in both soft and hard ways under software command. 4.3.2.3 - Boost Battery To supply very long lines (high loop resistance), the SLIC can be set in "Boost battery" mode. In this mode the line is fed with a total battery voltage equal to |Vb+| + |Vb-|, keeping the same current limiting values as in active mode. The Vb+ battery is the same positive supply voltage needed for ringing generation. 4.3.3 - RING In this mode COFISLIC provides ringing signal equivalent to a maximum 85Vrms ring line voltage. HV L3000N L3000N and L3000S L3000S handle a maximum 65Vrms balanced ring signal; HV STLC3170 STLC3170 handles a maximum 85Vrms. It is possible to reduce power consumption if Power Reduced Ring mode is chosen. The output impedance is represented only by the two Rp protection resistors and the current is limited to 100mA. C/I and CR1 register configuration (programmed by GCI monitor channel) define Ring conditions as herebelow shown: Table 6: SLIC MODE C/I (7) C/I (6) C/I (5) CR1 CR1(*) CR1(*) (7) (3) (2) RING 1 1 X X 1/0 1/0 Reduced Power Ring 1 0 X X 1/0 1/0 (*) CR1.3 has to be equal to CR1.2 : 0 or 1 If unbalanced ringing is requested, SLIC can support also external ringing injection configuration, providing both logic command for relay driver and ringing detection circuitry. 4.3.3.1 - Ring Generation When the ringing function is selected, a low level ringing signal (1.5Vrms typ.) is generated inside the STLC3040 STLC3040 and provided on the VOUT pin. This signal is then amplified and injected in balanced mode into the line through the HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170), with superimposed DC voltage of 24V typical. Both ringing frequency and amplitude are software programmable. The first and the last ring cycles are synchronized by the STLC3040 STLC3040 so that the ringing signal always starts and stops with zero phase. In Ring mode the Off Hook indication is asserted whenever during two consecutive ring periods ( or an equivalent time in pause) the mean value of the IT current exceedes the programmed threshold. After the persistance time the Off Hook is sent to C/I upstream. 4.3.3.2 - Power Reduced Ring The modes in Table 6 differ only during the ringpause phase. During the pause of reduced-power-ring mode the SLIC Kit is set in Stand-By. The pause state is forced by stop ring command (C/I.5 downstream = 0) or by the detection of OffHook. 4.3.3.3 - Unbalanced Ringing The device allows an unbalanced Ring application. This application requires an external ringing generator. A digital I/O pin can be used to drive the external relay driver. An external ring sync. signal synchronised on the Vring zero crossing, must be provided on pin 29 of STLC3040 STLC3040. The external ring frequency must be the same as the value programmed in the internal register. 4.4 - TESTING FEATURES STLC3040/HV STLC3040/HV (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) kit allows to perform up to 11 tests. They are aimed at covering the following issues. 1. Line and Battery Characteristics AC, DC Leakage. 2. SLIC Kit block testing. 3. Signal Path Behavior Every test is set by internal registers, which are written through GCI data down Monitor. Test results are typically digitalized, codified and dropped in the first PCM channel (byte B1) of GCI interface. For four go/nogo tests (Analog Loopback, Ring Generator, TTX Generator and TTX filter) the result of the test is also written in one bit of CR5 register that is readable through Monitor. Test functions are carried out with SLIC Kit in a mode set automatically by COFISLIC. For detailed explanationabout tests see chapter 6. 4.4.2 - Loop Backs LOOP1 and LOOP2 bits of CR4 register set up some internal loop backs. This feature is typically used for COFISLIC tests (see fig. 3). Any Loopback is enabled by CR1.5 bit. Loopback type is selected by register CR4. There are three types of loopback. Loopback 1 (CR4.2 = 0, CR4.1 = 1) simply copies the downstream B1 to the upstream B1 through the GCI interface. In this case no Rx signal is sent to the line. The kit operates as previously set. Loopback 2 (CR4.2 = 1, CR4.1 = 0) sets Kit SLIC in Active mode. It copies the output of DSD (Digital Sigma Delta converter) to the input of the DEC 9/49 STLC3040 STLC3040 block, as shown in fig. 3. Rx signal goes on to the line. Please note that this loopback function cuts off the Tx channel connection to the line. All other functionalitiesare those of Active mode. Loopback 3 (CR4.2 = 1, CR4.1 = 1) sets Kit SLIC in Active mode. Rx signal is prevented to go the line. Tx path is cut off from the line as well. Output of ASD is copied to input of AFE port filter. DSP part can be still exercised via B1. All the functionalities are those of active mode. 4.4.3 - Test Tones Generation In Active mode STL3040 STL3040 can generate either 1kHz or 800Hz frequencies towards the 2-wire line. The two tones can also be enabled at the same time. TON bit of CR1 register enables the 1 kHz test tone generator. 800Hz is enabled by CR5[3.0] = 4h. 800Hz amplitude is programmable through the same register (CR10) used to set TTX amplitude. 1kHz level is fixed at PCM full scale and can be modified changing Rx channel gain. 4.5 COFISLIC Reset Any reset to COFISLIC sets SLIC kit in External Indication. COFISLIC is set in Power denial. There are four different reset sources: Power-On Reset, Reset pin MR (pin 36), Reset bit (SOP command bit 4). During Reset, output pins are set as follows: DU (pin 6) High impedance C1 (pin 9) Vhv C2 (pin 10) Vhv PDO (pin 28) High impedance O1 ( pin 39) Low Level Additionally a Reset of the DSP part of the COFISLIC is triggered by CLK fail detection (see also page 17). 4.5.1.1 Power On Reset When voltage at VDD pin crosses over an internal fixed threshold (typ. 2.5V) COFISLIC is reset. 4.5.1.3 Reset bit RST (SOP command bit 4) If RST bit is programmed to 1 COFISLIC is reset. SOP register is set by GCI down stream channel. Until the end of the current command processing, the GCI is kept active. 4.5.1.4 - CLK fail Reset Clock fail triggers a reset routine of the DSP which lasts, until the first good frame that follows the failed ones. In active mode during the Reset routine, the voice channel of "Data up" (Du, pin 6) is forced IDLE dependent on the selected codification law. As far as "Data down" (DD, pin 5) is concerned, the voice channel does not reach the Vout during this phase. Z sinthesys is partially performed, the DSP branch is not active while the analog loop is kept active. Coefficients and CR registers' contents do not change because of this partial reset, GCI state as well. Metering pulse injection signaling is not affected too. Ring generation and ring trip detection are not influenced too. 4.5.2. Start-up State During reset the device is in Power- Denial Mode. After Reset, COFISLIC is automatically switched to its basic start-up state in which it uses internal default values for all filters and settings (AC and DC). Programmed coefficients of filters are not reset. Bit 0 of CR6 register, FIXC, is set to 1, this means that fixed values are used after a Reset until FIXC is set to 0. Even if FIXC = 1, both checksum and reading of filter coefficients are carried out on formerly programmed coefficient set. Table 7: Fixed Filter Coefficients Filter KA, KD Z 019C, 24A0, 1600 X 149A, 0521, 3F40,3EF2 R 1879, 39E0, 00B4,0006 GTX 4.5.1.2 Reset Pin MR If an high level is applied to pin 36 (MR) the COFISLIC is reset. MR pin has built-in filter to reduce spike sensitivity. Spikes smaller than 90ns are neglected. Therefore at MR pin a high level is surely recognised as a Reset if it is present for at least 2µs. 10/49 Coefficients (h) 0E00 GRX B FF 60 0, 0, 0, 0050, 0680, 06D0, 0, 3C80 SLIC is switched to operating mode carried by GCI Command Indicate at least two frames after reset. SLIC status and Filter configuration can be changed by SOP and COP commands. After reset the device is internally set as follows: - configuration registers are set to their default STLC3040 STLC3040 values (see Chapter 4-8 Configuration Register) - RST bit (SOP command bit 4) is set to 1 to indicate that a reset has occured - GCI interface is reset. After software Reset its former state is kept. On-going GCI communication is stopped - DU is in high impedance state - FIXC = 1 (CR6 Register) Fixed Coefficients are selected ­ DC characteristics of SLIC-Kit - External Indication - Normal Battery - Test Disabled - Persistence for Off-Hook and I1: 10ms - Persistence for Ground Key: 20ms - Ring Trip threshold = 4.2mA - Ilim = 22mA in active mode - Ilim = 7.7mA in Stand-By mode - Off-Hook detection threshold in active mode = 10mA - Off-Hook detection threshold in Stand-By mode = 7.7mA - Feeding Resistance in either Active or StandBy mode = 2 (50 + Rp) (fuse impedance value is not included) - Ring: Internal - Ring Frequency = 25Hz - Ring Voltage = 65Vrms - Line Voltage Drop = 28.2V - External Indication Voltage Threshold for OffHook detection = 9.0V - A-law is programmed AC characteristics of SLIC-Kit - Metering with Teletax - Line Impedance: (Synthetized Impedance + 2 Rp) = 700 + 2Rp - Balance Impedance: 910 / / 62nF - Tx Gain: 0dBr - Rx Gain: -7dBr - Teletax Voltage onto line VTTX = 10Vrms - Teletax Frequency = 16kHz - Battery Reversal: Hard Further after the reset - I/O pins are set as inputs - PD bit of CR1 is reset (means STLC3040 STLC3040 in Power-Denial mode). - All bits of Signalling Register are masked - Data Upstream C/I byte is reset to 0 Check Configuration-registers reset-value for more detailed information. 4.6 GCI Backplane Interface GCI is a standard serial interface for interconnection of SLIC kit to the line card backplane. The digital interface is used to transfer status information to and from the SLIC as well as to transfer filter coefficients for the DSP. With this approach an analog Line Card could be replaced by an ISDN one and viceversa without need to change the interface to the linecard controller. As far as physical level is concerned this standard consists of four wires: - Serial Transmitted data to the backplane: DU - Serial Received data from the backplane: DD - 8KHz Frame Synchronization: FSC - Master Data Clock (2048KHzor 4096KHz): DCL The frame is divided into eight time-slots which contains four bytes each. Bit rate in both directions is 2048Kbit/sec and it's not affected by clock frequency. This can be chosen setting SEL24 SEL24 pin. Eight GCI time slots are selectable via three pins TS2-TS0 (see Table 8). For every time slot the first bit, received or transmitted, is the Most Significant one, according to timing diagram shown in fig. 7. Information is clocked out on the rising edge of data clock and it is latched in on the falling edge of DCL signal. Frame Synchronization FSC is a 8KHz signal and its rising edge gives the time reference of the first bit in the first GCI (input or output) channel and resets the slot counter at the next falling edge of the clock every frame. Four bytes of any GCI time slot are: - B1 channel for PCM data, - B2 channel not used, - M (Monitor) channel used to write and monitor COFISLIC internal registers, - C/I (Command/Indication) channel used to set the Operating Mode. 8bits 8bits 8bits 6bits B1 B2 MONITOR C/I Byte 1 Byte 2 Byte 3 1bit 1bit A E Byte 4 A single GCI channel has 256kbit/s data rate. Exchange Protocol STLC3040 STLC3040 validates a received byte if it is detected identicaltwo consecutivetimes. (see figg. and7and 8) The exchange protocol is identical for both directions. The sender uses the E bit to indicate that it is sending a Monitor byte while the receiver uses A bit to acknowledge the received byte. When no 11/49 STLC3040 STLC3040 Table 8: GCI Time Slot assignment. SEL24 SEL24 TS2 TS1 TS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 GCI operating mode 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 time slot 0:DCL time slot 1:DCL time slot 2:DCL time slot 3:DCL time slot 4:DCL time slot 5:DCL time slot 6:DCL time slot 7:DCL time slot 0:DCL time slot 1:DCL time slot 2:DCL time slot 3:DCL time slot 4:DCL time slot 5:DCL time slot 6:DCL time slot 7:DCL = 2048kHz = 2048kHz = 2048kHz = 2048kHz = 2048kHz = 2048kHz = 2048kHz = 2048kHz = 4096kHz = 4096kHz = 4096kHz = 4096kHz = 4096kHz = 4096kHz = 4096kHz = 4096kHz Figure 7. GCI Interface Timing (DCL = 2048KHz, SEL24 SEL24 = 0) 125µs FSC DCL 2048KHz DD TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 DU TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 Detail C Detail C FSC DCL DD/DU Bit 0 Bit n Bitn - 1 D95TL210A D95TL210A 12/49 STLC3040 STLC3040 Figure 7. (continued) GCI Interface Timing for 8 voice channels (per 8 KHz frame) 125µs FSC DCL 4096KHz DD TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 DU TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 Detail A Detail A DD Voice Channel don't care Monitor Channel C/I Channel A E DU Voice Channel High Impedance Monitor Channel C/I Channel A E GCI Interface Timing (DCL = 4096KHz, SEL24 SEL24 = 1, per 8 KHz frame) 125µs FSC DCL 4096KHz DD TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 DU TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 Detail B Detail B FSC DCL DD/DU Bit 0 Bit n Bit n-1 D95TL209A D95TL209A 13/49 STLC3040 STLC3040 message is transferred, E bit and A bit are forced to inactive state (high = 5V). A transmission is started by the sender (Transmit section of the Monitor channel protocol handler) by putting the E bit from inactive to active state (low = 0V) and by sending the first byte on Monitor channel in the same frame. Transmission of a message is allowed only if A bit, sent from the receiver, has been set inactive for at least one consecutive frame. When the receiver is ready, it validates the incoming byte when received identical in two consecutive frames. Then, the receiver sets A bit from the inactive to the active state (preacknowledgement) and maintain active at least in the following frame (acknowledgement). If validation is not possible (two last bytes received are not identical) the receiver aborts the message by setting the A bit active for only a single frame.The second byte can be transmitted by the sender putting the E bit from the active to the inactive state and sending the second byte on the Monitor channel in the same frame . The E bit is set inactive for only one frame. If it remains inactive more than one frame, it means an end of message. The second byte may be transmitted only after receiving of the pre-acknowledgement of the previous byte . Each byte has to be transmitted at least in two consecutive frames. The receiver validates the current received byte as for the first one and then set the A bit in the next two frames first from the active state to the inactive state (pre-acknowledgement) and back to the active (acknowledgement). If the receiver cannot validate the received current byte (two bytes received not identical)it pre-acknowledges normally but lets the A bit in the inactive state in the next frame which indicates an abort request . If a message sent by the COFISLIC is aborted, the COFISLIC will send again the complete message until receiving of an acknowledgement . A message received by the COFISLIC can be acknowledged or aborted with flow Control. The most significant bit (MSB) of Monitor byte is sent first on the Monitor channel. E & A bits are active low and inactive state on DU is 5 V. When no byte is transmitted, Monitor channel time slot on DU is in the high impedance state. The GCI interface transmitter will abort after 8 times during which it hasn't succesfully received any acknowledge from the device upstream. The GCI interface receiver will go in abort request mode after 8 times of unsuccessful attempts to get 2 identical copies of the data. This means that after 8 frames of unsuccessful handshake, the GCI interface transmitter will abort while the receiver will make a request for abort. 4.6.1 B1/B2 Channels 4.6.1.1 PCM codifications GCI interface extracts receiving PCM data from 14/49 the B1 channel on DD pin and outputs PCM bytes on DU pin. 4.6.1.2 Linear codification STLC3040 STLC3040 allows Linear codification simply setting two bits of CR12 register. COMTX (bit 0) enables the linear code in transmission, while COMRX (bit 1) enables the linear code in receive. STLC3040 STLC3040's linear code consists of 16 bits which means a range from (-215) to (215-1) Linear Code is housed in B1 and B2 channels, B1 is the least significant byte end B2 is the most significant byte. 15 bits are dedicated to the module while the most significant bit is the sign bit. If bit 15 (sign bit) = 0 bit 14.bit 0 represent the module. If bit 15 = 1 module is got by 2-complementing bit 14 . bit 0. 4.6.2 C/I Channel Command/Indicate byte is a 6 bits wide command full duplex transmission. Internal C/I registers will be loaded if downstream command is stable for two frames. Also upstream Command/Indicate byte lasts for at least two consecutive 8KHz frames. Command/Indicate is mainly used to set SLIC operating mode and to monitor subscriber On/Off-Hook and Ground-Key detection. Any change of line conditions like On-Off/Hook and Ground Key is signalled via upstream C/I. HOOK and GNDK bits always reflect line conditions even if corresponding bits of Signalling Register are masked by CR12 register. Bit 5 of upstream Command/Indicate says that at least one of Signalling Register six most significant bits has changed its logical value. Bit 5 of upstream Command/Indicate does not change if related bits of Signalling Register have been masked by CR12 register. Input/Output pins (IO1/2,I1,O1) can be set and monitored by C/I channel too. Note that there is no address in both directions because there is one GCI time slot per each COFISLIC. C/I channel in Downstream direction consists of six bits as shown below : BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 RING CONV TIM IO1 IO2 O1 Basically the first 3 Most significant Bits of C/I downstrean operate as follows. For a complete description please refer to Table 13. STLC3040 STLC3040 Figure 8: GCI Monitor Channel messaging examples. M X M1 M1 M2 M2 X X X E A 1st byte 2nd byte (M1) (M2) pr e-ack (M1) Ready for a message 3rd byte? ? EOM (X) pre- ack pre-ac k? (M2) ack (M1) ack (M2) (X) Ready for a new message TWO BYTES MESSAGE - NORMAL TRANSMISSION X M1 M1 M2 M2 X X X X M1 M1 M2 M E A 1st byte (M1) Rea dy for a message 2nd byte (M2) pre- ack (M1) ack (M1) 3r d byte ? (X) pre- ack (M2) abort (M2) EOM (or abo rt ack) Rea dy for ret ransmission 1st byte (M1) pre- ack (M1) TWO BYTES MESSAGE ABORTED ON THE SECOND AND RETRANSMITTED M1 = start Byte E & A BITS TIMING RING = Sets COFISLIC into ringing state. = 0 COFISLIC is not in ringing state. = 1 COFISLIC is in ringing state. CONV = Sets COFISLIC into power up state. = 0 COFISLIC is in a power down state. = 1 COFISLIC in power up state. TIM = Timing bit to control the timing of ringing and meterpulses. = 0 COFISLIC is in ringing pause or no meterpulse is on. = 1 COFISLIC is in ringing or output of a meterpulse is running. IO1, IO2 define the value for the programmable Input/Output pins (7, 8) if programmed as output pins by CR2 register. IO1 = 0 The related pin 7 at the digital interface of the COFISLIC is set to a logic 0 = 1 The related pin 7 at the digital interface of the COFISLIC is set to a logic 1 IO2 = 0 The related pin 8 at the digital interface of the COFISLIC is set to a logic 0 = 1 The related pin 8 at the digital interface of the COFISLIC is set to a logic 1 O1 sets value for fixed output pin 39 15/49 STLC3040 STLC3040 = 0 The related pin 39 at the digital interface of the COFISLIC is set to a logic 0 = 1 The related pin 39 at the digital interface of the COFISLIC is set to a logic 1 C/I channel in Upstream direction is herebelow described: channel transfers: SOP, COP, TOP. BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 X R/W X X B3 B2 X X R/W =0 Write Operation =1 Read Operation B3 BIT6 BIT5 BIT4 BIT3 BIT2 HOOK GNDK SLCX IO1 IO2 I1 HOOK indicates loop condition: = 0 Subscriber is On-Hook = 1 Subscriber is Off-Hook GNDK indicates Ground Key detection: = 0 No Detected Longitudinal Current = 1 Detected Longitudinal Current SLCX is the summary output of the signalling register (See TOP command) = 0 No unmasked bit in signalling register has toggled = 1 An unmasked bit in signalling register, has toggled, it is reset only if SR register is read. IO1,IO2 give logical state of programmable Input/Output pins (7, 8) IO1 = 0 Corresponding pin 7 at digital interface of COFISLIC is receiving a logic 0 = 1 Corresponding pin 7 at digital interface of COFISLIC is receiving a logic 1 IO2 = 0 Corresponding pin 8 at digital interface of the COFISLIC is receiving a logic 0 = 1 Corresponding pin 8 at digital interface of COFISLIC is receiving a logic 1 If as per CR1 register IO1 and IO2 are programmed as outputs, data up command indicate, IO1 and IO2 are set to 1 I1 gives logical state of fixed input pin 38. = 0 pin 38 is receiving a logic 0. = 1 pin 38 is receiving a logic 1. 4.7.1 Monitor-Channel (M-channel) As already mentioned COFISLIC can be programmed and monitored via GCI Monitor. Data transfer from and to STLC3040 STLC3040 starts with a specific byte, called Start Byte: BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 1 0 0 0 0 0 0 X In downstream a second byte selects one of the three different kinds of commands which Monitor 16/49 B2 0 1 SOP command 1 1 TOP command X BIT7 0 COP command For SOP, COP, TOP commands the Start Byte is 81 in DU directions. SOP commands set and monitor COFISLIC status. TOP commands read Signalling register and coefficient checksum. COP commands set and read filters coefficient. SOP and COP can be either write or read commands, while TOP is used only for reading. A write command (SOP and COP) can be followed by up to 14 bytes. An answer to SOP, COP, TOP commands consists of maximum 16 bytes. First byte is always the start byte (81h). Registers from CR1 to CR12 are accessed by SOP command both in reading and writing. TOP command is used to read the Signalling Register and the Coefficient Checksum. The RAM, where filters coefficient are stored, is accessed by COP commands. A fourth command of the Monitor Channel is the so called Channel Identification Command (CIC). This command will be run if the COFISLIC receives the following code on the Monitor Channel for at least two frames: BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 1 0 0 0 0 0 0 0 Upon CIC command is received COFISLIC will place two bytes on DU line, each byte is repeated at least twice. BIT7 BIT6 BIT5 BIT4 1 0 0 0 BIT3 BIT2 BIT1 BIT0 CONF(3) CONF(2) CONF(1) CONF(0) This byte replaces usual Start byte. Low nibble CONF(3)-CONF(0) defines the identification code according to the logic values of three input pins IDH (pin 35), IDL and IDM (pin 31 and 32). Herebelow it is the Table of Identification: STLC3040 STLC3040 Table 9: SIGNALLING REGISTER (SR) SR provides information about loop condition: Off/OnHook condition, line constant current, line voltage. It also signals temperature alarm related to HV SLIC (L3000N L3000N, L3000S L3000S, STLC3170 STLC3170) and clock fails (see page 10). The Clock fail indication is set whenever the number of DCL periods in one frame (between two-FSC pulses) is different from the standard one. Hook and Ground Key state variations toggle the related bits of SR register and therefore switch HOOK and GNDK bits of upstream C/I. Every change of any of the six most significative bits of SR register is summarized in SLCX bit (bit 5) of upstream Command/Indicate, provided that these bits are not masked by CR12 register. Masking acts only on SLCX bit. IDH IDM IDL Id. Code +5V -5V -5V 0 +5V -5V 0V 1 +5V -5V +5V 2 +5V 0V -5V 3 +5V 0V 0V 4 +5V 0V +5V 5 +5V +5V -5V 6 +5V +5V 0V 7 0V +5V 0V 8 0V +5V -5V 9 0V 0V +5V A 0V 0V 0V B 0V 0V -5V C BIT7 BIT6 BIT5 BIT4 BIT3 0V -5V +5V D HOOK GNDK VB_2 0V -5V 0V E -5V -5V BIT1 BIT0 Reset Value: 00h 0V BIT2 F Data transfer is completed by the next byte: BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 1 0 0 0 1 0 0 ILIM TEMP CK_FAIL XX XX HOOK indicates loop condition (same as in upstream C/I): = 0 Subscriber is On-Hook = 1 Subscriber is Off-Hook 0 4.7.1.1 TOP Command As above mentioned TOP command allows reading Signalling Register and Coefficient RAM checksum. BIT7 X BIT6 BIT5 R/W X BIT4 BIT3 BIT2 X 1 1 BIT1 BIT0 LSEL1 LSEL0 R/W = 0 No Operation = 1 Read Operation LSEL1 LSEL0 0 0 1 byte for signalling register reading 0 1 1 byte for signalling register and 2 bytes for filter coefficients checksum reading, low byte is read first and then high byte. 1 0 GNDK shows a Ground Key detection (same as in upstream C/I): = 0 No Detected Longitudinal Current = 1 Detected Longitudinal Current VB_2half battery voltage across the line is detected VOL (VLINE compared to ). 2 This bit is designed to indicate the line DC operating point only in Stand-By and Active modes, with no TTX injection VOL |) 2 VOL |) = 1 if (|VLINE|>| 2 = 0 if (|VLINE|