STDM110 AO21DH/AO21/AO21D2/AO21D2B/AO21D4 - Datasheet Archive

 

0.25µm 2.5V CMOS Standard Cell Library for Pure Logic/MDL Products STDM110 0.25µm 2.5V CMOS Standard Cell Library for

 

STDM110 STDM110 0.25µm 2.5V CMOS Standard Cell Library for Pure Logic/MDL Products STDM110 STDM110 0.25µm 2.5V CMOS Standard Cell Library for Pure Logic/MDL Products Data Book 1999 Samsung Electronics Co., Ltd. All rights reserved. No part of this document may be reproduced, in any form or by any means, without the prior written consent of the publisher. Samsung assumes no responsibility for any errors resulting from the use of the information contained herein, nor does it convey any license under the patent rights of Samsung or others. Samsung reserves the right to make changes in its products or product specification to improve function or design at any time, without notice. SEC and STDM110 STDM110 are trademarks of Samsung Electronics Co., Ltd. Verilog is a registered trademark of Cadence Design Systems, Inc. Viewlogic is a registered trademark of Viewlogic Systems, Inc. Mentor is a registered trademark or Mentor Graphics Co. Synopsys is a registered trademark of Synopsys, Inc. Head Office Marketing Team Samsung Electronics Co., Ltd System LSI Business, ASIC Division, ASIC Design Service Team San #24, Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyunggi-Do, Korea Samsung Electronics Co., Ltd System LSI Business, ASIC Division, ASIC Marketing Team 15th Fl., Severance Bldg. 84-11, 5-Ka, Namdaemoon-Ro, Chung-Ku, Seoul, Korea TEL 82-2-760-6500, 6501 (Hot Line) FAX 82-331-209-4920 http://www.intl.samsungsemi.com Printed in the Republic of Korea TEL FAX 82-2-259-4988 82-2-259-2494 Introduction This databook contains information about STDM110 STDM110 0.25µm 2.5V standard cell library for pure Logic/MDL products developed by SEC (Samsung Electronics Corporation). The "library" basically contains various kinds of internal and I/O cells and soft-macros which are used for developing ASIC (Application Specific Integrated Circuit). It also includes a design kit helping designers to work in a workstation platform, and all sorts of design environments needed for an automatic chip design. There are six chapters in this databook: Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Introduction Electrical Characteristics Internal Macrocells Input/Output Cells Compiled Macrocells PLL In this databook each cell is followed by its AC electrical characteristics, and these characteristic values are almost equal when the corresponding cell is operated in a real chip. The purpose of this databook is to prevent any misuse or misapplication of STDM110 STDM110 cell library by providing precise information about the cell list, electrical data, directions for use, and matters demanding special attention. If you want to get more information about DRAMs, Digital cores and Analog cores that are not included in this databook, access the Samsung ASIC web site(http://www.intl.samsungsemi.com) or contact Head Office. Samsung ASIC iii STDM110 STDM110 Contents 1 Introduction 1.1 Library Description .1-1 1.2 Features .1-2 1.3 EDA Support .1-4 1.4 Product Family .1-4 1.4.1 Analog Core Cell.1-4 1.4.2 Internal Macrocells.1-12 1.4.3 Compiled Macrocells.1-12 1.4.4 Input/Output Cells .1-14 1.5 Timings.1-16 1.6 Delay Model .1-22 1.7 Testability Design Methodology.1-24 1.8 Maximum Fanouts .1-27 1.9 Packages Capability by Lead Count .1-34 1.10 Power Dissipation.1-36 1.11 VDD/VSS Rules and Guidelines.1-39 1.12 Crystal Oscillator Considerations .1-45 2 Electrical Characteristics DC Electrical Characteristics.2-1 3 Internal Macrocells Overview .3-1 Summary Tables .3-2 Logic Cells AD2DH/AD2/AD2D2/AD2D4 .3-17 AD3DH/AD3/AD3D2/AD3D4 .3-19 AD4DH/AD4/AD4D2/AD4D4 .3-21 AD5/AD5D2/AD5D4 .3-24 ND2DH/ND2/ND2D2/ND2D4 .3-27 ND3DH/ND3/ND3D2/ND3D4 .3-29 ND4DH/ND4/ND4D2/ND4D2B/ND4D4 .3-32 ND5/ND5D2/ND5D4.3-35 ND6/ND6D2/ND6D4.3-38 Samsung ASIC iv STDM110 STDM110 Contents ND8/ND8D2/ND8D4.3-42 NR2DH/NR2/NR2D2/NR2D2B/NR2D4/NR2A .3-46 NR3DH/NR3/NR3D2/NR3D2B/NR3D4/NR3A .3-49 NR4DH/NR4/NR4D2/NR4D2B/NR4D4 .3-53 NR5/NR5D2/NR5D4.3-56 NR6/NR6D2/NR6D4.3-60 NR8/NR8D2/NR8D4.3-64 OR2DH/OR2/OR2D2/OR2D4 .3-68 OR3DH/OR3/OR3D3/OR3D4 .3-70 OR4DH/OR4/OR4D2/OR4D4 .3-73 OR5/OR5D2/OR5D4 .3-76 XN2/XN2D2/XN2D4 .3-80 XN3/XN3D2/XN3D4 .3-82 XO2/XO2D2/XO2D4 .3-84 XO3/XO3D2/XO3D4 .3-86 AO21DH/AO21/AO21D2/AO21D2B/AO21D4 AO21DH/AO21/AO21D2/AO21D2B/AO21D4 .3-88 AO211DH/AO211/AO211D2/AO211D2B/AO211D4 AO211DH/AO211/AO211D2/AO211D2B/AO211D4 .3-91 AO2M110/AO2M110D2 AO2M110/AO2M110D2.3-94 AO22DH/AO22/AO22D2/AO22D2B/AO22D4 AO22DH/AO22/AO22D2/AO22D2B/AO22D4 .3-97 AO22DHA/AO22A/AO22D2A/AO22D4A AO22DHA/AO22A/AO22D2A/AO22D4A .3-100 AO221/AO221D2/AO221D4 AO221/AO221D2/AO221D4.3-103 AO222/AO222D2/AO222D2B/AO222D4 AO222/AO222D2/AO222D2B/AO222D4.3-107 AO222A/AO222D2A/AO222D4A AO222A/AO222D2A/AO222D4A.3-112 AO2222/AO2222D2/AO2222D4 AO2222/AO2222D2/AO2222D4.3-114 AO31DH/AO31/AO31D2/AO31D4 AO31DH/AO31/AO31D2/AO31D4.3-118 AO311/AO311D2/AO311D4 AO311/AO311D2/AO311D4.3-121 AO3M110/AO3M110D2 AO3M110/AO3M110D2.3-125 AO32/AO32D2/AO32D4 AO32/AO32D2/AO32D4.3-128 AO321/AO321D2/AO321D4 AO321/AO321D2/AO321D4.3-132 AO322/AO322D2/AO322D4 AO322/AO322D2/AO322D4.3-136 AO33/AO33D2/AO33D4 AO33/AO33D2/AO33D4.3-140 AO331/AO331D2/AO331D4 AO331/AO331D2/AO331D4.3-144 AO332/AO332D2/AO332D4 AO332/AO332D2/AO332D4.3-148 AO4M110/AO4M110D2 AO4M110/AO4M110D2.3-152 OA21DH/OA21/OA21D2/OA21D2B/OA21D4 OA21DH/OA21/OA21D2/OA21D2B/OA21D4 .3-155 OA211DH/OA211/OA211D2/OA211D2B/OA211D4 OA211DH/OA211/OA211D2/OA211D2B/OA211D4 .3-158 OA2M110/OA2M110D2 OA2M110/OA2M110D2 .3-161 OA22DH/OA22/OA22D2/OA22D2B/OA22D4 OA22DH/OA22/OA22D2/OA22D2B/OA22D4 .3-164 OA22DHA/OA22AOA22D2A/OA22D4A OA22DHA/OA22AOA22D2A/OA22D4A .3-167 OA221/OA221D2/OA221D4 OA221/OA221D2/OA221D4.3-170 OA222/OA222D2/OA222D2B/OA222D4 OA222/OA222D2/OA222D2B/OA222D4.3-174 OA2222/OA2222D2/OA2222D4 OA2222/OA2222D2/OA2222D4.3-179 OA31/OA31D2/OA31D4 OA31/OA31D2/OA31D4.3-183 Samsung ASIC v STDM110 STDM110 Contents OA311/OA311D2/OA311D4 OA311/OA311D2/OA311D4.3-186 OA3M110/OA3M110D2 OA3M110/OA3M110D2 .3-190 OA32/OA32D2/OA32D4 OA32/OA32D2/OA32D4.3-193 OA321/OA321D2/OA321D OA321/OA321D2/OA321D.3-197 OA322/OA322D2/OA322D4 OA322/OA322D2/OA322D4.3-201 OA33/OA33D2/OA33D4 OA33/OA33D2/OA33D4.3-205 OA331/OA331D2/OA331D4 OA331/OA331D2/OA331D4.3-209 OA332/OA332D2/OA332D4 OA332/OA332D2/OA332D4.3-213 OA4M110/OA4M110D2 OA4M110/OA4M110D2 .3-217 SCG1/SCG1D2 .3-220 SCG2//SCG2D2 .3-223 SCG3/SCG3D2 .3-225 SCG4/SCG4D2 .3-228 SCG5/SCG5D2 .3-231 SCG6/SCG6D2 .3-234 SCG7/SCG7D2 .3-236 SCG8/SCG8D2 .3-239 SCG9/SCG9D2 .3-241 SCG10/SCG10D2 SCG10/SCG10D2 .3-243 SCG11/SCG11D2 SCG11/SCG11D2 .3-245 SCG12/SCG12D2 SCG12/SCG12D2 .3-248 SCG13/SCG13D2 SCG13/SCG13D2 .3-250 SCG14/SCG14D2 SCG14/SCG14D2 .3-252 SCG15/SCG15D2 SCG15/SCG15D2 .3-254 SCG16/SCG16D2 SCG16/SCG16D2 .3-256 SCG17/SCG17D2 SCG17/SCG17D2 .3-258 SCG18/SCG18D2 SCG18/SCG18D2 .3-160 SCG19/SCG19D2 SCG19/SCG19D2 .3-263 SCG20/SCG20D2 SCG20/SCG20D2 .3-265 SCG21/SCG21D2 SCG21/SCG21D2 .3-267 SCG22/SCG22D2 SCG22/SCG22D2 .3-269 DL1D2/DL1D4 .3-271 DL2D2/DL2D4 .3-272 DL3D2/DL3D4 .3-273 DL4D2/DL4D4 .3-274 DL5D2/DL5D4 .3-275 DL10D2/DL10D4 DL10D2/DL10D4 .3-276 IVDH/IV/IVD2/IVD3/IVD4/IVD6/IVD8/IVD16 IVDH/IV/IVD2/IVD3/IVD4/IVD6/IVD8/IVD16 .3-277 IVCD(11/13)/IVCD(22/26)/IVCD44 /IVCD44.3-280 IVT/IVTD2/IVTD4/IVTD8/IVTD16 IVT/IVTD2/IVTD4/IVTD8/IVTD16 .3-282 IVTN/IVTND2/IVTND4/IVTND8/IVTND16 IVTN/IVTND2/IVTND4/IVTND8/IVTND16 .3-284 NIDH/NID/NID2/NID3/NID4/NID6/NID8/NID16 NIDH/NID/NID2/NID3/NID4/NID6/NID8/NID16 .3-286 OAK_NID10P/OAK NID10P/OAK_NID 20P .3-289 STDM110 STDM110 vi Samsung ASIC Contents NIT/NITD2/NITD4/NITD8/NITD16 NIT/NITD2/NITD4/NITD8/NITD16 .3-290 OAK_DUCLK10/OAK DUCLK10/OAK_DUCLK16 DUCLK16.3-296 CTSB/CTSBD2/CTSBD3/CTSBD4/CTSBD6/ CTSBD8/CTSBD16 CTSBD8/CTSBD16 .3-298 Flip-Flops FD1/FD1D2 .3-304 FD1CS/FD1CSD2 .3-306 FD1S/FD1SD2 .3-308 FD1SQ/FD1SQD2.3-310 FD1Q/FD1QD2.3-312 FD2/FD2D2 .3-314 FD2CS/FD2CSD2 .3-316 FD2S/FD2SD2 .3-320 FD2SQ/FD2SQD2.3-322 FD2Q/FD2QD2.3-324 FD3/FD3D2 .3-326 FD3CS/FD3CSD2 .3-328 FD3S/FD3SD2 .3-332 FD3SQ/FD3SQD2.3-334 FD3Q/FD3QD2.3-336 FD4/FD4D2 .3-338 FD4CS/FD4CSD2 .3-341 FD4S/FD4SD2 .3-345 FD4SQ/FD4SQD2.3-349 FD4Q/FD4QD2.3-352 FD5/FD5D2 .3-354 FD5S/FD5SD2 .3-356 FD6/FD6D2 .3-358 FD6S/FD6SD2 .3-360 FD7/FD7D2 .3-362 FD7S/FD7SD2 .3-364 FD8/FD8D2 .3-366 FD8S/FD8SD2 .3-369 FDS2/FDS2D2 .3-373 FDS2CS/FDS2CSD2 .3-375 FDS2S/FDS2SD2.3-377 FDS3/FDS3D2 .3-379 FDS3CS/FDS3CSD2 .3-381 FDS3S/FDS3SD2.3-383 FJ1/FJ1D2.3-385 FJ1S/FJ1SD2 .3-387 FJ2/FJ2D2.3-389 FJ2S/FJ2SD2 .3-391 Samsung ASIC vii STDM110 STDM110 Contents FJ4/FJ4D2.3-393 FJ4S/FJ4SD2 .3-396 FT2/FT2D2 .3-399 Latches LD1/LD1D2 .3-402 LD1A/LD1D2A.3-404 LD1Q/LD1QD2 .3-406 LD2/LD2D2 .3-408 LD2Q/LD2QD2 .3-411 LD3/LD3D2 .3-413 LD4/LD4D2 .3-416 LD5/LD5D2 .3-419 LD5Q/LD5QD2 .3-421 LD6/LD6D2 .3-423 LD6Q/LD6QD2 .3-426 LD7/LD7D2 .3-428 LD8/LD8D2 .3-431 LS0/LS0D2 .3-434 LS1/LS1D2 .3-436 Bus Holder BUSHOLDER .3-437 Internal Clock Drivers CK(2/4/6/8) .3-438 Decoders DC4 .3-441 DC4I .3-443 DC8I .3-445 Adders FADH/FA/FAD2.3-450 HADH/HA/HAD2 .3-453 SCG23/SCG23D2 SCG23/SCG23D2 .3-456 Multiplexers MX2DH/MX2/MX2D2/MX2D4 .3-460 MX2X4 .3-463 MX2IDH/MX2I/MX2ID2/MX2ID4 .3-466 MX2IDHA/MX2IA/MX2ID2A/MX2ID4A.3-469 MX2IX4 .3-472 MX3I/MX3ID2/MX3ID4 .3-475 MX4/MX4D2/MX4D4 .3-479 STDM110 STDM110 viii Samsung ASIC Contents MX8/MX8D2/MX8D4 .3-483 4 Input/Output Cells Overview .4-1 Summary Tables .4-2 Input Buffers PvIC/PvICD/PvICU.4-8 PvIS/PvISD/PvISU .4-12 PvIT/PvITD/PvITU .4-16 Output Buffers PvOByz .4-20 PvODyz .4-29 PvOTyz .4-41 Bi-Directional Buffers PvBaDyz/PvBaUDyz .4-59 PvBaTyz/PvBaDTyz/PvBaUTyz .4-59 Oscillators PHSOSC(K1/K2/M1/M2) .4-61 PH2SOSC(K1/K2/M1/M2) .4-66 PSOSC(K1/K2/M1/M2).4-71 PCI Buffers PTIPCI.4-78 PTOPCI .4-79 PTBPCI .4-80 USB I/O Buffers PBUSB/PBUSB1 .4-83 PBUSBLS.4-84 PBUSB_FS.4-85 Power Pads VDD2(I/P/O/IP/OP/T)/VDD3(P/O/OP) .4-92 VSS2(I/P/O/IP/OP/T)/VSS3(P/O/OP).4-92 Analog Interface VDD2I_ABB/VDD2OP_ABB/VDD2T_ABB.4-92 VSS2I_ABB/VSS2OP_ABB/VSS2T_ABB.4-92 VBB_ABB/VSSBB_ABB.4-92 PIC_ABB .4-94 Samsung ASIC ix STDM110 STDM110 Contents PICC_ABB .4-95 PICEN_ABB .4-96 POT1/2/4/8/_ABB.4-97 ESD Slot Cells EV1I/EV2P/EV2O/EV2OP/EV3P/EV3O/EV3OP .4-100 EV1I_ABB/EV2OP_ABB .4-100 Common Slot Cells .4-101 5 Compiled Macrocells Overview .5-1 Compiled Memory Naming Convention.5-1 Characteristics for Timing and Power.5-2 Built-In Self Test and Built-In Redundancy-Analysis .5-4 Compiled Memory Selection Guide.5-5 Low-Power Compiled Memory SPSRAM_LP .5-7 DPSRAM_LP .5-17 SPARAM_LP .5-27 DROM .5-37 MROM .5-45 Overview to Compiled Datapath Overview to Compiled Datapath.5-53 Compiled Macrocell Selection Guide .5-54 ADDER.5-55 BS .5-66 MPY .5-78 6 PLL PLL2013X PLL2013X .6-1 STDM110 STDM110 x Samsung ASIC NOTE Introduction 1 Table of Contents 1.1 Library Description . 1-1 1.2 Features . 1-2 1.3 EDA Support . 1-4 1.4 Product Family. 1-4 1.4.1 Analog Core Cells . 1-4 1.4.2 Internal Macrocells. 1-12 1.4.3 Compiled Macrocells. 1-12 1.4.4 Input/Output Cells . 1-14 1.5 Timings. 1-16 1.6 Delay Model. 1-22 1.7 Testability Design Methodology. 1-24 1.8 Maximum Fanouts . 1-27 1.9 Packages Capability by Lead Count. 1-34 1.10 Power Dissipation . 1-37 1.11 VDD/VSS Rules and Guidelines . 1-40 1.12 Crystal Oscillator Considerations . 1-46 Introduction 1.1 Library Description 1.1 Library Description Samsung ASIC offers STDM110 STDM110 as 0.25um CMOS standard cell library. Samsung's 0.25um cell-based logic process providing up to 5 layers of interconnect metal with various I/O pad-pitch options such as 70um pitch pad and 80um pitch pad. STDM110 STDM110 which reduced power dissipation and system cost by merging the logic and IPs as a whole and connecting internally from logic to memory data bus is ideal for high-performance products such as graphics controller, projector, portable CD and so on. STDM110 STDM110 can support up to eight million gate counts of logic providing 75% of usable gate. Logic density is 2.1 times greater than that of MDL90 MDL90. The power consumption of compiled memory is 90% smaller than MDL90 MDL90. STDM110 STDM110 also supports fully user-configurable compiled memory and datapath elements. Each element is provided as a compiler. Two different types of compiled memories in STDM110 STDM110 are available to support memories suitable to high-density and low-power applications. To support mixed voltage environments, 2.5V, 3.3V drive and 5V-tolerant IO cells are available. LVTTL, LVCMOS, PCI, OSC, AGP, PECL, HSTL, LVDS and USB buffers are supported. To better support a system-on-chip design style, various core cells are available including processor cores like ARM7TDMI/ARM9TDMI/ ARM920T/ARM940T ARM920T/ARM940T from ARM, Teaklite from DSPG. The STDM110 STDM110 supports data transmission and communication core such as USB, IEEE1284 IEEE1284 and UART. The list of analog core cells includes ADC, DAC, CODEC, LVDS, RAMDAC and PLL with various bits and frequency ranges. Samsung design methodology offers an comprehensive timing driven design flow including automated time budgeting, tight floorplan synthesis intergration, powerful timing analysis and timing driven layout. Its advanced characterization flow provides accurate timing data and robust delay models for a 0.25um very deep-submicron technology. Advanced verification methods like static timing analysis and formal verification provide an effective verification methodology with a variety of simulators and cycle based simulation. Samsung DFT methodology supports scan design, BIST and JTAG boundary scan. Samsung provides a full set of test-ready IPs with an efficient core test integration methodology. Samsung ASIC 1-1 STDM110 STDM110 1.2 Features 1.2 Features Introduction · · · · · · · · · · STDM110 STDM110 1.8V standard cell library including processor and analog cores 0.25um five layer metal(from four layer metal option) CMOS technology - Logic, processor and analog High basic cell usages - Up to 8 million gates - Maximum usage: 75% for five layer metal High speed - Typical 2-input NAND gate delay (ND2D4): 112ps (F/O=2 + WL (0.02pF) Operation temperature (TA) - Commercial range: 0°C to +70°C - Industrial range: -40°C to +85°C Digital cores usages - Hard-macro: ARM7TDMI, ARM9TDMI, ARM920T ARM920T, ARM940T ARM940T, Teaklite - Soft-macro: AMBA, DMA Controller, SDRAM Controller, Interrupt Controller, IIC, WDT, RTC, USB, IrDA, UART(16C450 16C450, 16C550 16C550), Fast Ethernet MAC, P1394a LINK, RS Decoder, Viterbi Decoder Analog cores usages - Ultra low voltage analog core (2.5V and 1.8V) available - Analog core supply voltage: 2.5V analog core: 2.5V ± 5% 1.8V analog core: 1.8V ± 5% - ADC: 8bit (30M, 2.5V), 10bit (30M, 100M, 2.5V), (250K, 20M, 1.8V), 12bit (200K, 20M, 2.5V) - DAC: 8bit (2M, 2.5V), 10bit (300M, 2.5V), (2M, 1.8V), 12bit (2M, 2.5V), (80M, 1.8V) - CODEC: 8bit (8K~11K), 16bit (44.1K) - PLL: 25M ~ 300M (FSPLL, 2.5V), 1G (PLL, 1.8V), 20M ~ 170M(FSPLL, 1.8V) - Others: 300M (RAMDAC+PLL) Fully user-configurable Static RAMs and ROMs - High-density and low-power memory available - Duty-free cycle in synchronous memory available - 2-bank architecture available - Flexible aspect ratio available - Up to 256K-bit single-port SRAM available. - Up to 128K-bit dual-port SRAM available. - Up to 512K-bit diffusion and metal-2 ROM available. - Up to 16K-bit multi-port register file available. - Up to 32K-bit FIFO available. Fully configurable datapath macrocells - 4 ~ 64 bit adder available - 4 ~ 64 bit barrel shifter available - 6 ~ 64 bit multiplier with 1-stage pipeline available - Various output driver strength available - A tightly integrate apollo, Avant!, design environment I/O cells - 2.5V/3.3V and 5V tolerant IO - 3-level (high, medium, no) slew rate control - 1/2/4/6/8/10/12mA available for 3.3V and 2.5V output buffers - 1/2/3mA available for 5V-tolerant output buffers 1-2 Samsung ASIC Introduction 1.2 · · · Features IO IP available - PCI (33MHz, 66MHz, 3.3V), (33MHz, 3.3/5V tolerant) - USB (full speed/low speed) - SSTL2 (DDR SDRAM interface, up to 200MHz) - AGP (AGP2.0 Compliant, 66MHz@1X,133MHz@2X, 266MHz@4X) - PECL (2.5V interface, up to 400MHz) - HSTL (class1, class2, 30MHz) - LVDS (3.3V(2.5V optional) interface, 300MHz) Various package options - QFP, thin QFP, power QFP, plastic BGA, super BGA, plastic leaded chip carrier, etc. Fully integrated CAD software and EDA support - Logic synthesis: Synopsys Design Compiler - Logic simulation: Cadence Verilog-XL, Cadence NC-Verilog, Viewlogic ViewSim, Mentor ModelSim-VHDL, Mentor ModelSim-Verilog, Synopsys VSS, Synopsys VCS - Scan insertion and ATPG: Synopsys TestGen, Synopsys Test Compiler, Mentor Fastscan - Static timing analysis: Synopsys PrimeTime, Synopsys MOTIVE - RC analysis: Avant! Star-RC - Power analysis: Synopsys DesignPower, CubicPower (ln-House Tool) - Formal verification: Synopsys Formality, Chrysalis Design VERIFYer, Verplex Tuxedo-LEC - Fault simulation: Cadence Verifault, SuperTest (In-House Tool) - Delay calculator: CubicDelay (In-House Tool) · STDM110 STDM110 contains 12 user selectable clock tree cells(CTC). At the pre-layout design stage, these will be used as the cells which represent actual clock tree informatin of P&R. The key features of new Samsung ASIC CTS flow are as follows: - 12 user selectable clock tree cells(CTC) for STDM110 STDM110 - Good pre-layout and post-layout correlation - No customer netlist modification - Accurate post-layout back-annotation mechanism - Insertion delay, skew, transition time management - Clock tree information file generation - Cover 100 to 30,000 fanouts and up to 1M gate count for CTS spanning block (GCCSB) - Tightly coupled with Samsung in-house delay calculator, CubicDelay Gated CTS support - Hierarchical/Flatten verilog, edif interface for P&R For more detail information for CTC flow, refer to "CTC flow guideline for CubicDelay" included in Samsung ASIC design kit. Samsung ASIC 1-3 STDM110 STDM110 1.3 EDA Support 1.3 EDA Support Introduction Samsung ASIC provides an efficient solution for multi-million gate ASICs in very deep submicron (VDSM) technology. For large system-on-chip (SOC) type designs, static verification methodology (static timing analysis and formal verification) will shorten your design cycle time, which in turn will lessen today's ever-increasing time-to-market pressure. Our Design-for-Test (DFT) methodology and service take you through all phases of test insertion, test pattern generation and fault grading to get high test coverage. STDM110 STDM110 supports a rich collection of industry-standard EDA tools from Cadence, Synopsys, Mentor graphics, and Avant! on multiple design platforms such as Solaris and HP. Customers are allowed to choose among the industryleading EDA tools from design capture, synthesis, simulation, and DFT to layout. Several powerful proprietary software tools are seamlessly integrated in our design kits to improve your product quality. For high simulation accuracy, STDM110 STDM110 uses a proprietary delay calculator. Cell delay is calculated based on a matrix of delay parameters for each macrocell, and signal interconnect delay is calculated based on the RC tree analysis. 1.4 Product Family STDM110 STDM110 library include the following design elements: s Analog core cells s Digital core cells s Internal macrocells s Compiled macrocells s Input/Output cells. 1.4.1 ANALOG CORE CELLS Introduction to Analog Cores Samsung ASIC is one of the leading suppliers of cell based mixed analog and digital designs. As a leading supplier of mixed analog and digital designs, Samsung ASIC has more analog design experience than any other vendors. Analog has been and will continue to be a part of the strategic focus at Samsung ASIC. Analog design is a part of the total Samsung ASIC integrated design system. Workstation symbols are supplied for analog cells and are entered as part of the design by the customer or design center. Samsung ASIC uses basically the same automatic layout and verification tools for analog cells as for digital cells. Analog designs are processed on the same production line as digital designs. Samsung's analog core family comprises ADC,DAC,PLL and sigma-delta ADC/ DAC, and their brief functional descriptions are introduced below. [data sheets for all analog cores available] Analog-to-Digital Converters Analog-to-digital converters provide the link between the analog world and digital systems. Due to their extensive use of analog and mixed analog-digital operations, A/D converters often appear as the bottleneck in data processing applications, limiting the overall speed or precision. An A/D converter produces a digital output, D, as a function of the analog input, A: D = f(A) While the input can assume an infinite number of values, the output can be selected from only a finite set of codes given by the converter's output word length(i.e, resolution). Thus, the ADC must approximate each input level with one STDM110 STDM110 1-4 Samsung ASIC Introduction 1.4 Product Family of these codes, this process is so called 'quantization'. In a digital system the amplitude is quantized into discrete steps, and at the same time the signal is sampled at discrete time intervals. This time interval is called sampling time or sampling frequency. After sampling and quantization process, the analog signal(A) becomes digital output (D). Digital-to-Analog Converters The D/A converters are the digital-to-analog conversion circuits, which are also called DACs. They can be considered as decoding devices that accept digitally coded signals and provide analog output in the form of currents or voltages. In this manner, they provide an interface between the digital signal of the computer systems and continuous signals of analog world. They are employed in a variety of applications, from CRT display systems and voice sythesizers to automatic test systems, digital controlled attenuators, and process control actuators. In addition, they are key components inside most A/D converters. Figure 1 shows the functional block diagram of a basic D/A converter system. The input to the D/A converter is a digital word, made up a stream of binary bits comprised of 1's and 0's. The output analog quantity A, which can be a voltage or current, is related to the input as b1 b2 bn A = KVREF - + - + . + - 2 1 n 2 2 2 where K is a scale factor, VREF is a reference voltage, n is the total number of bits, and b1,b2,.,bn are the bit coefficients, which are quntized to be a 1 or a 0. As a function of the input binary word which determines the bit coefficients, the output exhibits 2n discrete voltage level ranging from zero to a maximum value of n 2 ­1 Vo(max)= VREF -n 2 with a minimum step change Vo given as V REF Vo= - \ n 2 Figure 1-1. Digital Data Input Functional Block Diagram of Basic D/A Converter b1 b2 b3 D/A Converter Analog Output bn Samsung ASIC 1-5 STDM110 STDM110 1.4 Product Family Introduction Sigma-Delta ADC/DAC VLSI offers high speed and high density, but reduced accuracy for analog components and reduced signal range (reduced dynamic range). Hence, an exchange of digital complexity and of resolution in time for resolution in signal amplitude is needed. So good solution is over-sampling data converter. Oversampling sigma-delta converter is used in slow speed (audio band) application because of process limit. It's noise shaping (sigma-delta) feature make high resolution about max. SND=90~100dB In ADC path, analog single input is converted to differential signal with antialiasing filtering through anti-aliasing filter block. And sigma-delta modulator converts the signal into oversampled noise-shaping 1bit PDM (Pulse Density Modulation). Following digital decimation filter reject the out of band noise and outputs 16bits high resolution digital data with down sampled to Fs rate. In DAC path, digital input data is oversampled by interpolation filter and it is converted to noiseshaped 1bit PDM through digital sigma-delta modulator. Analog SC-post-filter rejects the out of band noise. And anti-image filter rejects sampling images and outputs single analog signal with high resolution. Phase Locked Loop Samsung's PLL cores implemented as an analog function provide frequency multiplication capabilities and enable system designers to synchronize ASIC chip-level clock networks with a common reference signal. In the past, designers wishing to incorporate a PLL into a digital design environment had only two options: (1) A special mixed-signal process to incorporate analog functions onto the chip (2) An all digital PLL that can be incorporated into a standard digital process. However, a mixed-signal process is too expensive to be a feasible solution. On the other hand digital PLLs typically require huge silicon area and exhibits poor locking time despite their high accuracy. Differing from the previous solutions, Samsung's PLL cores can be implemented on standard digital CMOS process while functioning as an analog PLL. Samsung's PLL cores: * Require only a few off-chip passive components for the whole function * Remove the need for an expensive mixed-signal process * Provide faster locking time than all digital PLLs * Present low jitter characteristics Glossary by Core Families 1. Digital-to-Analog Converter 1. Resolution - An n-bit binary converter should be able to provide 2n distinct and different analog output values corresponding to the set of n-bit binary words. A converter that satisfies this criterion is said to have resolution of n bits. The smallest output change that can be resolved by a linear DAC is 2-n of the full-scale span. 2. Accuracy - Error of a D/A converter is the difference between the actual analog output and the output that is expected when a given digital code is applied to the converter. Source of error include gain error, offset error, linearity errors and noise. Error is usually commensurate with resolution, less than 2-(n+1), or 1/2 LSB of full scale. STDM110 STDM110 1-6 Samsung ASIC Introduction 1.4 Figure 1-2. Product Family Error of D/A Converter Analog Output Analog Output Actual Gain Error Ideal Ideal Actual Offset Error Digital Input Digital Input 3. LSB (Least-Significant Bit) - In a system in which a numerical magnitude is represented by a series of binary digits, the LSB is that bit that carries the smallest value or weight. It represents the smallest analog change that can be resolved by an n-bit converter. LSB (Analog Value) = FSR/2n FSR = Full-Scale Range, n = number of bits 4. MSB (Most-Significant Bit) - The binary digit with the largest numerical weighting. Normally, the MSB of a digital word has a weighting of 1/2 the full range. 5. Compliance-Voltage Range - For a current output DAC, the maximum range of(output) terminal voltage for which the device will provide the specified currentoutput characteristics. 6. Glitch - A glitch is a switching transient appearing in the output during a code transition. Its value is expressed as a product of voltage (V*ns) or current (mA*ns) and time duration or charge transferred. 7. Harmonic Distortion (and Total Harmonic Distortion) - The DAC is driven by the digitized representation of sine wave. The ratio of the RMS sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower order harmonics are included, such as second through fifth. 2 2 2 2 1/2 ( V2 + V3 + V4 + V5 ) THD = 20log -V1 V1: RMS amplitude of the fundamental 8. Signal-to-Noise Ratio (SNR) - This signal to noise ratio depends on the resolution of the converter and automatically includes specifications of linearity, distortion, sampling time uncertainty, glitches, noise, and settling time. Over half the sampling frequency, this signal to noise ratio must be specified and should ideally follows the theoretical formula; S/Nmax = 6.02N + 1.76dB 9. Slew Rate - Slew rate of a device or circuit is a limitation in the rate of change of output voltage, usually imposed by some basic circuit consideration such as limited current to charge of capacitor. Amplifiers with slew rate of a few V/µs are common and moderate in cost. Slew rates greater than about 75 V/µs are usually seen only in more sophisticated (and expensive) devices The output slewing speed of a voltage-output D/A converter is usually limited by the slew rate of the amplifier used at its output (if one is used). Samsung ASIC 1-7 STDM110 STDM110 1.4 Product Family Introduction 10. Settling Time - The time required, following a prescribed data change from the 50% point of the login input change, for the output of a DAC to reach and to remain within a given fraction (usually ±1/2lsb) of the final value. Typical prescribed changes are full scale, 1MSB and 1LSB at a major carry. Settling time of current-output DACs is quite fast. The major share of settling time of a voltageoutput DAC is usually contributed by the settling time of the output op-amp circuit. Figure 1-3. Setting Time +V0 V0 -V0 Slew Rate 1 Slewing Setting Time to V0 Final Setting 11. Power-Supply Sensitivity -The sensitivity of a converter to changes in the power-supply voltages is normally expressed in terms of percent-of-full-scale change in analog output value (of fractions of 1LSB) for a 1% dc change in the power supply. Power supply sensitivity may also expressed in relation to a specified dc shift of supply voltage. A converter may be considered "good" if the change in reading at full scale does not exceed 1/2LSB for 3% change in power supply. Even better specs are necessary for converters designed for battery operation. 12. ILE (integral Linearity Error) - Linearity error of a converter, expressed in %, ppm of full-scale range or multiples of 1LSB, is a deviation of the analog values in a plot of the measured conversion relationship from a straight line. The straight line can be either a "best straight line" determined empirically by manipulation of the gain and/or offset to equalize maximum positive and negative deviation of the actual transfer characteristics from this straight line; or it can be a straight line passing through the endpoints of the transfer characteristic endpoints of the transfer characteristic after they have been calibrated (sometimes referred to as "endpoint" linearity). Endpoint linearity error is similar to relative accuracy error. For multiplying D/A converters, the analog linearity error, at a specified digital code, is defined in the same way as for multipliers, by deviation from a "best straight line" through the plot of the analog output-input response. 13. DLE (Differential Linearity Error) - Any two adjacent digital codes should result in measured output values that are exactly 1LSB apart (2-n of full scale for an n-bit converter). Any deviation of the measured "step" from the ideal difference is called differential linearity error expressed in multiplies of 1LSB. It is an important specification because a differential linearity error greater than 1LSB can lead to non-monotonic response in a D/A converter and missed codes in an A/D converter. 14. Monotonic - A DAC is said to be monotonic if the output either increases or remains constant as the digital input increases with the result that the output will always be a single-valued function of the input. The specification "monotonic" STDM110 STDM110 1-8 Samsung ASIC Introduction 1.4 Product Family (over a given temperature range) is sometimes substituted for a differential nonlinearity specification since differential nonlinearity less than 1LSB is a sufficient condition for monotonic behaviour. 2. Analog-to-Digital Converter 1. ILE (Integral Linearity Error: INL) - Integral nonlinearity refers to the deviation of each individual code from a line drawn from "zero" through "full scale". The point used as "zero" occurs 1/2LSB before the first code transition. "Full scale" is defined as a level 1 1/2LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line. 2. DLE (Differential Linearity Error: DNL) - An ideal ADC exhibits code transitions that are exactly 1LSB apart. DNL is the deviation from this ideal value. It is often specified in terms of the resolution for which no missing codes are guaranteed. 3. Offset Error - The first transition should occur at a level 1/2LSB above "zero". Offset is defined as the deviation of the actual first code transition from that point. 4. Gain Error - The first code transition should occur for an analog value 1/2LSB above nominal negative full scale. The last transition should occur for an analog value 1 1/2LSB below the nominal positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions. 5. Pipeline Delay (Latency) - The number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided every clock cycle. 6. Effective Number of Bits (ENOB) - This is a measure of a device's dynamic performance and may be obtained from the SNDR or from a sine wave curve test fit according to the following expression: ENOB = SNDR - 1.76/6.02 ENOB = N-log2[RMS error (actual) / RMS error (ideal)] 7. Analog Bandwidth - The analog input frequency at which the spectral power of the fundamental frequency, as determined by FFT analysis is reduced by 3dB. 8. Aperture Delay - The delay between the sampling clock and the instant the analog input signal is sampled. 9. Aperture Jitter - The sample to sample variation in aperture delay. 10. Bit Error Rate (BER) - The number of spurious code errors produced for any given input sine wave frequency at a given clock frequency. In this case it is the number of codes occurring outside the histogram cusp for a 1/2 FS sine wave. 11. Signal to Noise Ratio - This signal to noise ratio depends on the resolution of the converter and automatically includes specifications of linearity, distortion, sampling time uncertainty, glitches, noise, and settling time. Over half the sampling frequency, this signal to noise ratio must be specified and should ideally follow the theoretical formula; S/Nmax = 6.02N + 1.76dB Samsung ASIC 1-9 STDM110 STDM110 1.4 Product Family Introduction 3. Phase Locked Loop 1. Lock Time - The time it takes the PLL to lock onto the system clock. Fast or slow lock time may be controlled by the loop filter characteristics. The loop filter characteristics are controlled by varying the R and C components. (Remember that R and C define the damping-factor as well) 2. Phase Error - The phase difference between the feedback clock signal and the system signal clock. 3. Clock Jitter - The deviations in a clock's output transitions from their ideal positions define the clock jitter. Jitter is sometimes specified as an absolute value in nanoseconds. All jitter measurement are made at a specified voltage. 1) Cycle-to-Cycle Jitter: The change in a clock's output transition from its corresponding position in the previous cycle. This kind of jitter is the most difficult to measure and usually requires a time-interval analyzer Figure 1-4. Cycle-to-Cycle Jitter t1 t2 t3 Clock Noise: jitter J1 = t2-t1 jitter J2 = t3-t2 : The maximum of such values over multiple cycles (J1,J2.) is the max. cycle-tocycle jitter. 2) Period Jitter: Period jitter measures the maximum change in a clock's output transition from its ideal position. You can use period-jitter measurements to calculate timing margins in systems. Figure 1-5. Period Jitter ideal cycle: t1 Clock Jitter 3) Long-term Jitter: Long-term jitter measures the maximum change in a clock's output transition from its ideal position over many cycles. How many cycles depends on the application and the frequency. A classic example of system affected by long-term jitter is a graphics card driving a CRT 4) Power Down Mode: PLL state in which the quiescent current is lowered to a very low level to conserve power. 5) Synthesize clock: a system clock may run at a relatively low rate compared to system components. A CPU, for example, may require an internal clock that is several times faster than the system I/O bus clock. Designers can use PLL STDM110 STDM110 1-10 Samsung ASIC Introduction 1.4 Product Family technology to synthesize a higher frequency on-chip clock using the system clock as a reference. 6) Deskew clock: Multiple chips on a printed circuit board or cores of different sizes within a single system on a chip experience clock skew. By using PLL or DLL technology to shift the phase of the reference clock within each chip or core, designers can minimize skew tune a system to perform up its potential. 7) Duty Ratio: the percentage of the period that the output is in a high state. 8) Output frequency range: The maximum output frequency range minus the minimum output frequency that is produced with an input signal for which the cell specifications still apply. Customer Service Samsung provides a full custom support for our customers need of analog cores. Samsung's worldwide sales offices and representatives give our customers a first-hand support for analog cores. And if needed, Samsung engineers are prepared to provide a fully customized total solution to satisfy our customers. Technical Support If our customers want to develop mixed-signal products, Samsung provides all technical support to meet customers needs. Mixed-signal design is quite different from pure logic design in terms of circuit design, techniques, layout and test methodology. Thus Samsung provides a successful technical guide and firmly support for all development steps. Definition of Analog Core Data Sheet Types Each product developed by Samsung will be supported by technical literature where the data sheets progress through the following levels of refinement 1. Core Preview Describes the main features and specifications for core that is under development. Some specifications such as exact pin-outs may not be finalized at time of publication.The purpose of this document is to provide customers with advance product planning information. 2. Preliminary Datasheet This is the first document completely describing a new core. It contains an features, application, timing diagram, theory of operation, core pin information, test guide, layout guide and AC/DC electrical information. This data sheet are based on prototype silicon performance and on worst case simulation models.The purpose of this data sheet is to provide ASIC customer with technical information sufficiently detailed to guarantee that they can safely begin active development. 3.Final Data sheet This is an updated version of preliminary data sheet reflecting actual performance of the final silicon. Updates include tighter specifications, more min. and max. values. The purpose of this data sheet is to communicate the confirmed performance of cores which have passed qualification, been fully characterized. Samsung ASIC 1-11 STDM110 STDM110 1.4 Product Family Introduction 1.4.2 INTERNAL MACROCELLS Internal Macrocells are the lowest level of logic functions such as NAND, NOR and flip-flop used for logic designs. There are about 471 different types of internal macrocells. They usually come in four levels of drive strength (0.5X, 1X, 2X and 4X). These macrocells have many levels of representations-logic symbol, logic model, timing model, transistor schematic, HSPICE netlist, physical layout, and placement and routing model. 1.4.3 COMPILED MACROCELLS Compiled macrocells of STDM110 STDM110 consist of compiled memory and compiled datapath macrocells. 1.4.3.1 Compiled Memory Macrocells Memories in STDM110 STDM110 are fully user-configurable and are provided as a compiler. Two different types of memories are available in STDM110 STDM110. One is suitable for high-density application with high-performance, called STDM110-HD STDM110-HD compiled memory. The other is suitable for low-power application, called STDM110-LP STDM110-LP compiled memory. In STDM110-HD STDM110-HD compiled memory, eight types of memories are available such as single-port synchronous/asynchronous static RAM, dual-port synchronous static RAM, synchronous diffusion/metal-programmable ROM, multi-port asynchronous register file and synchronous first-in first-out memory. Synchronous memories have a fully synchronous operation at the rising-edge of clock and the duty-free cycle is available. Also, the bit-write capability is available. Asynchronous memories have a synchronous operation for a write enable signal during write mode and have an asynchronous operation for address signal during read mode. Multi-port asynchronous register file supports four kinds of configurations such as 2 port(1-read/1-write), 3 port(1-read/2-write and 2-read/1write) and 4 port (2-read/2-write). The first-in first-out memory which is widely used in communication buffering types of applications has also fully synchronous operation at the rising- edge of clock. On the other hand, in STDM110-LP STDM110-LP compiled memory, five types of memories are available such as single-port synchronous/asynchronous static RAM, dual-port synchronous static RAM and synchronous diffusion/metal-programmable ROM. Synchronous memories are almost same as that of STDM110-HD STDM110-HD except that the duty-free cycle is not available. Asynchronous memory is same as that of STDM110-HD STDM110-HD. To dramatically reduce the power consumption in STDM110-LP STDM110-LP, some of lowpower techniques such as a partial activation architecture in cell array and a divided word-line structure was adopted, rather than STDM110-HD STDM110-HD. Basically in STDM110-HD STDM110-HD and STDM110-LP STDM110-LP, the power-down mode which significantly reduces the power dissipated during a read or write mode is provided. Also compiled memories have a standby mode except multi-port asynchronous register file and first-in first-out memory. While in standby mode, the data stored in the memory is retained, data outputs remain stable and the power is greatly reduced because memory operation is internally blocked while the memory contents and the data outputs are unaffected. STDM110 STDM110 1-12 Samsung ASIC Introduction 1.4 Product Family To improve the memory performance and to reduce the power consumption, 2bank architecture is provided except some memories such as dual-port synchronous static RAM, multi- port asynchronous register file and first-in first-out memory. In 2-bank architecture, only one bank is activated and the other bank is in standby mode. To support various memory shapes which are determined by the floorplan of a chip design, flexible memory aspect ratios are provided. For certain specific memory configuration, all types of timing, power and area values are provided by an automatic datasheet generator. To easily do interface to layout, the physical abstract data for Silicon Ensemble and Apollo, called phantom cell or black box, is provided. BIST(Built-In Self-Test) circuitry is currently available for most of STDM110 STDM110 compiled memories. BIST circuits are designed to detect a set of fault types that impact the functionality of memory and is generated by a softmacro-based BIST generator. The softmacro-based BIST generator generates both an individual BIST netlist for each memory and a shared BIST netlist for all memories used in a design. However, when several memories of the same or the different type area used in the design, if you generate the individual BIST netlist for each memory, there are some redundant blocks because the individual BIST netlist has same function. In this case, it would better use the shared BIST netlist to eliminate such redundancy and reduce area. 1.4.3.2 Compiled Datapath Macrocells Compiled datapath macro cells include Adder, Barrel Shifter and Multiplier. Adder performs the adding or adding/subtracting operation on the control of a mode selection signal. Barrel Shifter makes input data shift or rotate in the left/right direction. In the shift operation, the vacant bit can be padded with zero, MSB value, or external data. Multiplier performs the 2's compliment multiplication. One pipeline stage insertion is available to get a high operating frequency. They have two output drive strengths, which are equal to the 1X and 2X-Drive in the primitive cell library. The hard macro cells are built through the Apollo, placement and routing tool from Avant!. All the leaf cells have the same physical configuration compatible with the primitive cell library. It allows that any primitive cell can be used as a bit slice cell in the datapath module design. We provide two kinds of engineering design services. One is to support additional compiled datapath macrocells such as ALUs, Comparators, Priority encoders, Incrementers and Decrementers, and so on. Another is to make hardwired datapath module design which provides a regular structured layout. Samsung ASIC 1-13 STDM110 STDM110 1.4 Product Family Introduction 1.4.4 INPUT/OUTPUT CELLS There are about seven hundreds different I/O buffers. Each I/O cell is implemented solely on the basic I/O cell architecture which forms the periphery of a chip. A test logic is provided to enable the efficient parametric (threshold voltage) testing on input buffers including LVCMOS and TTL level converters, Schmitt trigger input buffers, clock drivers and oscillator buffers. Pull-up and pull-down resistors are optional features. Three basic types of output buffers (non-inverting, tri-state and open drain) are available in a range of driving capabilities from 1mA to 12mA for 2.5V, 3.3V drive and from 1mA to 3mA for 5.0V tolerant drive. One or two levels of slew rate controls are provided for each buffer type (except 1mA, 2mA and 3mA buffers) to reduce output power/ground noise and signal ringing, especially in simultaneous switching outputs. Bi-directional buffers are combinations of input buffers and output buffers (tristate and open drain) in a single unit. The I/O structure has been fully characterized for ESD protection and latch-up resistance. For user's convenience, STDM110 STDM110 library provides 100K pull-down and pull-up resistance respectively. 1.4.4.1 I/O Applications To support mixed voltage environments, LVTTL, LVCMOS and Schmitt trigger I/ O cells are available at 2.5V, 3.3V interface and 5V tolerant interface. The I/O application diagram is as follows. Figure 1-6. I/O Applications 2.5V 2.5V C B 2.5 T S 3.3V C 3.3/ 5V tolerant Internal Circuit operating voltage: 1.8V D 3.3V B S T T 3.3 D Input Buffer 1.4.4.2 2.5 Output Buffer I/O Cell Drives Options To provide designers with the greater flexibility, each I/O buffer can be selected among various current levels (e.g., 1mA, 2mA,., 12mA). The choice of currentlevel for I/O buffers affects their propagation delay and current noise. The slew rate control helps decrease the system noise and output signal overshoot/undershoot caused by the switching of output buffers. The output edge rate can be slowed down by selecting the high slew rate control cells. STDM110 STDM110 1-14 Samsung ASIC Introduction 1.4 Product Family STDM110 STDM110 provides three different sets of output slew rate controls. Only one I/O slot is required for any slew rate control options. 1.4.4.3 5V Tolerant I/O Buffers STDM110 STDM110 I/O library is based on a process which has the most optimum performance in 1.8V. In this process, voltage more than 3.6V are not allowed at the gate oxide because of a reliability problem. And a special circuit is adopted in order to make pin voltage tolerable up to 5.25V and to offer TTL interface driving up to 3mA. Obviously, this circuit is constructed not to permit more than 3.6V at the gate oxide. The external circuit diagram is as follows. The maximum external tolerance of this buffer is 5.25V. It can be used as a 3.3V normal buffer. Figure 1-7. 5V Tolerant I/O Buffers 3.3V 3.3V 5.0V Output voltage 3.3V Open drain output 5V tolerant input Tri-state output TTL Input Bi-directional I/O TTL Input 0.25µm 2.5V process Normal 5V process 1.4.4.4 PCI Buffers PCI buffers are designed for PCI local bus application which is an industrystandard, high-performance 32bit or 64bit bus architecture. Samsung ASIC offers input, output, bi-directional PCI buffers for 33MHz and 66MHz operation. These buffers are compliant with PCI local bus specification 2.1. 1.4.4.5 USB (Universal Serial Bus) Buffers Various kinds of peripheral equipment such as mouse, joy stick, keyboard, modem, scanner and printer improve the power of a computer. However, it is not easy to connect and use them properly in the computer. USB specification established late in 1995 is a good solution for this problem, providing facile method of an expansion. Samsung ASIC offers full speed and low speed USB buffers that complies with Universal Serial Bus specification 1.0, 1.1. 1.4.4.6 Other Buffers Samsung ASIC can support various kinds of buffers such as HSTL, SSTL, AGP, PECL, LVDS, and so on. For more information please contact us. Samsung ASIC 1-15 STDM110 STDM110 1.5 Timings Introduction 1.5 Timings 1.5.1 WIRE LENGTH LOAD Table 1-1. shows the equivalent standard load matrix for 4-layer and 5-layer metal interconnect. The equivalent standard load values are function of gate count and fanout. These values are based on capacitive loading and are used in wire length estimates which affect propagation delay. Table 1-1. Gates Count Equivalent Standard loads for 4-layer and 5-layer Metal Interconnect Fanouts 1 2 3 4 5 6 5000 1.159 2.242 3.822 5.113 5.965 7.020 10000 1.530 2.932 5.561 7.701 8.964 10.500 50000 4.192 8.247 12.439 16.494 16.801 17.980 7 8 16 32 64 7.859 10.94 28.672 45.642 79.821 12.110 15.211 29.903 47.725 83.520 21.026 22.806 35.536 48.347 84.605 4LM 100000 4.596 9.327 13.925 18.523 18.889 20.241 23.582 27.031 41.002 54.253 94.944 150000 12.843 17.125 21.406 22.684 23.600 24.296 26.001 29.730 39.828 63.672 127.344 200000 13.520 18.026 22.533 23.885 24.849 25.582 27.372 31.299 41.865 66.931 133.812 300000 14.871 19.830 24.786 26.588 27.596 28.363 30.317 34.634 46.268 73.871 147.587 400000 16.225 21.631 26.852 28.693 29.845 30.718 32.868 37.479 50.016 79.707 159.207 500000 18.099 24.132 30.166 32.177 33.435 34.390 36.777 42.032 53.235 84.861 169.459 600000 19.375 25.836 32.476 34.593 35.915 36.919 39.467 45.186 54.763 87.312 174.320 800000 22.324 29.767 37.739 40.113 41.593 42.719 45.642 52.399 59.180 94.390 188.385 1000000 25.078 33.439 42.657 45.272 46.898 48.140 51.408 59.135 63.283 100.964 201.447 1500000 32.631 43.509 56.047 59.341 61.381 62.946 67.174 77.514 75.639 120.743 240.788 2000000 39.706 52.941 68.596 72.524 74.956 76.821 81.946 94.736 87.196 139.244 277.587 2500000 46.327 61.770 80.342 84.864 87.657 89.807 95.771 110.853 97.994 156.527 311.959 3000000 52.517 70.023 91.321 96.399 99.532 101.946 108.693 125.919 108.065 172.646 344.022 4000000 60.251 80.335 104.770 110.594 114.189 116.958 124.701 144.463 123.979 198.073 394.685 5000000 67.558 90.078 117.479 124.008 128.041 131.146 139.827 161.985 139.017 222.099 442.560 6000000 75.754 101.005 131.728 139.052 143.573 147.053 156.788 181.634 155.879 249.038 496.241 5000 1.101 2.131 3.631 4.856 5.667 6.669 7.466 10.397 27.238 43.360 75.830 10000 1.454 2.786 5.283 7.317 8.515 9.976 11.505 14.451 28.408 45.339 79.344 50000 3.982 7.834 11.818 15.670 15.961 17.081 19.976 21.666 33.760 45.929 80.374 5LM 100000 4.366 8.861 13.229 17.597 17.944 19.229 22.403 25.679 38.952 51.540 90.198 150000 12.201 16.268 20.336 21.549 22.420 23.081 24.701 28.244 37.837 60.488 120.977 200000 12.843 17.125 21.406 22.691 23.606 24.304 26.004 29.734 39.771 63.584 127.122 300000 14.128 18.839 23.546 25.259 26.216 26.944 28.801 32.903 43.955 70.178 140.207 400000 15.414 20.549 25.509 27.257 28.353 29.181 31.225 35.606 47.515 75.722 151.247 500000 17.195 22.925 28.658 30.567 31.763 32.670 34.938 39.931 50.573 80.618 160.986 600000 18.406 24.543 30.852 32.862 34.119 35.073 37.494 42.926 52.025 82.947 165.605 800000 21.208 28.278 35.852 38.107 39.514 40.584 43.360 49.779 56.220 89.670 178.967 1000000 23.825 31.767 40.524 43.008 44.554 45.733 48.837 56.178 60.119 95.916 191.374 1500000 31.000 41.333 53.245 56.374 58.312 59.798 63.815 73.637 71.856 114.706 228.749 2000000 37.721 50.295 65.166 68.898 71.208 72.980 77.849 90.000 82.837 132.281 263.707 2500000 44.011 58.682 76.324 80.621 83.274 85.317 90.983 105.311 93.093 148.700 296.362 3000000 49.891 66.523 86.755 91.579 94.555 96.849 103.257 119.622 102.661 164.014 326.821 4000000 57.239 76.318 99.532 105.065 108.479 111.110 118.466 137.239 117.779 188.169 374.950 5000000 64.180 85.575 111.606 117.807 121.639 124.588 132.836 153.885 132.067 210.995 420.432 6000000 71.965 95.955 125.141 132.099 136.394 139.700 148.949 172.552 148.084 236.587 471.429 7000000 78.436 104.582 136.393 143.976 148.655 152.259 162.339 188.067 161.397 257.858 513.812 8000000 87.950 117.266 152.935 161.439 166.687 170.727 182.031 210.877 180.976 289.134 576.135 STDM110 STDM110 1-16 Samsung ASIC Introduction 1.5 Timings 1.5.2 TIMING PARAMETERS This section discusses issues involving timing parameters. 1.5.2.1 Transition Time Figure 1-8. shows the definition of rise transition time (tR) and fall transition time (tF). Transition time is defined as the delay between the time when the input (output) signal voltage level is 10% of supply voltage (VDD) and the time of the input (output) signal voltage level is 90% of VDD. Figure 1-8. Rise and Fall Transition Time VDD 90% 90% 10% 10% tR 1.5.2.2 tF Propagation Delay Figure 1-9. shows the definition of propagation delays. Propagation delay is defined as the delay between the time when the input signal voltage level is 50% of supply voltage (VDD) and the time when the output signal voltage level is 50% of VDD. Figure 1-9. Propagation Delay In 50% In Out tPLH 50% tPHL 50% 50% Out In VDD In 50% 50% tPHL tPLH Out 50% 50% Out Samsung ASIC 1-17 STDM110 STDM110 1.5 Timings Introduction 1.5.2.3 Setup / Hold Time Figure 1-10. shows the definition of setup time and hold time. The setup timing check is defined as the minimum interval which a data signal must remain stable before active transition of a clock. Any change to the data signal within this interval results in a timing violation. The hold timing check is defined as the minimum interval which a data signal must remain stable after active transition of a clock. Any change to the data signal within this interval results in a timing violation. Figure 1-10. Setup and Hold Time 50% D 50% 50% CK tSU tHD 1.5.2.4 Recovery Time Figure 1-11. shows the definition of recovery time. A recovery timing check measures the time between the release of an asynchronous control signal from the active state to the next active clock edge. For example, the time between RN and the CK of FD2 cell. If the active edge of the CK occurs too soon after the release of the RN, the state of the FD2 becomes uncertain. The state can be the value set by the RN or the value clocked into the FD2 from the data input. Figure 1-11. Recovery Time 50% RN 50% CK tRC STDM110 STDM110 1-18 Samsung ASIC Introduction 1.5 1.5.2.5 Timings Removal Time Figure 1-12. shows the definition of removal time. A removal timing check measures the time between the active clock edge and the release of an asynchronous control signal from the active state. For example, the time between RN and the CK of FD2 cell. If the release of the RN occurs too soon after the active edge of the clock, the state of the FD2 becomes uncertain. The uncertainty can be caused by the value set by the RN or the value clocked into the FD2 from the data input. Figure 1-12. Removal Time 50% RN 50% CK tRM 1.5.2.6 Minimum Pulse Width Figure 1-13. shows the definition of minimum pulse width. The minimum pulse width timing check is the minimum allowable time for the positive (high) or negative (low) phase of each cycle. Figure 1-13. Minimum Pulse Width 50% CK tPWH tPWL 1.5.2.7 Minimum Period Figure 1-14. shows the definition of minimum period. The minimum period timing check is the minimum allowable time for one complete cycle of the signal. Figure 1-14. Minimum Period 50% CK tPRD Samsung ASIC 1-19 STDM110 STDM110 1.5 Timings Introduction 1.5.3 TEMPERATURE AND SUPPLY VOLTAGE The next figure describes propagation delay derating factors (KT, KV) as a function of on-chip junction temperature (TJ) and supply voltage (VDD). As a result of power dissipation, the junction temperature is generally higher than the ambient temperature. The temperature of the die inside the package (junction temperature, TJ) is calculated using chip power dissipation and the thermal resistance to the ambient temperature (JA) of the package. Information on package thermal performance can be obtained from Samsung application engineers. Figure 1-15. Effect of Temperature and Supply Voltage on Propagation Delay Temperature (TJ) KT 1.129 1.079 1.060 1.000 0.966 0.909 ­40 0 25 70 85 125 (°C) Supply Voltage (VDD) KV 1.113 1.000 0.914 1.65 STDM110 STDM110 1-20 1.80 1.95 (Volt) Samsung ASIC Introduction 1.5 Timings 1.5.4 BEST AND WORST CASE CONDITIONS A circuit should be designed to operate properly within a given specification level, either commercial or industrial. It is recommended that circuits be simulated for best case, normal case, and worst case conditions at each specification level. The following expressions also allow for the effect of process variation on circuit performance. Best case(Worst case): TBC (TWC) = KP x KT x KV x TNOM where TBC = Best case propagation delay TWC = Worst case propagation delay TNOM = Normal propagation delay (TJ = 25 oC, VDD = 1.85V and typical process) KP, KT, KV = Refer toTable 1-2., Table 1-3., and Table 1-4. 1.5.5 DERATING FACTORS OF STDM110 STDM110 The multipliers can be applied to nominal delay data in order to estimate the effects of supply voltage, temperature and process. Nominal data are provided for conditions of VDD = 1.8V, TJ = 25°C and typical process. The derating factors of STDM110 STDM110 is as follows. Table 1-2. STDM110 STDM110 Cell Process Derating Factor (KP) Slow Table 1-3. Temp. (oC) KT Table 1-4. Fast 1.0 0.809 STDM110 STDM110 Cell Temperature Derating Factor (KT) 125 85 70 25 0 ­40 1.129 1.079 1.060 1.000 0.966 0.909 STDM110 STDM110 Cell Voltage Derating Factor (KV) Voltage (V) 1.65 1-21 1.80 1.95 1.113 KV Samsung ASIC Typ 1.252 Process Factor (KP) 1.000 0.914 STDM110 STDM110 1.6 Delay Model 1.6 Delay Model Introduction The ASIC timing characteristics consist of the following components: · Cell propagation delay from input to output transitions based on input waveform slope, fanout loads and distributed interconnection wire resistance and capacitance. · Interconnection wire delay across the metal lines. · Timing requirement parameters such as setup time, hold time, recovery time, skew time, minimum pulse width, etc. · Derating factors for junction temperature, power supply voltage, and process variations. Timing model for STDM110 STDM110 focuses on how to characterize cell propagation delay time accurately. To accomplish this goal, 2-dimensional table look-up delay model has been adopted. The index variables of this table are input waveform slope and output load capacitance. See the figure below. Samsung ASIC design automation system supports an n-dimensional table model even though we adopted 2-dimensional model for our 0.25µm cell-based products. Figure 1-16. 2-Dimensional Table Delay Model Propagation Delay [ns] 1.5 1.0 Load Cap [pF] 0.5 1.0 2.0 3.0 0.4 0.8 1.2 Input Waveform Slope [ns] STDM110 STDM110 1-22 Samsung ASIC Introduction 1.6 Delay Model The Table 1-5. shows an example of this model for 2-input NAND cell. The data in this table are high-to-low transition delay times from one of the two input pins to output pin. The number of points and values of the index variables can differ for each cell. Table 1-5. \ CAP Table Delay Model Example 0.0060 0.0260 0.0480 0.0920 0.1590 0.2480 0.0260 0.05808 0.12103 0.18966 0.32676 0.53545 0.81256 0.2730 0.09949 0.17367 0.24202 0.37902 0.58771 0.86485 0.4780 0.11632 0.20817 0.28627 0.42265 0.63065 0.90741 0.8870 0.13823 0.25166 1.35082 0.51127 0.71886 0.99418 1.5000 0.15769 0.29517 1.41346 0.60959 0.85193 1.12790 SLOP Notice that 5-by-6 table is used. Delay values between grid points and beyond this table are determined by linear interpolation and extrapolation methods. This general table delay model provides great flexibility as well as high accuracy since extensive software revisions are not required when a cell library is updated. The other timing components such as interconnection wire delay, timing requirement parameters and derating factors are characterized in a commonly-accepted way in industry. The figure below summarizes the features of Samsung ASIC's delay model. 2-dimensional table delay model for output loading and input waveform slope effects is used.The slopes (tR, tF) and delay times (tPLH, tPHL) of all cell instances are calculated recursively. The input waveform slope of each primary input pad and the loading capacitance of each primary output pad can be assigned individually or by default. Pin to pin delays of cells and interconnection wires are supported. The effect of distributed interconnection wire resistance and capacitance on cell delay is analysed using the effective capacitance concept. Figure 1-17. Features of Delay Model S1 A_Y CO1 CO2 B_Y S2 D Q CO3 S3 Samsung ASIC CK 1-23 STDM110 STDM110 1.7 Testability Design Methodology 1.7 Testability Design Methodology Introduction 1.7.1 SCAN DESIGN · · · Multiplexed scan flip-flop that minimizes the area or delay overhead needed to implement scan design. Automated design rules checking, scan insertion, and test pattern generation High fault coverage on synchronous designs 1.7.2 BOUNDARY-SCAN · · · · IEEE Std 1149.1 JTAG boundary-scan registers with primitive cells Boundary-Scan Description Language (BSDL) description for board testing Combination with internal scan design and core testing Boundary Scan Architecture A boundary scan architecture contains TAP (Test Access Port), TAP controller, instruction register and a group of test data registers. The instruction and test data registers are separate shift-register-based paths connected in parallel with a common serial data input and a common serial data output which are connected to TAP, TDI and TDO signals. TAP controller selects the alternative instruction and test data register paths between TDI and TDO. The schematic view of the top level design of the test logic architecture is shown in the Figure 118. Figure 1-18. JTAG Test Access Port (TAP) Block Diagram TDI TAP Controller TMS TCK Mux Instruction Register LOGIC Bypass Register SYSTEM Device Identity Register Scannable Register TEST ACCESS PORT (TAP) TDO Multiplexer Boundary Scan Path STDM110 STDM110 1-24 Samsung ASIC Introduction 1.7 Testability Design Methodology Boundary Scan Functional Block Descriptions TAP (Test Access Port) TAP is a general-purpose port that can provide with an access to many test support functions built into a component, including the test logic. It includes three inputs (TCK; Test Clock Signal, TMS; Test Mode Signal and TDI; Test Data Input) and one output (TDO; Test Data Output) required by the test logic. An optional fourth input (TRSTN; Test Reset) is provided for the asynchronous initialization of the test logic. The values applied at TMS and TDI pins are sampled on the rising edge of TCK, and the value placed on TDO pin changes on the falling edge of TCK. TAP Controller TAP controller receives TCK, interprets the signals on TMS, and generates clock and control signals for both instruction and test data registers and for other parts of the test circuitries as required. Instruction Register/Instruction Decoder Test instructions are shifted into and held by the instruction register. Test instructions include a selection of tests to be performed or the test data register to be accessed. A basic 3-bit instruction register and its instruction decoder are provided as macrofunctions in the library. Test Data Registers Data registers include a bypass register, a boundary scan register, a device identification register and other design specific registers. Only the bypass- and boundary scan registers are mandatory; the rest are optional. Bypass register: The bypass register provides a single-bit serial connection through the circuit when none of the other test data registers is selected. It can be used to allow test data to flow through a given device to the other components in a product without affecting a normal operation. Boundary scan register: The boundary scan register detects typical production defects in board interconnects, such as opens, shorts, etc. It also allows an access to component inputs and outputs when you test their logic or sample flow-through signals. Special boundary scan register macrocells are provided for this purpose. These special registers is discussed in the next section of next pages. Design-specific test data register: These optional registers may be provided to allow an access to design-specific test support features in the integrated circuit, such as self-test, scan test. Device identification register: This is an optional test data register that allows the manufacturer part number and variant of a components to be identified. The 32-bit identification register is partitioned into four fields: Device version identifier1st field Device part number Manufacturer's JEDEC number LSB Samsung ASIC The first four bits beginning from MSB 2nd field 16 bits 3rd field 11 bits 4th field 1 bit -tied in High 1-25 STDM110 STDM110 1.7 Testability Design Methodology Introduction The ASIC designer is free to fill the version and part number in any manner as long as the total twenty bits are used. Samsung's JEDEC code: 78 decimal = 1001110 Continuation field (4 bits) = 0000 Contents of device identification register: XXXX XXXXXXXXXXXXXXXX 0000 1001110 1 Users can define these two fields. Boundary Scan Register (connection of all boundary scan cells) Test Access Port (TAP) TDI Boundary Scan Path I/O Pad Instruction Register Test Data Register TMS TAP Controller Circuit Prior to Boundary Scan (Core Logic) TCK Bypass Register TDO MUX 1.7.3 BIST (BUILT-IN SELF-TEST) · · · STDM110 STDM110 Efficient test solution for compiled memory macrocells At speed and parallel testing of multiple memories Less routing overhead and test pin requirements 1-26 Samsung ASIC Introduction 1.8 Maximum Fanouts 1.8 1.8.1 INTERNAL MACROCELLS The maximum fanouts for STDM110 STDM110 primitive cells are as follows. Note that these fanout limitation values are calculated when the rise and fall times of the input signal is 0.273ns. Depending on the rise and fall times, the maximum fanout limitations can be varied case by case. In the following table the maximum fanout values for all pins of STDM110 STDM110 internal macrocells are listed. Table 1-6. Maximum Fanouts of Internal Macrocells (When input tR/tF = 0.273ns, one fanout (SL) = 0.006380pF) Cell Output Maximum Name Pin Fanout ad2 ad2d2 ad2d4 ad2dh ad3 ad3d2 ad3d4 ad3dh ad4 ad4d2 ad4d4 ad4dh ad5 ad5d2 ad5d4 ao21 ao211 ao2111 ao2111d2 ao211d2 ao211d2b ao211d4 ao211dh ao21d2 ao21d2b ao21d4 ao21dh ao22 ao221 ao221d2 ao221d4 ao222 ao2222 ao2222d2 ao2222d4 ao222a ao222d2 ao222d2a ao222d2b ao222d4 ao222d4a Samsung ASIC Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 37 76 149 16 37 74 146 16 37 72 142 16 17 35 150 17 10 6 77 20 76 154 5 34 75 151 8 16 9 75 151 9 5 75 151 14 18 75 75 151 151 1-27 Cell Name ao22a ao22d2 ao22d2a ao22d2b ao22d4 ao22d4a ao22dh ao22dha ao31 ao311 ao3111 ao3111d2 ao311d2 ao311d4 ao31d2 ao31d4 ao31dh ao32 ao321 ao321d2 ao321d4 ao322 ao322d2 ao322d4 ao32d2 ao32d4 ao33 ao331 ao331d2 ao331d4 ao332 ao332d2 ao332d4 ao33d2 ao33d4 ao4111 ao4111d2 busholder dc4 dc4i dc8i dl1d2 dl1d4 dl2d2 dl2d4 dl3d2 dl3d4 dl4d2 dl4d4 dl5d2 dl5d4 dl10d2 Maximum Fanouts Output Pin Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y0 Y1 Y2 Y3 YN0 YN1 YN2 YN3 YN0 YN1 YN2 YN3 YN4 YN5 YN6 YN7 Y Y Y Y Y Y Y Y Y Y Y Maximum Fanout 16 32 32 76 150 150 7 7 15 9 5 77 76 151 32 152 6 15 8 75 151 7 75 151 76 150 14 7 75 151 7 75 151 74 150 5 75 10000 37 37 37 36 33 33 33 34 23 23 23 23 23 23 23 23 76 154 76 154 76 154 76 154 76 154 76 STDM110 STDM110 1.8 Maximum Fanouts Introduction Cell Name dl10d4 oak_duclk 10 oak_duclk 16 fa fad2 fadh fd1 fd1d2 fd1cs fd1csd2 fd1q fd1qd2 fd1s fd1sd2 fd1sq fd1sqd2 fd2 fd2d2 fd2cs fd2csd2 fd2q fd2qd2 fd2s fd2sd2 fd2sq fd2sqd2 fd3 fd3d2 fd3cs fd3csd2 fd3q fd3qd2 fd3s fd3sd2 fd3sq fd3sqd2 fd4 fd4d2 fd4cs STDM110 STDM110 Output Pin Maximum Fanout Y CK CKB CK CKB S CO S CO S CO Q QN Q QN Q QN Q QN Q Q