AN2495 L6565 STC04IE170HV STEVAL-ISA019V1 PKC-136 230VAC 400VAC 1N4007 STTH108 - Datasheet Archive

 

Application note 80 W Very wide input voltage range 3-phase SMPS designed based on L6565 and ESBT STC04IE170HV Introduction The

 

AN2495 AN2495 Application note 80 W Very wide input voltage range 3-phase SMPS designed based on L6565 L6565 and ESBT STC04IE170HV STC04IE170HV Introduction The purpose of this application note is to explain the design of a 80 W 3-phase auxiliary power supply for Motor Drives and Welding Applications. To have a very good system in terms of both efficiency and cost, the L6565 L6565 PWM controller has been selected as well as the STC04IE170HV STC04IE170HV as the main switch. The combination of these ST parts is to target a highly efficient solution for high DC input voltage, a typical requirement of any three-phase application. The L6565 L6565 driver is a variable frequency PWM driver suitable to a design flyback converter working in Quasi-Resonant mode. It boasts some very interesting additional features. The study on the frequency response, reported in the present document, has been carried out using MATLAB. All the design choices are thoroughly discussed to allow the user to adapt the project to specific needs. The input voltage can also be extended up to 1000 V DC because there is enough margin to do so. Finally, the experimental results are analyzed to better understand the benefits given by the use of ESBT in this application. The document is associated with the release of the STEVAL-ISA019V1 STEVAL-ISA019V1 (see figure below). 80 W 3-phase SMPS (working prototype) June 2007 Rev 3 1/27 www.st.com Contents AN2495 AN2495 Contents 1 Design specifications and L6565 L6565 brief description . . . . . . . . . . . . . . . . 4 2 Flyback stage design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Transformer design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 Core size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 Transformer losses and air gap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.3 Wire size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Base driving circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Output circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Start-up network design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Frequency response and loop compensation . . . . . . . . . . . . . . . . . . . 16 7 Efficiency, waveforms and experimental results . . . . . . . . . . . . . . . . . 19 8 PCB layout and list of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2/27 AN2495 AN2495 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Flyback topology basic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Evaluation board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Dynamic magnetization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Relative core losses versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power transformer Tronic 0600387 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 The proportional driving schematic and its equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . 11 Current transformer SL 051 220 21 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Converter feedback network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stabilized open loop transfer function G(s) = G1(s) · G2(s) (Bode plots) . . . . . . . . . . . . . . 19 Overall efficiency versus output power for two different values of input voltage. . . . . . . . . 19 Minimum input voltage-maximum load (250 V-80 W) in steady state. . . . . . . . . . . . . . . . . 20 Medium input voltage-maximum load (500 V-80 W) in steady state . . . . . . . . . . . . . . . . . 20 Maximum input voltage-maximum load (850 V-80 W) in steady state . . . . . . . . . . . . . . . . 21 Very low load condition (750 V-5 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Low load condition (750 V-24 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 High load condition (750 V-80 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Proportional base driving circuit relevant waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PCB layout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PCB layout (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3/27 Design specifications and L6565 L6565 brief description 1 AN2495 AN2495 Design specifications and L6565 L6565 brief description Table 1 lists the converter specification data and the main parameters fixed for the demo board. Table 1. Converter specification data and fixed parameters Symbol Description Values Vinmin Rectified minimum Input voltage 250 Vinmax Rectified maximum Input voltage 850 Vout Output voltage 1 24 V/3.33 A Vaux Auxiliary output voltage 15 V/0.1 A Pout Maximum output Power 80 W h Converter efficiency > 80% F Minimum switching frequency 50 kHz Vspike Max over voltage limited by clamping circuit 200 V Figure 1 shows a simplified schematic diagram of a fly-back converter. L6565 L6565 has a current mode control and as already stated, is designed to build flyback converters working in quasi-resonant mode and ZVS (zero voltage switching) at turn-on or at least Quasi ZVS that means valley switching during turn-on. This condition allows the designer to reduce as much as possible the power losses at turn-on. Since the input range is from 250 V up to 850V, the ZVS is obtained only when Vin=Vinmin=Vfl=250 V. L6565 L6565 has 8 pin. For the detailed explanation of each pin function please refer to the L6565 L6565 datasheet. Figure 1. Flyback topology basic diagram PKC-136 PKC-136 4/27 1 2 1 2 230VAC 230VAC J2 400VAC 400VAC J1 D4 1N4007 1N4007 D3 1N4007 1N4007 FUSE F1 D2 1N4007 1N4007 D1 1N4007 1N4007 220n 1M1 10k R18 1M1 R10 1M1 R9 R4 200k R3 200k R2 200k C8 VCC R8 C2 + C1 + C12 1n 3V D9 STTH108 STTH108 D8 STTH108 STTH108 D7 0.56 R11 1.6 1/2W R16 2 4 T2 2 turns VCC 1.6 1/2W R17 R15 1k R12 10 + C6 470p C9 4 U1 L6565N L6565N 1N4148 1N4148 D11 2k2 R13 33u 50V 100n C5 STC04IE170HV STC04IE170HV Q1 VOGT SL0512202101 SL0512202101 1 4 13 STTH108 STTH108 3 turns 2 D10 R7 39k 2W C7 6.8n 2kV 1 3 220u 450V 220u 450V R6 39k 2W 10R R5 COMP CS VFF 3 R1 200k 7 OUT 8 VCC INV 1 Title 2 6 2n2 10p 12 13 14 Ns 8 9 10 ISO1 TRONIC 0600387 C11 C10 56k 5 7 Naux R14 1N4007 1N4007 D6 Np T1 4 PC817 PC817 3 5 ZCD GND 6 1 2 1 R19 TL431 TL431 3 U2 R21 15k C13 10n 3k3 47k 1k5 R23 C4 1000u 35V + R24 1000u 35V C3 STPS20120D STPS20120D D5 47k R20 2.7k R22 + 24VDC 24VDC 2 1 J3 Figure 2. 2 2 1 AN2495 AN2495 Flyback stage design Flyback stage design In Figure 2 the complete schematic of the 80 W SMPS is shown. Evaluation board schematic 5/27 Flyback stage design AN2495 AN2495 As commonly known, the voltage stress on the device (power switch) is given by: Equation 1 V off = V inmax ­ V fl ­ V spike where Vfl = flyback voltage = (Vout + VF, diode)*Np/Ns and Vspike is the maximum over voltage allowed by the clamping network. It has been fixed 200 V. Np is the number of turns on the primary side while Ns is the number of turns on the main output secondary winding. Now, taking into account a 200 V margin, the maximum flyback voltage that can be chosen is: Equation 2 V fl = BV ­ V inmax ­ V spike ­ V m arg in = 1700 ­ 1000 ­ 200 ­ 250 = 250V After calculating the flyback voltage, proceed with the next step in the converter design. The turn ratio between primary and secondary side is calculated with the following formula: Equation 3 V fl Np 250 - = - = - = 10 V out + V F, diode 24 + 1 Ns As a first approximation, since the turn-on of the device occurs immediately after the energy stored on the primary side inductance has been totally transferred to the secondary side: Equation 4 V dcmin T onmax = V fl T reset and Equation 5 T onmax + T reset = T S Where Tonmax is the maximum on time, Treset is the time needed to demagnetize the transformer inductance and TS is the switching time. Combining the two previous equations Tonmax results in: Equation 6 V fl · T S T onmax = - 10µs V dcmin + V fl The next step is to calculate the peak current. According to the converter specification of Table 1, output power of 80 W and desired efficiency (at least 80%), by using a formula that does not take into account the losses on the power switch, on the input bridge, and on the rectified network, we have: Equation 7 P IN 6/27 1 - · L P I P 2 2 = 1.25P OUT = - = TS 1 - V dcmin 2 T onmax 2 2 -LP TS AN2495 AN2495 Flyback stage design Hence Equation 8 2 2 V dcmin T onmax L P = - = 1.56mH 2.5T S P OUT From here now we can calculate the peak current on primary. Equation 9 V dcmin T onmax I P = - = 1.6A LP 2.1 Transformer design 2.1.1 Core size The core size has to be chosen according to the power that must be managed, the primary inductance, and the saturation current as well. An approximate but efficient formula could be used as a starting point. Eventually at the end, the designer may choose a bigger core and repeat the following steps. Equation 10 1.316 AP L P I rms ( primary ) = 10 -1 3 [cm4] -2 T · K u · B max Where: T is the maximum temperature variation with respect to the ambient temperature KU is the utilization factor of the window (say the portion of the window used for winding that generally ranges between 0.4 and 0.7) Bmax is the maximum flux in the core. From Equation 10, at the end an ETD34 ETD34 is the best choice. 2.1.2 Transformer losses and air gap From Faraday's law we can define the minimum primary winding turns to avoid saturation of the core. Looking at the saturation curve of the core, we can safely work up to 200 mT: Equation 11 V in, min · T O ( N, max ) 250 · 10µ N pmin = - = - = 117 B · A e 0.200 · 97µ 7/27 Flyback stage design Figure 3. AN2495 AN2495 Dynamic magnetization curves Concerning the gap, from the EPCOS datasheet, we can use the following approximate formula: Equation 12 1- AL K2 l g = gaplenght = - K 1 K1 = 153, K2 = -0.713, while AL has to be calculated. Knowing that Lp = 1.56mH and Np = 120, Equation 13 L P 1.56m A L = - = - = 108nH 2 2 120 N P 108 Hence: l g = gaplenght = - 153 Figure 4. 8/27 1 -­ 0.713 = 1.63mm Relative core losses versus frequency AN2495 AN2495 Flyback stage design From Figure 4, operating at 50 kHz with 220 mT flux excursion, the power dissipation density is about 300 mW/cm3. Once again, referring to the datasheet, the total volume of ETD 34 is 7.63 cm3, therefore: Equation 14 P core = 0.3 · 7.6 = 2.29W Assuming a 95% efficiency for the transformer, only 4 W can be lost on it, of which about 2.3 is lost on the core while the residual 1.7 W is dissipated on the copper. Achieving this efficiency is detailed in the following Section 2.1.3: Wire size. 2.1.3 Wire size To chose the right wire size we must know the rms current on both the primary and secondary side. Since I peak, primary = 1.6 A and I peak, secondary = 16 A, Equation 15 I rms, primary = 0.65A and I rms, sec ondary = 6.53A By imposing a 1 W loss on the primary side wire, the maximum series resistance can be calculated as follows: From the Joule law we can calculate the resistance of both the primary and secondary winding. Equation 16 P CU, sec R S = - R S = 0.016 2 I SRMS P CU, pri R P = - R P = 2.36 2 I PRMS From that, knowing the copper resistivity at 100 °C ( 100 = 2.303 10-6 cm), and the average wind length Lt (Lt = 5.6 cm), we can easily calculate the wire sections (in cm2). Equation 17 100 N p L t ­4 A PCU = - = 6.54 · 10 RP [ cm ] d p = 0.028 [ cm ] 100 N S L t A SCU = - = 0.0096 RS [ cm ] d s = 0.011 [ cm ] 2 Equation 18 2 From Table 2: Table 2. Skin effect AC/DC resistance ratios for square - wave currents 25 kHz Skin wire Diameter depth S, no. d, mils mils d/S 50 kHz Skin Rac/ depth S, Rdc mils 100 kHz 200 kHz d/S Rac/ Rdc Skin depth S, mils d/S Skin Rac/ depth S, Rdc mils d/S Rac/ Rdc 12 81.6 17.9 4.56 1.45 12.7 6.43 1.55 8.97 9.10 2.55 6.34 12.87 3.50 14 64.7 17.9 3.61 1.30 12.7 5.08 1.54 8.97 7.21 2.00 6.34 10.21 2.90 16 51.3 17.9 2.87 1.10 12.7 4.04 1.25 8.97 5.72 1.70 6.34 8.09 2.30 9/27 Flyback stage design Table 2. AN2495 AN2495 Skin effect AC/DC resistance ratios for square - wave currents (continued) 25 kHz Skin wire Diameter depth S, no. d, mils mils d/S 50 kHz Skin Rac/ depth S, Rdc mils 100 kHz 200 kHz d/S Rac/ Rdc Skin depth S, mils d/S Skin Rac/ depth S, Rdc mils d/S Rac/ Rdc 18 40.7 17.9 2.27 1.05 12.7 3.20 1.15 8.97 4.54 1.40 6.34 6.42 1.85 20 32.3 17.9 1.80 1.00 12.7 2.54 1.05 8.97 3.60 1.25 6.34 5.09 1.54 22 25.6 17.9 1.43 1.00 12.7 2.02 1.00 8.97 2.85 1.10 6.34 4.04 1.30 24 20.3 17.9 1.13 1.00 12.7 1.60 1.00 8.97 2.26 1.04 6.34 3.20 1.15 26 16.1 17.9 0.90 1.00 12.7 1.27 1.00 8.97 1.79 1.00 6.34 2.54 1.05 28 12.7 17.9 0.71 1.00 12.7 1.00 1.00 8.97 1.42 1.00 6.34 2.00 1.00 30 10.1 17.9 0.56 1.00 12.7 0.80 1.00 8.97 1.13 1.00 6.34 1.59 1.00 32 8.1 17.9 0.45 1.00 12.7 0.84 1.00 8.97 0.90 1.00 6.34 1.28 1.00 34 6.4 17.9 0.36 1.00 12.7 0.50 1.00 8.97 0.71 1.00 6.34 1.01 1.00 Note: To completely avoid the skin effect, the maximum diameter which is allowed is 20.3 mils which means 0.5 mm. For practical considerations and to better optimize the utilization of the transformer window and at the same time in accordance with Equation 15 to Equation 18 and Table 2, it can be determined that: Equation 19 d p = 0.028 [ cm ] d s = 0.05 [ cm ] 3 in parallel The specifications of the transformer provided by TRONIC according to the above calculations are shown in Figure 5. 10/27 AN2495 AN2495 Base driving circuit design Figure 5. Power transformer Tronic 0600387 Top view 3 Base driving circuit design In practical application, such as SMPS, where the load is variable, the collector current is variable as well. As a consequence it is very important to provide a base current to the device which is related to the collector. In this way it is possible to avoid device oversaturation at low load and to optimize the performance in terms of power dissipation. The best and simplest way to do this is the proportional driving method provided by current transformer, in Figure 6 At the same time, it is very useful to provide a short pulse to the base to make the turn-on as fast as possible and to reduce the dynamic saturation phenomenon. The pulse is achieved by using the capacitor and the zener in Figure 6. Figure 6. The proportional driving schematic and its equivalent circuit Lp Dz Ic Ic Cb LTp Rb IM Ip Is LTp Ib 11/27 Base driving circuit design AN2495 AN2495 The IC/IB ratio is fixed once the current transformer turn ratio has been chosen. From ESBT STC04DE170 STC04DE170 datasheet, and especially looking at the storage time characterization, it is clear that a turn ratio equal to 5 is a good value to ensure the right saturation of ESBT at Ic = 2 A, so that in the current transformer we can fix at first: Equation 20 NP - = 1 -NS 5 The core magnetic permeability of current transformer has to be as high as possible in order to minimize the magnetization current Im (that is not transferred to the secondary side but only drives the core into saturation). On the contrary, too high permeability core may lead the core into saturation even with a very small magnetization current. To avoid saturation, it is necessary to increase the number of primary turns and the size of the core as well. If a core with a very small magnetic permeability is chosen, it is possible to reduce the number of primary turns and the core size. If the permeability is too small, we may not have current on the secondary side because almost all the collector current becomes magnetization current. As a compromise, a ferrite material with a relative permeability in the range 4500 ÷ 7000 is the best choice. After selecting the ferrite ring diameter, the minimum primary turns is determined to avoid core saturation from the preliminarily fixed turn ratio N with 0.2. By applying Faraday's law and imposing the maximum flux Bmax equals to Bsat/2: Equation 21 V 1 · T onmax B d V 1 = N TP · - N TP · A e · - N TP = 2 · -T dt A e · B sat Where, Bsat is the saturation flux of the core which depends on the magnetic permeability. During the conduction time, the junction base-emitter of ESBT can be seen as a forward biased diode. To complete the secondary side load loop, the voltage drop on both diode D and resistor RB must be added in series with the base of the ESBT. The equivalent secondary side voltage source is given by: Equation 22 V S = V BEon ­ V D ­ V RB 2.5V Since the magnetization inductance cannot be neglected, only IP, a fraction of the total collector current, is transferred to the secondary. As a result, the magnetization current has to be first as low as possible. Meanwhile, the value of the magnetization inductance must be taken into account for the proper calculation of transformer primary turns and turns ratio. The magnetization voltage drop, that is, the voltage at the primary of the current transformer, can now be easily calculated: Equation 23 N 1T V 1 = V S · - = 2.5 · N 2T 1 - = 0.5 ( V ) 5 The magnetization current will be: Equation 24 V 1 T ONmax I Mmax = -L TP 12/27 AN2495 AN2495 Base driving circuit design The number of primary turns should be increased if IMmax is relatively high. The core must have window area large enough to hold all primary and secondary windings. Otherwise it is necessary to choose a bigger core size. Once both core material and size are fixed, the turn ratio must be adjusted to get the desiderated IC/IB ratio according to Equation 25 below: Equation 25 I P I Cmax ­ I Mmax N eff = - = -IB IC -5 where IMmax is the maximum magnetization current. The insulation between primary and secondary should be considered since the voltage on the primary side during the off time can surpass 1500 V. The next step is to select the zener diode, the capacitor Cb, and the resistor Rb. The turn-on performance of ESBT is related to the initial base peak current and its duration tpeak that is approximately given by Equation 26: Equation 26 t peak = 3R b C b A suitable value for Rb is 0.56 It can eliminate the ringing on the base current after the . peak, and at the same time, it generates negligible power dissipation. The value tpeak can be determined once the minimum on time is set based on the operation frequency. Bear in mind that in practical application, it should never be lower than 200ns. The value of Cb can be counted since the values of tpeak and Rb are known. Ipeak must be limited in order to avoid an extra saturation of the device. The zener diode Dz controls this and clamps the voltage across the small capacitor Cb. The zener must be chosen according to the following empiric formulas and inside the range of VZmin and VZmax: Equation 27 V Zmax = 2 ( I peak R b + 1 ) V Zmin = 2 ( I peak R b ) The base peak current is higher with higher clamp voltage (Dz) or smaller capacitance (Cb), which in turn will lead to shorter duration of the peak time. The higher and longer the base peak current is, the lower the power dissipation during turnon. The designer must limit the Ib peak both in terms of amplitude and time duration otherwise at low load a very high saturation level may result. If the device is oversaturated, the storage time is too long with higher power dissipation during turn-off. Moreover a long storage time can also lead to output oscillation especially at high input voltage. To overcome the above mentioned problems, it is suggested to set the peak duration to 1/3 the minimum duty cycle. Following all the formulas mentioned in this section applied to the present job gives: Equation 28 V 1 · T onmax N TP = 2 · - 2 A e · B sat where Ae is the magnetic area considering a ring core with 12.5 mm diameter and the saturation field Bsat is 400 mT. 13/27 Base driving circuit design AN2495 AN2495 From the first approximated assumption NS should be 10. From bench verification it's very simple to verify that the turn ratio to get the best trade-off between conduction and turn-off losses is 6. Of course, this verification and final decision has been taken after setting all the other components in the driving network and exactly: Equation 29 t peak = 3R b C c = 400ns = C b = 238nF = C b = 220nF (closet commercial value) Finally the zener has been set to 3 V. Figure 7 shows current transformer specifications: Figure 7. Current transformer SL 051 220 21 01 Section Bottom view 14/27 Equivalent schematic AN2495 AN2495 4 Output circuit design Output circuit design In order to choose the output capacitor, the series resistance of the electrolytic capacitor must be defined. It is well known that the main cause of the output ripple is the series resistance of the electrolytic capacitor, known as ESR, while the capacitive ripple is absolutely negligible. Therefore knowing the secondary side peak current is 16 A and imposing a resistive ripple equal to 2% (0.48 V), we have: Equation 30 V ripple 0.48 ESR < - = - = 0.03 16 I SP Using very low ESR output capacitances, from the catalogue we get the relation ESR*C=32e-6s from which: Equation 31 ­6 32 · 10 C out > - = 1066µF ESR To have some margin and to have a better thermal spread the final choice is to use two 680 µF capacitors in parallel. From the Kirchoff voltage law we can calculate the maximum voltage stress on the output diode: Equation 32 NS V off ­ diode = V out + - · V inmax = 109V NP Finally adding a 10% margin, the STPS20120D STPS20120D has been selected. 5 Start-up network design To allow the circuit to start as soon as the line voltage is applied, it is necessary to precharge both C5 and C8 capacitances. A resistor connected to the DC bus directly makes the pre-charge of C5 electrolytic capacitance. The circuit must start at a minimum DC input voltage of 250 V. The current required by L6565 L6565 driver during start-up time determines the (R1+ R2+ R3+ R4) value. Considering that L6565 L6565 driver needs a 0.07 mA maximum start-up current, we obtain: Equation 33 V inmin 250V ( R 1 + R 2 + R 3 + R 4 ) < - = - 3.6M I SU 0.07mA Start-up resistance must be lower than 3.6 M in order to reach the best trade-off between power dissipation and time-to-start. As a consequence, before choosing start-up resistor, 15/27 Frequency response and loop compensation AN2495 AN2495 we have to determine C5 capacitance value, which is set according to another requirement. C5 must be able to supply L6565 L6565 driver until the steady state behavior of the converter is established. The time from bench verification is 20 ms maximum. Being minimum hysteresis-voltage (difference between start-up threshold and under-voltage threshold) of L6565 L6565 3.7 V, the voltage across C5 has to decrease less than 3.7 V during the start-up period. From L6565 L6565 datasheet we know that maximum quiescent current after turn-on is 3.5 mA, then C5 must be chosen such that: Equation 34 I Q · t 3.5mA · 20ms V = - < 3.7V C 5 > - 19µF C5 3.7V C5=33 µF is a good choice in order to guarantee a good margin. Finally we can set the start-up resistance value in order to reduce time-to-start and contemporarily optimize standby power dissipation. The L6565 L6565 has a maximum start-up threshold of 14.5 V, therefore the maximum time-to-start is approximately: Equation 35 C 5 · 14.5V Time - to - start = - 2 sec ( R 1 + R 2 + R 3 + R 4 ) 808k V inmin - ­ I ( R 1 + R 2 + R 3 + R 4 ) SU A good choice is to put in series four 200 k resistances (R1= R2= R3= R4= 200 k), which dissipate less than 1 W standby power. The pre-charge of C8 base capacitance is made connecting it to the OUT pin of L6565 L6565 through a diode in series to a 2.2 k resistance. 6 Frequency response and loop compensation The transfer function in the complex frequency domain of the discontinuous current mode (DCM) flyback converter with L6565 L6565 driver is given by: Equation 36 L p D max ( 1 + s · C out · ESR ) 1 ­ s · - 2 2 n R out ( 1 ­ D max ) n · R out · ( 1 ­ D max ) V out ( s ) G 1 ( s ) = - = - · -V comp ( s ) 2 · R S · ( 1 + D max ) C out R out 1 + s · -1 + D max The parameters and values are listed in Table 3. Table 3. Transfer functions main parameters Parameter Value n Primary/secondary turn-ratio 10 RS Sensing resistor 0.8 Dmax 16/27 Description Maximum duty-cycle 0.5 AN2495 AN2495 Frequency response and loop compensation Table 3. Transfer functions main parameters (continued) Parameter Description Value ESR Electrolytic series resistance 16 m Rout=Vout/Iout Output load 7.2 Cout Output capacitance 2 mF Lp Primary inductance 1.56 mH It is worth noting that the transfer function has one pole and one zero on the left half plane and one more zero on the right half plane. The RHP zero is very difficult, if not impossible, to compensate and therefore must be kept well beyond the closed-loop bandwidth. As a result, the transient response of such system will not be extremely fast. Poles and zeros are given in Equation 37 and Equation 38: Equation 37 5 3 f p = 25Hz ;f Z1 = 3.5 · 10 Hz ;f Z2 = 5 · 10 Hz A good line and load regulation implies a high DC gain, thus the open loop gain should have a pole at the origin. Normally in this case we need a feedback network like the one in Figure 8. Figure 8. Converter feedback network Its transfer function, which comprises a pole at the origin and a zero-pole pair, is given by: Equation 38 v comp ( s ) CTR max · R COMP 1 1 + s ( R H + R F )C F - G 2 ( s ) = - = - · - · -s 1 + sR COMP C comp V out ( s ) RB RH CF The task of the control loop design is then to determine the transfer function G2(s) in order to ensure that the resulting closed-loop system is stable and performs well in terms of dynamic response, and line and load regulation. It is well known that the characteristics of the closed-loop system can be inferred from its open loop transfer function properties, that is G(s) = G1(s) · G2(s). 17/27 Frequency response and loop compensation AN2495 AN2495 Frequency response requirements are summarized below: 1. Optimum dynamic performance requires a large gain bandwidth, that is the open-loop cross-over frequency fc to be typically chosen equal to fsw/5 (fc = 10 khz). 2. Phase margin m comprised between 45° and 90° is used as a design guideline. This ensures fast transient response with very little ringing. Sometimes this is not enough and so phase shift should be lower than 180° at any frequency below fc, because a phase shift over 180° would result in a conditionally stable system. 3. Good load and line regulation implies a high DC gain (this requirement is ensured by the feedback network, whose transfer function has a pole at the origin). First choose a typical value for RL= R22= 2.7 k . From the L6565 L6565 datasheet we know that Icomp= 5 mA (source current) and Rcomp= 15 k . and can obtain: Equation 39 V out ­ ( V ref ­ V diode ) 24V ­ 3.5V R B = R 24 < - = - = 4.1k 5mA I comp R24= 1.5 k is a good choice. It is good practice to put a 3.3 k resistor (R23= 3.3 k) in parallel to the photodiode . The resistive partition has to be set with high precision according to the subsequent formula: Equation 40 V out ­ V ref R high = R 22 · - = 23.2k V ref There is no next closed commercial value so it is a good idea to put two 47 k resistances (R19 = R20 = 47 k) in series. Now C11 (Ccomp), C13 (CF) and R21 (RF) must be set in order to satisfy frequency response requirements. A good choice is to set the pole of G2(s) in order to cancel the low frequency zero of G1(s): Equation 41 1 - = 5kHz C 11 = C comp 2.12nF 2 · R comp · C comp The next close commercial value for C11= 2.2nF has been chosen. Similarly C13 and R21 have been determined by setting the corresponding zero close to the pole of G1(s) and imposing the open-loop gain to cross the 0 dB axis only once at f = fc = 10 kHz: Equation 42 1 - = 400Hz C = 10nF 13 2 · ( R H + R F ) · C F = 1 R 21 15k G ( j) ­4 = 2 · 10 rad/sec In such a way we ideally get a phase margin of 90 degrees and an adequate closed-loop bandwidth. Figure 9 shows Bode plots of the stabilized open loop transfer function. 18/27 AN2495 AN2495 Efficiency, waveforms and experimental results Figure 9. Stabilized open loop transfer function G(s) = G1(s) · G2(s) (Bode plots) As expected, all requirements have been satisfied by properly choosing the feedback network. Gain bandwidth is quite large, phase margin is around 90°, and system stability margin is improved. Efficiency, waveforms and experimental results Overall efficiency variation versus output power is illustrated in Figure 10 for two different values of input voltage. Figure 10. Overall efficiency versus output power for two different values of input voltage Efficiency versus output power 85 80 75 Efficiency (%) 7 70 Vin=250V Vin=850V 65 60 55 50 0 10 20 30 40 50 60 70 80 Output power (W) It is worth noting that with low input voltage (red curve), total efficiency is over 80% at medium and high load working conditions, reaching almost 85%. Efficiency decreases with 19/27 Efficiency, waveforms and experimental results AN2495 AN2495 input voltage, however it is above 75% at loads higher than 30% even with maximum input voltage. Theoretical assumptions made so far have been validated with the use of a demo board. A complete description of this board has been carried out and the most meaningful waveforms at any working condition are shown in Figure 11 through Figure 16. Figure 11, Figure 12 and Figure 13 show the prototype steady state behavior, by indicating the gate voltage (blue waveform), the base current (violet waveform) and the collector voltage (sky blue waveform) at maximum load for different input voltages. Figure 11. Minimum input voltage-maximum load (250 V-80 W) in steady state Figure 12. Medium input voltage-maximum load (500 V-80 W) in steady state 20/27 AN2495 AN2495 Efficiency, waveforms and experimental results Figure 13. Maximum input voltage-maximum load (850 V-80 W) in steady state Waveforms in Figure 14, Figure 15, and Figure 16 describe the function of the converter at both low and high load conditions with the same input rectified voltage. Figure 14. Very low load condition (750 V-5 W) Figure 15. Low load condition (750 V-24 W) 21/27 Efficiency, waveforms and experimental results AN2495 AN2495 Figure 16. High load condition (750 V-80 W) The waveform in Figure 17 illustrates the function of the proportional base driving network. In this graph, collector current is in violet while base current is in sky blue. Figure 17. Proportional base driving circuit relevant waveform 22/27 AN2495 AN2495 8 PCB layout and list of material PCB layout and list of material The printed circuit board is shown in Figure 18 and Figure 19. Figure 18. PCB layout (top view) Figure 19. PCB layout (bottom view) 23/27 Bill of material 9 AN2495 AN2495 Bill of material The bill of material is listed in Table 4. Table 4. Bill of material Part C1,C2 220 µF/450 F/450 V C3,C4 1000 µF/35 V C5 33 µF/50 V C6 100 nF C7 6n8 C8 220 n C9 470 pF C10 10 pF C11 2n2 C12 1 nF C13 10 n D1,D2,D3,D4 1N4007 1N4007 D5 STPS20120D STPS20120D D6 1N4007 1N4007 D7,D8,D10 STTH108 STTH108 D9 3VZener D11 1N4148 1N4148 R1, R2, R3, R4 200 k/0.25 W R5 10 R/0.25 W R6, R7 39 k/2 W R8, R9, R10 1M1/0.25 W R11 0.56 R/1 W R12 10 R/0.25 W R13 2k2/0.25 W R14 56k/0.25W R15 1k/0.25 W R16, R17 1 R6/1W R18 10 k/0.25W R19, R20 47 k/0.25 W R21 15 k/0.25 W R22 24/27 Description 2k7/0.25 W AN2495 AN2495 References Table 4. Bill of material (continued) Part R23 3k3/0.25 W R24 1k5/0.25 W Q1 STC04IE170HV STC04IE170HV J1, J2 ARK700I/2 ARK700I/2 J3 ARK500/2 ARK500/2 U1 L6565 L6565 U2 TL431 TL431 ISO1 PC817 PC817 F1 FUSE 2 A / 250 V FUSE HOLDER HA122100 HA122100, RM = 10 mm T1 TRONIC 0600387 T2 VOGT SL0512202101 SL0512202101 het1, het2 10 Description V7477X V7477X References STMicroelectronics application note AN1889 AN1889 "ESBT STC03DE120 STC03DE120 IN 3-PHASE AUXILIARY POWER SUPPLY" STMicroelectronics application note AN1262 AN1262 "OFFLINE FLYBACK CONVERTERS DESIGN METHODOLOGY WITH THE L6590 L6590 FAMILY" STMicroelectronics application note AN2131 AN2131 "HIGH POWER 3-PHASE AUXILIARY POWER SUPPLY DESIGN BASED ON L5991 L5991 AND ESBT STC08DE150 STC08DE150" STMicroelectronics L6565 L6565 datasheet "QUASI-RESONANT SMPS CONTROLLER" STMicroelectronics STC04IE170HV STC04IE170HV datasheet "Emitter switched bipolar transistor ESBT® 1700 V - 4A - 0.17 " Abraham I.Pressman, "Switching Power Supply Design", McGraw-Hill, Inc. 25/27 Revision history 11 AN2495 AN2495 Revision history Table 5. Revision history Date 28-Mar-2007 1 First issue 10-Apr-2007 2 Equation 5 and Equation 15 modified 20-Jun-2007 26/27 Revision Changes 3 ESBT part number has been updated AN2495 AN2495 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 27/27