ST92141 8/16-BIT PSDIP32 CSDIP32W ST92E141 ST92T141 PSDIP32/ PSDIP32/CSDIP32W - Datasheet Archive

 

8/16-BIT MCU FOR 3-PHASE AC MOTOR CONTROL PRODUCT PREVIEW s s s s s s s s s s s s s s s s s s s s Register File based 8/16 bit

 

ST92141 ST92141 8/16-BIT 8/16-BIT MCU FOR 3-PHASE AC MOTOR CONTROL PRODUCT PREVIEW s s s s s s s s s s s s s s s s s s s s Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW, HALT and STOP modes 0-25 MHz Operation (internal clock) @ 5V±10% voltage range -40°C to +85°C Operating Temperature Range Fully Programmable PLL Clock Generator, with Frequency Multiplication and low frequency, low cost external crystal (3-5 MHz) Minimum Instruction Cycle time: 160 ns - (@ 25 MHz internal clock frequency) Internal Memory: ­ EPROM/OTP/ROM 16K bytes ­ RAM 512 bytes 224 general purpose registers available as RAM, accumulators or index pointers (register file) 32-pin Dual Inline and 34-pin Small Outline Packages 15 programmable I/O pins with Schmitt Trigger input, including 4 high sink outputs (20mA @ VOL=3V) 4 Wake-up Interrupts (one usable as NonMaskable Interrupt) for emergency event management 3-phase Induction Motor Controller (IMC) Peripheral with 3 pairs of PWM outputs and asynchronous emergency stop Serial Peripheral Interface (SPI) with Master/ Slave Mode capability 16-bit Timer with 8-bit Prescaler usable as a Watchdog Timer 16-bit Standard Timer with 8-bit Prescaler 16-bit Extended Function Timer with Prescaler, 2 Input Captures and 2 Output Compares 8-bit Analog to Digital Converter allowing up to 6 input channels with autoscan and watchdog capability Low Voltage Detector Reset Rich Instruction Set with 14 Addressing Modes Division-by-Zero trap generation Versatile Development Tools, including Assembler, Linker, C-compiler, Archiver, Source Level Debugger and Hardware Emulators with Real-Time Operating System available from Third Parties PSDIP32 PSDIP32 SO34 Shrink CSDIP32W CSDIP32W DEVICE SUMMARY DEVICE Program Memory (Bytes) RAM (Bytes) ST92141 ST92141 16K ROM 512 ST92E141 ST92E141 16K EPROM 512 ST92T141 ST92T141 16K OTP 512 PACKAGE PSDIP32/ PSDIP32/ SO34 CSDIP32W CSDIP32W PSDIP32/ PSDIP32/ SO34 Rev. 1.4 June 2000 1/178 This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice. 9 Table of Contents 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.1 ST9+ Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.2 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.3 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.4 Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.5 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.6 3-phase Induction Motor Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.7 Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.8 Standard Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.9 Extended Function Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.10 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.11 Analog/Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.1 I/O Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.2 I/O Port Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.3.1 Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.3.2 EPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4 REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 DEVICE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 CORE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.1 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.2 Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 SYSTEM REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.1 Central Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.2 Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.3 Register Pointing Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.4 Paged Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.5 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.6 Stack Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.5 MEMORY MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.6 ADDRESS SPACE EXTENSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.6.1 Addressing 16-Kbyte Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.6.2 Addressing 64-Kbyte Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.7 MMU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.7.1 DPR[3:0]: Data Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.7.2 CSR: Code Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.7.3 ISR: Interrupt Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.7.4 DMASR: DMA Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.8 MMU USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.8.1 Normal Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.8.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.8.3 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178. 38 . 2/178 1 Table of Contents 3 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 INTERRUPT VECTORING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Divide by Zero trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Segment Paging During Interrupt Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 INTERRUPT PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 PRIORITY LEVEL ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Priority level 7 (Lowest) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Maximum depth of nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Simultaneous Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Dynamic Priority Level Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 ARBITRATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Concurrent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 TOP LEVEL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 ON-CHIP PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 NMI/WKP0 LINE MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.1 NMI/Wake-Up Event Handling in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.2 NMI/Wake-Up Event Handling in STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.3 Unused Wake Up Management Unit lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 INTERRUPT RESPONSE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 INTERRUPT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU) . . . . . . . . . . . . . . . . . . 3.12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.4 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 EM CONFIGURATION REGISTERS (EM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 RESET AND CLOCK CONTROL UNIT (RCCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 CLOCK CONTROL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Clock Control Unit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 PLL Clock Multiplier Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 CPU Clock Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 Peripheral Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.5 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 CLOCK CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 RESET/STOP MANAGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 Reset Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 39 39 39 40 40 40 40 40 40 41 41 41 44 46 48 48 49 50 50 50 51 52 55 55 55 56 57 59 62 63 63 63 63 65 66 66 66 67 67 69 73 74 75 76 78 3/178 Table of Contents 6 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2 SPECIFIC PORT CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3 PORT CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4 INPUT/OUTPUT BIT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.5 ALTERNATE FUNCTION ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.5.1 Pin Declared as I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.5.2 Pin Declared as an Alternate Function Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.5.3 Pin Declared as an Alternate Function Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.6 I/O STATUS AFTER WFI, HALT AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.1 TIMER/WATCHDOG (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.1.3 Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.1.4 WDT Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.1.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.2 STANDARD TIMER (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.2.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2.3 Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.2.4 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.2.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.3 EXTENDED FUNCTION TIMER (EFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.3.4 Interrupt Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.3.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.4 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.4.4 Tacho Counter Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.4.5 IMC Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.4.6 IMC Output selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.4.7 NMI management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 7.4.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 7.5.5 Interrupt Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7.5.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 178 4/178 Table of Contents 7.6 ANALOG TO DIGITAL CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 147 148 150 151 156 174 174 176 176 5/178 ST92141 ST92141 - GENERAL DESCRIPTION 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST92141 ST92141 microcontroller is developed and manufactured by STMicroelectronics using a proprietary n-well HCMOS process. Its performance derives from the use of a flexible 256-register programming model for ultra-fast context switching and real-time event response. The intelligent onchip peripherals offload the ST9 core from I/O and data management processing tasks allowing critical application tasks to get the maximum use of core resources. The new-generation ST9 MCU devices now also support low power consumption and low voltage operation for power-efficient and low-cost embedded systems. 1.1.1 ST9+ Core The advanced Core consists of the Central Processing Unit (CPU), the Register File, the Interrupt controller, and the Memory Management Unit. The MMU allows addressing of up to 4 Megabytes of program and data mapped into a single linear space. Four independent buses are controlled by the Core: a 16-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit interrupt bus which connects the interrupt controllers in the on-chip peripherals with the core. Note: The DMA features of the ST9+ core are not used by the on-chip peripherals of the ST92141 ST92141. This multiple bus architecture makes the ST9 family devices highly efficient for accessing on and offchip memory and fast exchange of data with the on-chip peripherals. The general-purpose registers can be used as accumulators, index registers, or address pointers. Adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory/register and memory/memory exchanges. 1.1.2 Power Saving Modes To optimize performance versus power consumption, a range of operating modes can be dynamically selected by software according to the requirements of the application. Run Mode. This is the full speed execution mode with CPU and peripherals running at the maximum clock speed delivered either by the Phase Locked Loop controlled by the RCCU (Reset and Clock Control Unit), directly by the oscillator or by an ex- 6/178 9 ternal source (dedicated Pin or Alternate Function). Slow Mode. Power consumption can be significantly reduced by running the CPU and the peripherals at reduced clock speed using the CPU Prescaler and RCCU Clock Divider. Wait For Interrupt Mode. The Wait For Interrupt (WFI) instruction suspends program execution until an interrupt request is acknowledged. During WFI, the CPU clock is halted while the peripheral with interrupt capability and interrupt controller are kept running at a frequency that can be programmed by software in the RCCU registers. In this mode, the power consumption of the device can be reduced by more than 95% (Low Power WFI). Halt Mode. When executing the HALT instruction, and if the Watchdog is not enabled, the CPU and its peripherals stop operating. If however the Watchdog is enabled, the HALT instruction has no effect. The main difference between Halt mode and Stop mode is that a reset is necessary to exit from Halt mode which causes the system to be reinitialized. Stop Mode. When Stop mode is requested by executing the STOP sequence (see Wake-up Management Unit section), the CPU and the peripherals stop operating. Operations resume after a wake-up line is activated. The difference between Stop mode and Halt mode is in the way the CPU exits each state: when the STOP sequence is executed, the status of the registers is recorded, and when the system exits from Stop mode the CPU continues execution with the same status, without a system reset. The Watchdog counter, if enabled, is stopped. After exiting Stop mode it restarts counting from where it left off. When the MCU exits from STOP mode, the oscillator, which was also sleeping, requires a start-up time to restart working properly. An internal counter is present to guarantee that, after exiting Stop Mode, all operations take place with the clock stabilised. 1.1.3 System Clock A programmable PLL Clock Generator allows standard 3 to 5 MHz crystals to be used to obtain a large range of internal frequencies up to 25MHz. ST92141 ST92141 - GENERAL DESCRIPTION 1.1.4 Low Voltage Reset The on-chip Low Voltage Detector (LVD) generates a static reset when the supply voltage is below a reference value. The LVD works both during power-on as well as when the power supply drops (brown-out). The reference value for the voltage drop is lower than the reference value for poweron in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). 1.1.5 I/O Ports The I/O lines are grouped into two I/O Ports and can be configured on a bit basis to provide timing, status signals, an address/data bus for timer inputs and outputs, analog inputs, external wake-up lines and serial or parallel I/O. 1.1.6 3-phase Induction Motor Controller The IMC controller is designed for variable speed motor control applications. Three pairs of PWM outputs are available for controlling a three-phase motor drive. Rotor speed feedback is provided by capturing a tachogenerator input signal. Emergency stop is provided by putting the PWM outputs in high impedance mode upon asynchronous faulty event on NMI pin. 1.1.7 Watchdog Timer (WDT) The Watchdog timer can be used to monitor system integrity. When enabled, it generates a reset after a timeout period unless the counter is refreshed by the application software. For additional security, watchdog function can be enabled by hardware using a specific pin. 1.1.8 Standard Timer The standard timer includes a programmable 16bit down-counter and an associated 8-bit prescaler with Single and Continuous counting modes. 1.1.9 Extended Function Timer The Extended Function Timer can be used for a wide range of standard timing tasks. It has a 16-bit free running counter with programmable prescaler. Each timer can have up to 2 input capture and 2 output compare pins with associated registers. This allows applications to measure pulse intervals or generate pulse waveforms. Timer overflow and other events are flagged in a status register with optional interrupt generation. 1.1.10 Serial Peripheral Interface (SPI) The SPI bus is used to communicate with external devices via the SPI, or I²C bus communication standards. 1.1.11 Analog/Digital Converter (ADC) The ADC provides up to 6 analog inputs with onchip sample and hold. The analog watchdog generates an interrupt when the input voltage moves out of a preset threshold. 7/178 9 ST92141 ST92141 - GENERAL DESCRIPTION Figure 1. ST92141 ST92141 Block Diagram RAM 512 bytes Register File 256 bytes I/Os WATCHDOG 8/16-bit CPU Interrupt Management ST9+ CORE OSCIN OSCOUT RESET INTCLK CK_AF Fully Prog. RCCU + LVD REGISTER BUS NMI WKUP[3:0] INT0 INT6 MEMORY BUS EPROM/ROM 16K SPI A/D Converter with analog watchdog IMC ICAP1 OCMP1 ICAP2 OCMP2 EXTCLK EF TIMER STIN STOUT STIM TIMER All alternate functions (Italic characters) are mapped on Port3 and Port5 8/178 9 P3[6:0] P5[7:0] WDIN WDOUT MISO MOSI SCK SSN AIN[7:2] EXTRG TACHO UH UL VH VL WH WL ST92141 ST92141 - GENERAL DESCRIPTION 1.2 PIN DESCRIPTION 1 32 ST92E141 ST92E141 VDD MOSI/P3.0 MISO/P3.1 SCK/STIN/WKUP3/P3.2 STOUT/SSN/P3.3 EXTRG/OCMP2/P3.4 INT6/OCMP1/P3.5 ICAP1/WKUP2/P3.6 AVDD AVSS INTCLK/AIN7/P5.7 CK_AF/AIN6/P5.6 AIN5/P5.5 AIN4/P5.4 AIN3/EXTCLK/WDOUT/P5.3 AIN2/INT0/WDIN/P5.2 17 16 VSS TACHO VH VL WH WL UH UL VPP P5.0/WKUP1/ICAP2 P5.1/NMI/WKUP0 RESET OSCOUT OSCIN VSS VDD PSDIP32/CSDIP32W PSDIP32/CSDIP32W Package 1 34 ST92E141 ST92E141 VDD MOSI/P3.0 MISO/P3.1 SCK/STIN/WKUP3/P3.2 STOUT/SSN/P3.3 EXTRG/OCMP2/P3.4 INT6/OCMP1/P3.5 ICAP1/WKUP2/P3.6 N.C. AVDD AVSS INTCLK/AIN7/P5.7 CK_AF/AIN6/P5.6 AIN5/P5.5 AIN4/P5.4 AIN3/EXTCLK/WDOUT/P5.3 AIN2/INT0/WDIN/P5.2 17 18 VSS TACHO VH VL WH WL UH UL N.C. VPP P5.0/WKUP1/ICAP2 P5.1/NMI/WKUP0 RESET OSCOUT OSCIN VSS VDD SO34 Package 9/178 9 ST92141 ST92141 - GENERAL DESCRIPTION Function SO34 Name SDIP32 SDIP32 SO34 Table 2. Primary Function pins SDIP32 SDIP32 Table 1. Power Supply Pins VPP Programming voltage for EPROM/OTP devices. Must be connected to VSS in user mode. 24 25 TACHO Signal input from a tachogenerator to the IMC controller for 31 measuring the rotor speed 33 VDD Main power supply voltage (5V ± 17 10% (2 pins internally connected) 1 18 UH U-phase PWM output signal 26 28 1 VH V-phase PWM output signal 30 32 18 19 WH W-phase PWM output signal 28 30 32 34 UL 27 9 10 The complemented UH, VH, WH 25 output signals with added dead 29 time to avoid crossover conduc27 tion from the power driver Name VSS Digital Circuit Ground (2 pins internally connected) AVDD Analog VDD of the Analog to Digital Converter AVSS Analog VSS of the Analog to Digit10 al Converter VL WL 11 Function 31 29 RESET 22 OSCIN is the input of the oscillator inverter and internal clock generator. OSCIN and OSCOUT connect a parallel-resonant crys- 19 tal (3 to 5 MHz), or an external source to the on-chip clock oscillator and buffer 20 OSCOUT 9 21 OSCIN 10/178 Reset (input, active low). The ST9+ is initialised by the Reset signal. With the deactivation of RESET, program execution begins from the memory location pointed to by the vector contained in memory locations 00h and 01h OSCOUT is the output of the os20 cillator inverter 21 ST92141 ST92141 - GENERAL DESCRIPTION 1.2.1 I/O Port Configuration All ports can be individually configured as input, bidirectional, output, or alternate function. Refer to the Port Bit Configuration Table in the I/O Port Chapter. All I/Os are implemented with a High Hysteresis or Standard Hysteresis Schmitt trigger function (See Electrical Characteristics). Weak Pull-Up = This column indicates if a weak pull-up is present or not (refer to Table 3). ­ If WPU = yes, then the WPU can be enabled/disable by software ­ If WPU = no, then enabling the WPU by software has no effect All port output configurations can be software selected on a bit basis to provide push-pull or open drain driving capabilities. For all ports, when configured as open-drain, the voltage on the pin must never exceed the VDD power line value (refer to Electrical characteristics section). 1.2.2 I/O Port Reset State I/Os are reset asynchronously as soon as the RESET pin is asserted low. All I/Os are forced by the Reset in "floating input" configuration mode. WARNING When a common pin is declared to be connected to an alternate function input and to an alternate function output, the user must be aware of the fact that the alternate function output signal always inputs to the alternate function module declared as input. When any given pin is declared to be connected to a digital alternate function input, the user must be aware of the fact that the alternate function input is always connected to the pin. When a given pin is declared to be connected to an analog alternate function input (ADC input for example) and if this pin is programmed in the "AF-OD" mode, the digital input path is disconnected from the pin to prevent any DC consumption. Table 3. I/O Port Characteristics Input Port 3[4:0] Schmitt trigger (High Hysteresis) Output Push-Pull/OD Port 3[6:5] Schmitt trigger (High Hysteresis) Port 5.0 Schmitt trigger (High Hysteresis) Push-Pull/OD (HC) Yes Push-Pull/OD (HC) Yes Floating input Floating input Port 5.1 Schmitt trigger (High Hysteresis) Push-Pull/OD Yes Floating input Port 5.2 Schmitt trigger (Standard Hysteresis) Push-Pull/OD (HC) Yes Floating input Push-Pull/OD Floating input Port 5[7:3] Schmitt trigger (Standard Hysteresis) Weak Pull-Up Reset State Yes Floating input Yes Legend: OD = Open Drain; HC= High current 11/178 9 ST92141 ST92141 - GENERAL DESCRIPTION Table 4. ST92141 ST92141 Alternate functions Port Name General Purpose I/O Pin No. Alternate Functions SDIP32 SDIP32 PSO34 PSO34 P3.0 2 2 P3.1 3 3 MOSI I/O SPI Master Output/Slave Input Data MISO I/O SPI Master Input/Slave Output Data WKUP3 P3.2 4 4 I Wake-up line 3 STIN I Standard Timer Input SCK P3.3 5 5 P3.4 6 6 P3.5 7 7 P3.6 8 8 23 24 22 23 16 17 All ports useable for general purpose I/O (input, output or bidirectional) I/O SPI Serial Clock Input/Output SSN I SPI Slave Select STOUT O Standard Timer Output EXTRG I A/D External trigger OCPM2 O Ext. Timer Output Compare 2 INT6 I External Interrupt 6 OCMP1 O Ext. Timer - Output Compare 1 ICAP1 I Ext. Timer - Input Capture 1 WKUP2 I Wake-up line 2 Ext. Timer - Input Capture 2 I Wake-up line 1 NMI I Not maskable Int. WKUP0 I Wake-up line 0 I Analog Data Input 2 INT0 I External Interrupt 0 I Watchdog input AIN3 P5.2 I WKUP1 WDIN P5.1 ICAP2 AIN2 P5.0 I Analog Data Input 3 15 16 EXTCLK I Ext. Timer - Input Clock WDOUT P5.3 O Watchdog Output P5.4 14 15 AIN4 I Analog Data Input 4 P5.5 13 14 AIN5 I Analog Data Input 5 P5.6 12 13 AIN6 I Analog Data Input 6 CK_AF I Clock Alternative Source P5.7 11 12 AIN7 I Analog Data Input 7 INTCLK O Internal Main Clock How to configure the I/O ports To configure the I/O ports, use the information in Table 3 and Table 4 and the Port Bit Configuration Table in the I/O Ports Chapter on page 81. I/O note = The hardware characteristics fixed for each port line in Table 3. All I/O inputs have Schmitt trigger fixed by hardware so selecting CMOS or TTL input by software 12/178 9 has no effect, the input will always be Schmitt Trigger. In particular, the Schmitt Triggers present on the P5[7:2] pins have a standard hysteresis whereas the remaining pins have Schmitt Triggers with High Hysteresis (refer to Electrical Specifications). Alternate Functions (AF) = More than one AF cannot be assigned to an external pin at the same time: ST92141 ST92141 - GENERAL DESCRIPTION An alternate function can be selected as follows. AF Inputs: ­ AF is selected implicitly by enabling the corresponding peripheral. Exceptions to this are ADC analog inputs which must be explicitly selected as AF by software. AF Outputs or Bidirectional Lines: ­ In the case of Outputs or I/Os, AF is selected explicitly by software. Example 1: Standard Timer input AF: STIN, Port: P3.2, I/O Note: Schmitt trigger. Write the port configuration bits: P3C2.2=1 P3C1.2=0 P3C0.2=1 or P3C2.2=0 P3C1.2=0 P3C0.2=1 Enable the Standard Timer input by software as described in the STIM chapter. Example 2: Standard Timer output AF: STOUT, Port: P3.3 Write the port configuration bits (for AF output push-pull): P3C2.3=0 P3C1.3=1 P3C0.3=1 Example 3: ADC analog input AF: AIN2, Port: P5.2, I/O Note: does not apply to analog inputs Write the port configuration bits: P5C2.2=1 P5C1.2=1 P5C0.2=1 13/178 9 ST92141 ST92141 - GENERAL DESCRIPTION 1.3 MEMORY MAP 1.3.1 Memory Configuration The Program memory space of the ST92141 ST92141, 16K bytes of directly addressable on-chip memory, is fully available to the user. The first 256 memory locations from address 0 to FFh hold the Reset Vector, the Top-Level (Pseudo Non-Maskable) interrupt, the Divide by Zero Trap Routine vector and, optionally, the interrupt vector table for use with the on-chip peripherals and the external interrupt sources. Apart from this case no other part of the Program memory has a predetermined function except segment 21h which is reserved for use by STMicroelectronics. 1.3.2 EPROM Programming The 16K bytes of EPROM memory of the ST92E141 ST92E141 may be programmed by using the EPROM Programming Boards (EPB) or gang programmers available from STMicroelectronics. EPROM Erasing The EPROM of the windowed package of the ST92E141 ST92E141 may be erased by exposure to Ultra-Violet light. The erasure characteristic of the ST92E141 ST92E141 is such that erasure begins when the memory is exposed to light with a wave lengths shorter than approximately 4000Å. It should be noted that sunlight and some types of fluorescent lamps have wavelengths in the range 3000-4000Å. It is thus recommended that the window of the ST92E141 ST92E141 packages be covered by an opaque label to prevent unintentional erasure problems when testing the application in such an environment. The recommended erasure procedure of the EPROM is the exposure to short wave ultraviolet light which have a wave-length 2537Å. The integrated dose (i.e. U.V. intensity x exposure time) for erasure should be a minimum of 15W-sec/cm2. The erasure time with this dosage is approximately 30 minutes using an ultraviolet lamp with 12000mW/cm2 power rating. The ST92E141 ST92E141 should be placed within 2.5cm (1 inch) of the lamp tubes during erasure. Table 5. First 6 Bytes of Program Space 0 1 2 3 4 5 Address high of Power on Reset routine Address low of Power on Reset routine Address high of Divide by zero trap Subroutine Address low of Divide by zero trap Subroutine Address high of Top Level Interrupt routine Address low of Top Level Interrupt routine Figure 2. Memory Map 220000h 21FFFFh SEGMENT 21h 64 Kbytes Reserved Reserved 210000h 20FFFFh PAGE 83 - 16 Kbytes 20C000h 20BFFFh 200200h Internal RAM 512 bytes SEGMENT 20h 64 Kbytes Reserved PAGE 82 - 16 Kbytes 208000h 207FFFh Reserved PAGE 81 - 16 Kbytes 204000h 203FFFh PAGE 80 - 16 Kbytes 200000h 200000h 00FFFFh PAGE 3 - 16 Kbytes 00C000h 00BFFFh SEGMENT 0 64 Kbytes Internal ROM max. 64 Kbytes PAGE 2 - 16 Kbytes 008000h 007FFFh PAGE 1 - 16 Kbytes ROM/EPROM 9 004000h 003FFFh 16 Kbytes 14/178 004000h 003FFFh 000000h 000000h PAGE 0 - 16 Kbytes ST92141 ST92141 - GENERAL DESCRIPTION 1.4 REGISTER MAP The following pages contain a list of ST92141 ST92141 registers, grouped by peripheral or function. Be very careful to correctly program both: ­ The set of registers dedicated to a particular function or peripheral. ­ Registers common to other functions. ­ In particular, double-check that any registers with "undefined" reset values have been correctly initialised. WARNING: Note that in the EIVR and each IVR register, all bits are significant. Take care when defining base vector addresses that entries in the Interrupt Vector table do not overlap. Table 6. Common Registers Function or Peripheral Common Registers ADC CICR + NICR + I/O PORT REGISTERS WDT CICR + NICR + EXTERNAL INTERRUPT REGISTERS + I/O PORT REGISTERS I/O PORTS EXTERNAL INTERRUPT RCCU I/O PORT REGISTERS + MODER INTERRUPT REGISTERS + I/O PORT REGISTERS INTERRUPT REGISTERS + MODER 15/178 9 ST92141 ST92141 - GENERAL DESCRIPTION Table 7. Group F Pages Resources available on the ST92141 ST92141 devices: Register Page 0 7 11 21 28 48 51 55 57 63 Res. PORT 3 R253 R252 3 Res. R255 R254 2 Res. WU WCR IMC Res. R251 Res. R250 WDT Res. Res. R249 MMU R248 EFT0 R247 R246 Res. R245 R244 A/D0 IMC Res. EXT INT RCCU EM PORT 5 Res. Res. R243 R242 MMU Res. SPI0 RCCU STIM0 Res. R241 Res. R240 16/178 9 RCCU Res. ST92141 ST92141 - GENERAL DESCRIPTION Table 8. Detailed Register Map Reset Value Hex. Doc. Page CICR Central Interrupt Control Register 87 52 FLAGR Flag Register 00 24 RP0 Pointer 0 Register xx 26 R233 RP1 Pointer 1 Register xx 26 R234 PPR Page Pointer Register xx 28 R235 MODER Mode Register E0 28 R236 USPHR User Stack Pointer High Register xx 30 R237 USPLR User Stack Pointer Low Register xx 30 R238 SSPHR System Stack Pointer High Reg. xx 30 R239 N/A Description R232 Core Register Name R231 (Decimal) Block Reg. No. R230 Page SSPLR System Stack Pointer Low Reg. xx 30 R224 P0DR Port 0 Data Register FF I/O R225 P1DR Port 1 Data Register FF Port R226 P2DR Port 2 Data Register FF 5:4,2:0 R228 P4DR Port 4 Data Register FF R229 P5DR Port 5 Data Register FF R242 EITR External Interrupt Trigger Register 00 52 R243 EIPR External Interrupt Pending Reg. 00 53 79 R244 EIMR External Interrupt Mask-bit Reg. 00 53 R245 EIPLR External Interrupt Priority Level Reg. FF 53 R246 INT EIVR External Interrupt Vector Register x6 54 R247 NICR Nested Interrupt Control 00 54 R248 0 WDTHR Watchdog Timer High Register FF 90 R249 WDTLR Watchdog Timer Low Register FF 90 R250 WDTPR Watchdog Timer Prescaler Reg. FF 90 R251 WDTCR Watchdog Timer Control Register 12 90 R252 WDT WCR Wait Control Register 7F 91 I/O 00 Port 3 Configuration Register 1 00 R254 P3C2 Port 3 Configuration Register 2 00 R244 P5C0 Port 5 Configuration Register 0 FF Port R245 P5C1 Port 5 Configuration Register 1 00 R246 P5C2 Port 5 Configuration Register 2 00 R240 SPDR SPI Data Register 00 145 R241 SPCR SPI Control Register 00 145 R242 SPSR SPI Status Register 00 146 R243 SPPR SPI Prescaler Register 00 146 R240 11 Port 3 Configuration Register 0 P3C1 5 7 P3C0 R253 I/O 3 R252 Port 3 2 STH Counter High Byte Register FF 95 R241 STL Counter Low Byte Register FF 95 R242 STP Standard Timer Prescaler Register FF 95 R243 STC Standard Timer Control Register 14 95 SPI STIM 79 17/178 9 ST92141 ST92141 - GENERAL DESCRIPTION Doc. Page DPR0 Data Page Register 0 xx 35 DPR1 Data Page Register 1 xx 35 DPR2 Data Page Register 2 xx 35 R243 DPR3 Data Page Register 3 xx 35 CSR Code Segment Register 00 36 R248 ISR Interrupt Segment Register xx 36 R249 EM Reset Value Hex. R244 MMU Description R242 21 Register Name R241 (Decimal) Block Reg. No. R240 Page DMASR DMA Segment Register xx 36 R245 EMR1 EM Register 1 80 62 R246 EMR2 EM Register 2 0F 62 R240 IC1HR Input Capture 1 High Register xx 108 R241 xx 108 Input Capture 2 High Register xx 108 IC2LR Input Capture 2 Low Register xx 108 R244 CHR Counter High Register FF 109 R245 CLR Counter Low Register FC 109 R246 EFT Input Capture 1 Low Register IC2HR R243 28 IC1LR R242 ACHR Alternate Counter High Register FF 109 R247 ACLR Alternate Counter Low Register FC 109 R248 OC1HR Output Compare 1 High Register 80 110 R249 OC1LR Output Compare 1 Low Register 00 110 R250 OC2HR Output Compare 2 High Register 80 110 R251 OC2LR Output Compare 2 Low Register 00 110 R252 CR1 Control Register 1 00 111 R253 CR2 Control Register 2 00 112 R254 SR Status Register 00 113 R255 CR3 Control Register 3 00 113 R248 PCR0 Peripheral Control Register 0 80 130 R249 PCR1 Peripheral Control Register 1 00 130 R250 PCR2 Peripheral Control Register 2 00 131 9 Polarity Selection Register 00 131 OPR Output Peripheral Register 00 132 IMR Interrupt Mask Register 00 132 DTG Dead Time Generator Register 00 133 R255 18/178 PSR R252 R254 IMC R251 R253 48 IMCIVR IMC Interrupt Vector Register xx 133 ST92141 ST92141 - GENERAL DESCRIPTION Register Name Description Reset Value Hex. Doc. Page TCPTH Tacho Capture Register High xx 125 R241 TCPTL Tacho Capture Register Low xx 125 R242 (Decimal) Block Reg. No. R240 Page TCMP Tacho Compare Register xx 125 R243 Tacho Prescaler Register Low 00 127 CPRS PWM Counter Prescaler Register 00 127 R247 REP Repetition Counter Register 00 127 R248 CPWH Compare Phase W Preload Register High 00 128 CPWL Compare Phase W Preload Register Low 00 128 CPVH Compare Phase V Preload Register High 00 128 CPVL Compare Phase V Preload Register Low 00 128 R252 CPUH Compare Phase U Preload Register High 00 129 R253 CPUL Compare Phase U Preload Register Low 00 129 R254 CP0H Compare 0 Preload Register High 00 129 R255 CP0L Compare 0 Preload Register Low 00 129 R240 CLKCTL Clock Control Register 00 69 R242 CLK_FLAG Clock Flag Register 48, 28 70 R246 PLLCONF PLL Configuration Register xx 71 R249 WUCTRL Wake-Up Control Register 00 59 R250 WUMRH Wake-Up Mask Register High 00 60 R251 WUMRL Wake-Up Mask Register Low 00 60 R252 WUTRH Wake-Up Trigger Register High 00 61 R253 WUTRL Wake-Up Trigger Register Low 00 61 R254 WUIMU TPRSL R251 57 127 R250 RCCU 36 00 R249 55 3F Tacho Prescaler Register High R246 IMC Interrupt Status Register TPRSH R245 51 ISR R244 WUPRH Wake-Up Pending Register High 00 61 R255 WUPRL Wake-Up Pending Register Low 00 61 R240 D0R Channel 0 Data Register xx 151 R241 D1R Channel 1 Data Register xx 151 R242 D2R Channel 2 Data Register xx 151 R243 D3R Channel 3 Data Register xx 151 R244 D4R Channel 4 Data Register xx 151 R245 D5R Channel 5 Data Register xx 151 R246 D6R Channel 6 Data Register xx 151 D7R Channel 7 Data Register xx 151 R248 LT6R Channel 6 Lower Threshold Reg. xx 152 LT7R Channel 7 Lower Threshold Reg. xx 152 R250 UT6R Channel 6 Upper Threshold Reg. xx 152 R251 UT7R Channel 7 Upper Threshold Reg. xx 152 R252 CRR Compare Result Register 0F 153 R253 CLR Control Logic Register 00 154 R254 ICR Interrupt Control Register 0F 155 R255 ADC R247 R249 63 IVR Interrupt Vector Register x2 155 Note: xx denotes a byte with an undefined value, however some of the bits may have defined values. Refer to register description for details. 19/178 9 ST92141 ST92141 - DEVICE ARCHITECTURE 2 DEVICE ARCHITECTURE 2.1 CORE ARCHITECTURE which hold data and control bits for the on-chip peripherals and I/Os. ­ A single linear memory space accommodating both program and data. All of the physically separate memory areas, including the internal ROM, internal RAM and external memory are mapped in this common address space. The total addressable memory space of 4 Mbytes (limited by the size of on-chip memory and the number of external address pins) is arranged as 64 segments of 64 Kbytes. Each segment is further subdivided into four pages of 16 Kbytes, as illustrated in Figure 3. A Memory Management Unit uses a set of pointer registers to address a 22-bit memory field using 16-bit address-based instructions. 2.2.1 Register File The Register File consists of (see Figure 4): 2.2 MEMORY SPACES ­ 224 general purpose registers (Group 0 to D, There are two separate memory spaces: registers R0 to R223) ­ The Register File, which comprises 240 8-bit ­ 6 system registers in the System Group (Group registers, arranged as 15 groups (Group 0 to E), E, registers R224 to R239) each containing sixteen 8-bit registers plus up to ­ Up to 64 pages, depending on device configura64 pages of 16 registers mapped in Group F, tion, each containing up to 16 registers, mapped to Group F (R240 to R255), see Figure 5. Figure 3. Single Program and Data Memory Address Space The ST9 Core or Central Processing Unit (CPU) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as BCD and Boolean formats; 14 addressing modes are available. Four independent buses are controlled by the Core: a 16-bit Memory bus, an 8-bit Register data bus, an 8-bit Register address bus and a 6-bit Interrupt/DMA bus which connects the interrupt and DMA controllers in the on-chip peripherals with the Core. This multiple bus architecture affords a high degree of pipelining and parallel operation, thus making the ST9 family devices highly efficient, both for numerical calculation, data handling and with regard to communication with on-chip peripheral resources. Data 16K Pages Address 255 254 253 252 251 250 249 248 247 3FFFFFh 3F0000h 3EFFFFh 3E0000h Code 64K Segments 63 62 up to 4 Mbytes 21FFFFh 210000h 20FFFFh 02FFFFh 020000h 01FFFFh 010000h 00FFFFh 000000h 20/178 9 Reserved 135 134 133 132 11 10 9 8 7 6 5 4 3 2 1 0 33 2 1 0 ST92141 ST92141 - DEVICE ARCHITECTURE MEMORY SPACES (Cont'd) Figure 4. Register Groups Figure 5. Page Pointer for Group F mapping PAGE 63 UP TO 64 PAGES 255 240 F PAGED REGISTERS 239 E SYSTEM REGISTERS 224 223 D PAGE 5 R255 PAGE 0 C B A R240 9 R234 8 224 GENERAL PURPOSE REGISTERS 7 6 PAGE POINTER R224 5 4 3 2 1 0 15 0 0 VA00432 VA00432 R0 VA00433 VA00433 Figure 6. Addressing the Register File REGISTER FILE 255 240 F PAGED REGISTERS 239 E SYSTEM REGISTERS 224 223 D GROUP D C R195 (R0C3h) B R207 A 9 (1100) (0011) 8 GROUP C 7 6 R195 5 4 R192 3 GROUP B 2 1 0 0 15 0 VR000118 VR000118 21/178 9 ST92141 ST92141 - DEVICE ARCHITECTURE MEMORY SPACES (Cont'd) 2.2.2 Register Addressing Register File registers, including Group F paged registers (but excluding Group D), may be addressed explicitly by means of a decimal, hexadecimal or binary address; thus R231, RE7h and R11100111b represent the same register (see Figure 6). Group D registers can only be addressed in Working Register mode. Note that an upper case "R" is used to denote this direct addressing mode. Working Registers Certain types of instruction require that registers be specified in the form "rx", where x is in the range 0 to 15: these are known as Working Registers. Note that a lower case "r" is used to denote this indirect addressing mode. Two addressing schemes are available: a single group of 16 working registers, or two separately mapped groups, each consisting of 8 working registers. These groups may be mapped starting at any 8 or 16 byte boundary in the register file by means of dedicated pointer registers. This technique is described in more detail in Section 2.3.3 Register Pointing Techniques, and illustrated in Figure 7 and in Figure 8. System Registers The 16 registers in Group E (R224 to R239) are System registers and may be addressed using any of the register addressing modes. These registers are described in greater detail in Section 2.3 SYSTEM REGISTERS. Paged Registers Up to 64 pages, each containing 16 registers, may be mapped to Group F. These are addressed using any register addressing mode, in conjunction with the Page Pointer register, R234, which is one of the System registers. This register selects the page to be mapped to Group F and, once set, does not need to be changed if two or more registers on the same page are to be addressed in succession. 22/178 1 Therefore if the Page Pointer, R234, is set to 5, the instructions: spp #5 ld R242, r4 will load the contents of working register r4 into the third register of page 5 (R242). These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between ST9 devices. The number of these registers therefore depends on the peripherals which are present in the specific ST9 family device. In other words, pages only exist if the relevant peripheral is present. Table 9. Register File Organization Hex. Address Decimal Address Function Register File Group F0-FF 240-255 Paged Registers Group F E0-EF 224-239 System Registers Group E D0-DF 208-223 Group D C0-CF 192-207 Group C B0-BF 176-191 Group B A0-AF 160-175 Group A 90-9F 90-9F 144-159 Group 9 80-8F 80-8F 128-143 Group 8 General Purpose Registers 70-7F 70-7F 112-127 60-6F 60-6F 96-111 Group 7 50-5F 50-5F 80-95 Group 5 40-4F 40-4F 64-79 Group 4 30-3F 30-3F 48-63 Group 3 20-2F 20-2F 32-47 Group 2 10-1F 10-1F 16-31 Group 1 00-0F 00-0F 00-15 Group 0 Group 6 ST92141 ST92141 - DEVICE ARCHITECTURE 2.3 SYSTEM REGISTERS The System registers are listed in Table 10 System Registers (Group E). They are used to perform all the important system settings. Their purpose is described in the following pages. Refer to the chapter dealing with I/O for a description of the PORT[5:0] Data registers. Table 10. System Registers (Group E) R239 (EFh) SSPLR R238 (EEh) SSPHR R237 (EDh) USPLR R236 (ECh) USPHR R235 (EBh) MODE REGISTER R234 (EAh) PAGE POINTER REGISTER R233 (E9h) REGISTER POINTER 1 R232 (E8h) Note: If an MFT is not included in the ST9 device, then this bit has no effect. Bit 6 = TLIP: Top Level Interrupt Pending. This bit is set by hardware when a Top Level Interrupt Request is recognized. This bit can also be set by software to simulate a Top Level Interrupt Request. 0: No Top Level Interrupt pending 1: Top Level Interrupt pending REGISTER POINTER 0 R231 (E7h) FLAG REGISTER R230 (E6h) Bit 5 = TLI: Top Level Interrupt bit. 0: Top Level Interrupt is acknowledged depending on the TLNM bit in the NICR Register. 1: Top Level Interrupt is acknowledged depending on the IEN and TLNM bits in the NICR Register (described in the Interrupt chapter). CENTRAL INT. CNTL REG R229 (E5h) PORT5 DATA REG. R228 (E4h) PORT4 DATA REG. R227 (E3h) PORT3 DATA REG. R226 (E2h) PORT2 DATA REG. R225 (E1h) PORT1 DATA REG. R224 (E0h) PORT0 DATA REG. 2.3.1 Central Interrupt Control Register Please refer to the "INTERRUPT" chapter for a detailed description of the ST9 interrupt philosophy. CENTRAL INTERRUPT CONTROL REGISTER (CICR) R230 - Read/Write Register Group: E (System) Reset Value: 1000 0111 (87h) 7 GCEN TLIP 0 TLI IEN IAM CPL2 CPL1 CPL0 Bit 7 = GCEN: Global Counter Enable. This bit is the Global Counter Enable of the Multifunction Timers. The GCEN bit is ANDed with the CE bit in the TCR Register (only in devices featuring the MFT Multifunction Timer) in order to enable the Timers when both bits are set. This bit is set after the Reset cycle. Bit 4 = IEN: Interrupt Enable . This bit is cleared by interrupt acknowledgement, and set by interrupt return (iret). IEN is modified implicitly by iret, ei and di instructions or by an interrupt acknowledge cycle. It can also be explicitly written by the user, but only when no interrupt is pending. Therefore, the user should execute a di instruction (or guarantee by other means that no interrupt request can arrive) before any write operation to the CICR register. 0: Disable all interrupts except Top Level Interrupt. 1: Enable Interrupts Bit 3 = IAM: Interrupt Arbitration Mode. This bit is set and cleared by software to select the arbitration mode. 0: Concurrent Mode 1: Nested Mode. Bit 2:0 = CPL[2:0]: Current Priority Level. These three bits record the priority level of the routine currently running (i.e. the Current Priority Level, CPL). The highest priority level is represented by 000, and the lowest by 111. The CPL bits can be set by hardware or software and provide the reference according to which subsequent interrupts are either left pending or are allowed to interrupt the current interrupt service routine. When the current interrupt is replaced by one of a higher priority, the current priority value is automatically stored until required in the NICR register. 23/178 1 ST92141 ST92141 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont'd) 2.3.2 Flag Register The Flag Register contains 8 flags which indicate the CPU status. During an interrupt, the flag register is automatically stored in the system stack area and recalled at the end of the interrupt service routine, thus returning the CPU to its original status. This occurs for all interrupts and, when operating in nested mode, up to seven versions of the flag register may be stored. FLAG REGISTER (FLAGR) R231- R231- Read/Write Register Group: E (System) Reset value: 0000 0000 (00h) 7 0 C Z S V DA H - DP Bit 7 = C: Carry Flag. The carry flag is affected by: Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left Arithmetic (sla, slaw), Swap Nibbles (swap), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply and Divide (mul, div, divws). When set, it generally indicates a carry out of the most significant bit position of the register being used as an accumulator (bit 7 for byte operations and bit 15 for word operations). The carry flag can be set by the Set Carry Flag (scf) instruction, cleared by the Reset Carry Flag (rcf) instruction, and complemented by the Complement Carry Flag (ccf) instruction. Bit 6 = Z: Zero Flag. The Zero flag is affected by: Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left Arithmetic (sla, slaw), Swap Nibbles (swap), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply and Divide (mul, div, divws), Logical (and, andw, or, orw, xor, xorw, cpl), Increment and Decrement (inc, incw, dec, 24/178 1 decw), Test (tm, tmw, tcm, tcmw, btset). In most cases, the Zero flag is set when the contents of the register being used as an accumulator become zero, following one of the above operations. Bit 5 = S: Sign Flag. The Sign flag is affected by the same instructions as the Zero flag. The Sign flag is set when bit 7 (for a byte operation) or bit 15 (for a word operation) of the register used as an accumulator is one. Bit 4 = V: Overflow Flag. The Overflow flag is affected by the same instructions as the Zero and Sign flags. When set, the Overflow flag indicates that a two'scomplement number, in a result register, is in error, since it has exceeded the largest (or is less than the smallest), number that can be represented in two's-complement notation. Bit 3 = DA: Decimal Adjust Flag. The DA flag is used for BCD arithmetic. Since the algorithm for correcting BCD operations is different for addition and subtraction, this flag is used to specify which type of instruction was executed last, so that the subsequent Decimal Adjust (da) operation can perform its function correctly. The DA flag cannot normally be used as a test condition by the programmer. Bit 2 = H: Half Carry Flag. The H flag indicates a carry out of (or a borrow into) bit 3, as the result of adding or subtracting two 8-bit bytes, each representing two BCD digits. The H flag is used by the Decimal Adjust (da) instruction to convert the binary result of a previous addition or subtraction into the correct BCD result. Like the DA flag, this flag is not normally accessed by the user. Bit 1 = Reserved bit (must be 0). Bit 0 = DP: Data/Program Memory Flag. This bit indicates the memory area addressed. Its value is affected by the Set Data Memory (sdm) and Set Program Memory (spm) instructions. Refer to the Memory Management Unit for further details. ST92141 ST92141 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont'd) If the bit is set, data is accessed using the Data Pointers (DPRs registers), otherwise it is pointed to by the Code Pointer (CSR register); therefore, the user initialization routine must include a Sdm instruction. Note that code is always pointed to by the Code Pointer (CSR). Note: In the current ST9 devices, the DP flag is only for compatibility with software developed for the first generation of ST9 devices. With the single memory addressing space, its use is now redundant. It must be kept to 1 with a Sdm instruction at the beginning of the program to ensure a normal use of the different memory pointers. 2.3.3 Register Pointing Techniques Two registers within the System register group, are used as pointers to the working registers. Register Pointer 0 (R232) may be used on its own as a single pointer to a 16-register working space, or in conjunction with Register Pointer 1 (R233), to point to two separate 8-register spaces. For the purpose of register pointing, the 16 register groups of the register file are subdivided into 32 8register blocks. The values specified with the Set Register Pointer instructions refer to the blocks to be pointed to in twin 8-register mode, or to the lower 8-register block location in single 16-register mode. The Set Register Pointer instructions srp, srp0 and srp1 automatically inform the CPU whether the Register File is to operate in single 16-register mode or in twin 8-register mode. The srp instruction selects the single 16-register group mode and specifies the location of the lower 8-register block, while the srp0 and srp1 instructions automatically select the twin 8-register group mode and specify the locations of each 8-register block. There is no limitation on the order or position of these register groups, other than that they must start on an 8-register boundary in twin 8-register mode, or on a 16-register boundary in single 16register mode. The block number should always be an even number in single 16-register mode. The 16-register group will always start at the block whose number is the nearest even number equal to or lower than the block number specified in the srp instruction. Avoid using odd block numbers, since this can be confusing if twin mode is subsequently selected. Thus: srp #3 will be interpreted as srp #2 and will allow using R16 .R31 as r0 . r15. In single 16-register mode, the working registers are referred to as r0 to r15. In twin 8-register mode, registers r0 to r7 are in the block pointed to by RP0 (by means of the srp0 instruction), while registers r8 to r15 are in the block pointed to by RP1 (by means of the srp1 instruction). Caution: Group D registers can only be accessed as working registers using the Register Pointers, or by means of the Stack Pointers. They cannot be addressed explicitly in the form "Rxxx". 25/178 1 ST92141 ST92141 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont'd) POINTER 0 REGISTER (RP0) R232 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh) POINTER 1 REGISTER (RP1) R233 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh) 7 0 RG4 RG3 RG2 RG1 RG0 RPS 0 7 0 RG4 Bit 7:3 = RG[4:0]: Register Group number. These bits contain the number (in the range 0 to 31) of the register block specified in the srp0 or srp instructions. In single 16-register mode the number indicates the lower of the two 8-register blocks to which the 16 working registers are to be mapped, while in twin 8-register mode it indicates the 8-register block to which r0 to r7 are to be mapped. Bit 2 = RPS: Register Pointer Selector. This bit is set by the instructions srp0 and srp1 to indicate that the twin register pointing mode is selected. The bit is reset by the srp instruction to indicate that the single register pointing mode is selected. 0: Single register pointing mode 1: Twin register pointing mode 0 RG3 RG2 RG1 RG0 RPS 0 0 This register is only used in the twin register pointing mode. When using the single register pointing mode, or when using only one of the twin register groups, the RP1 register must be considered as RESERVED and may NOT be used as a general purpose register. Bit 7:3 = RG[4:0]: Register Group number. These bits contain the number (in the range 0 to 31) of the 8-register block specified in the srp1 instruction, to which r8 to r15 are to be mapped. Bit 2 = RPS: Register Pointer Selector. This bit is set by the srp0 and srp1 instructions to indicate that the twin register pointing mode is selected. The bit is reset by the srp instruction to indicate that the single register pointing mode is selected. 0: Single register pointing mode 1: Twin register pointing mode Bit 1:0: Reserved. Forced by hardware to zero. Bit 1:0: Reserved. Forced by hardware to zero. 26/178 1 ST92141 ST92141 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont'd) Figure 7. Pointing to a single group of 16 registers REGISTER GROUP BLOCK NUMBER REGISTER GROUP BLOCK NUMBER Figure 8. Pointing to two groups of 8 registers REGISTER FILE REGISTER FILE 31 REGISTER POINTER 0 & REGISTER POINTER 1 F 31 REGISTER POINTER 0 set by: F 30 srp #2 29 instruction E 30 29 E set by: 28 srp0 #2 28 & points to: 27 D 27 D srp1 #7 instructions 26 point to: 26 25 25 addressed by BLOCK 7 9 4 9 8 4 r15 8 7 GROUP 3 3 7 r8 6 3 6 5 2 5 4 2 4 3 r15 1 3 1 GROUP 1 r7 2 r0 2 r0 1 0 addressed by BLOCK 2 1 GROUP 1 addressed by BLOCK 2 0 0 0 27/178 1 ST92141 ST92141 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont'd) 2.3.4 Paged Registers Up to 64 pages, each containing 16 registers, may be mapped to Group F. These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between ST9 devices. The number of these registers depends on the peripherals present in the specific ST9 device. In other words, pages only exist if the relevant peripheral is present. The paged registers are addressed using the normal register addressing modes, in conjunction with the Page Pointer register, R234, which is one of the System registers. This register selects the page to be mapped to Group F and, once set, does not need to be changed if two or more registers on the same page are to be addressed in succession. Thus the instructions: spp #5 ld R242, r4 will load the contents of working register r4 into the third register of page 5 (R242). Warning: During an interrupt, the PPR register is not saved automatically in the stack. If needed, it should be saved/restored by the user within the interrupt routine. PAGE POINTER REGISTER (PPR) R234 - Read/Write Register Group: E (System) Reset value: xxxx xx00 (xxh) 7 0 PP5 PP4 PP3 PP2 PP1 PP0 0 0 Bit 7:2 = PP[5:0]: Page Pointer. These bits contain the number (in the range 0 to 63) of the page specified in the spp instruction. Once the page pointer has been set, there is no need to refresh it unless a different page is required. Bit 1:0: Reserved. Forced by hardware to 0. 2.3.5 Mode Register The Mode Register allows control of the following operating parameters: ­ Selection of internal or external System and User Stack areas, 28/178 1 ­ Management of the clock frequency, ­ Enabling of Bus request and Wait signals when interfacing to external memory. MODE REGISTER (MODER) R235 - Read/Write Register Group: E (System) Reset value: 1110 0000 (E0h) 7 SSP 0 USP DIV2 PRS2 PRS1 PRS0 BRQEN HIMP Bit 7 = SSP: System Stack Pointer. This bit selects an internal or external System Stack area. 0: External system stack area, in memory space. 1: Internal system stack area, in the Register File (reset state). Bit 6 = USP: User Stack Pointer. This bit selects an internal or external User Stack area. 0: External user stack area, in memory space. 1: Internal user stack area, in the Register File (reset state). Bit 5 = DIV2: OSCIN Clock Divided by 2. This bit controls the divide-by-2 circuit operating on OSCIN. 0: Clock divided by 1 1: Clock divided by 2 Bit 4:2 = PRS[2:0]: CPUCLK Prescaler. These bits load the prescaler division factor for the internal clock (INTCLK). The prescaler factor selects the internal clock frequency, which can be divided by a factor from 1 to 8. Refer to the Reset and Clock Control chapter for further information. Bit 1 = BRQEN: Bus Request Enable. 0: External Memory Bus Request disabled 1: External Memory Bus Request enabled on BREQ pin (where available). Note: Disregard this bit if BREQ pin is not available. Bit 0 = HIMP: High Impedance Enable. When any of Ports 0, 1, 2 or 6 depending on device configuration, are programmed as Address and Data lines to interface external Memory, these lines and the Memory interface control lines (AS, DS, R/W) can be forced into the High Impedance ST92141 ST92141 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont'd) state by setting the HIMP bit. When this bit is reset, it has no effect. Setting the HIMP bit is recommended for noise reduction when only internal Memory is used. If Port 1 and/or 2 are declared as an address AND as an I/O port (for example: P10. P14 = Address, and P15. P17 = I/O), the HIMP bit has no effect on the I/O lines. 2.3.6 Stack Pointers Two separate, double-register stack pointers are available: the System Stack Pointer and the User Stack Pointer, both of which can address registers or memory. The stack pointers point to the "bottom" of the stacks which are filled using the push commands and emptied using the pop commands. The stack pointer is automatically pre-decremented when data is "pushed" in and post-incremented when data is "popped" out. The push and pop commands used to manage the System Stack may be addressed to the User Stack by adding the suffix "u". To use a stack instruction for a word, the suffix "w" is added. These suffixes may be combined. When bytes (or words) are "popped" out from a stack, the contents of the stack locations are unchanged until fresh data is loaded. Thus, when data is "popped" from a stack area, the stack contents remain unchanged. Note: Instructions such as: pushuw RR236 RR236 or pushw RR238 RR238, as well as the corresponding pop instructions (where R236 & R237, and R238 & R239 are themselves the user and system stack pointers respectively), must not be used, since the pointer values are themselves automatically changed by the push or pop instruction, thus corrupting their value. System Stack The System Stack is used for the temporary storage of system and/or control data, such as the Flag register and the Program counter. The following automatically push data onto the System Stack: ­ Interrupts When entering an interrupt, the PC and the Flag Register are pushed onto the System Stack. If the ENCSR bit in the EMR2 register is set, then the Code Segment Register is also pushed onto the System Stack. ­ Subroutine Calls When a call instruction is executed, only the PC is pushed onto stack, whereas when a calls instruction (call segment) is executed, both the PC and the Code Segment Register are pushed onto the System Stack. ­ Link Instruction The link or linku instructions create a C language stack frame of user-defined length in the System or User Stack. All of the above conditions are associated with their counterparts, such as return instructions, which pop the stored data items off the stack. User Stack The User Stack provides a totally user-controlled stacking area. The User Stack Pointer consists of two registers, R236 and R237, which are both used for addressing a stack in memory. When stacking in the Register File, the User Stack Pointer High Register, R236, becomes redundant but must be considered as reserved. Stack Pointers Both System and User stacks are pointed to by double-byte stack pointers. Stacks may be set up in RAM or in the Register File. Only the lower byte will be required if the stack is in the Register File. The upper byte must then be considered as reserved and must not be used as a general purpose register. The stack pointer registers are located in the System Group of the Register File, this is illustrated in Table 10 System Registers (Group E). Stack location Care is necessary when managing stacks as there is no limit to stack sizes apart from the bottom of any address space in which the stack is placed. Consequently programmers are advised to use a stack pointer value as high as possible, particularly when using the Register File as a stacking area. Group D is a good location for a stack in the Register File, since it is the highest available area. The stacks may be located anywhere in the first 14 groups of the Register File (internal stacks) or in RAM (external stacks). Note. Stacks must not be located in the Paged Register Group or in the System Register Group. 29/178 1 ST92141 ST92141 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont'd) USER STACK POINTER HIGH REGISTER (USPHR) R236 - Read/Write Register Group: E (System) Reset value: undefined SYSTEM STACK POINTER HIGH REGISTER (SSPHR) R238 - Read/Write Register Group: E (System) Reset value: undefined 7 0 USP15 USP15 USP14 USP14 USP13 USP13 USP12 USP12 USP11 USP11 USP10 USP10 USP9 USP8 7 SSP15 SSP15 SSP14 SSP14 SSP13 SSP13 SSP12 SSP12 SSP11 SSP11 SSP10 SSP10 SSP9 7 0 USP6 USP5 USP4 USP3 USP2 USP1 7 USP0 SSP7 Figure 9. Internal Stack Mode SSP6 SSP5 REGISTER FILE STACK POINTER (LOW) F 0 SSP4 SSP3 SSP2 SSP1 Figure 10. External Stack Mode REGISTER FILE points to: F STACK POINTER (LOW) & STACK POINTER (HIGH) point to: MEMORY E E STACK D D 4 4 3 3 2 2 1 1 0 0 STACK 30/178 1 SSP8 SYSTEM STACK POINTER LOW REGISTER (SSPLR) R239 - Read/Write Register Group: E (System) Reset value: undefined USER STACK POINTER LOW REGISTER (USPLR) R237 - Read/Write Register Group: E (System) Reset value: undefined USP7 0 SSP0 ST92141 ST92141 - DEVICE ARCHITECTURE 2.4 MEMORY ORGANIZATION Code and data are accessed within the same linear address space. All of the physically separate memory areas, including the internal ROM, internal RAM and external memory are mapped in a common address space. The ST9 provides a total addressable memory space of 4 Mbytes. This address space is arranged as 64 segments of 64 Kbytes; each segment is again subdivided into four 16 Kbyte pages. The mapping of the various memory areas (internal RAM or ROM, external memory) differs from device to device. Each 64-Kbyte physical memory segment is mapped either internally or externally; if the memory is internal and smaller than 64 Kbytes, the remaining locations in the 64-Kbyte segment are not used (reserved). Refer to the Register and Memory Map Chapter for more details on the memory map. 31/178 1 ST92141 ST92141 - DEVICE ARCHITECTURE 2.5 MEMORY MANAGEMENT UNIT The CPU Core includes a Memory Management Unit (MMU) which must be programmed to perform memory accesses (even if external memory is not used). The MMU is controlled by 7 registers and 2 bits (ENCSR and DPRREM) present in EMR2, which may be written and read by the user program. These registers are mapped within group F, Page 21 of the Register File. The 7 registers may be Figure 11. Page 21 Registers sub-divided into 2 main groups: a first group of four 8-bit registers (DPR[3:0]), and a second group of three 6-bit registers (CSR, ISR, and DMASR). The first group is used to extend the address during Data Memory access (DPR[3:0]). The second is used to manage Program and Data Memory accesses during Code execution (CSR), Interrupts Service Routines (ISR or CSR), and DMA transfers (DMASR or ISR). Page 21 FFh R255 FEh R254 FDh R253 FCh R252 FBh R251 FAh R250 F9h DMASR R249 F8h ISR R248 Relocation of P[3:0] and DPR[3:0] Registers F7h MMU R247 F6h EMR2 R246 F5h EMR1 R245 F4h CSR R244 F3h DPR3 R243 F2h DPR2 R242 F1h DPR1 R241 F0h DPR0 R240 32/178 1 EM MMU MMU SSPLR SSPHR USPLR USPHR MODER PPR RP1 RP0 FLAGR CICR P5DR P4DR P3DR P2DR P1DR P0DR DMASR ISR EMR2 EMR1 CSR DPR3 DPR2 1 DPR0 Bit DPRREM=0 (default setting) SSPLR SSPHR USPLR USPHR MODER PPR RP1 RP0 FLAGR CICR P5DR P4DR DPR3 DPR2 DPR1 DPR0 DMASR ISR EMR2 EMR1 CSR P3DR P2DR P1DR P0DR Bit DPRREM=1 ST92141 ST92141 - DEVICE ARCHITECTURE 2.6 ADDRESS SPACE EXTENSION To manage 4 Mbytes of addressing space it is necessary to have 22 address bits. The MMU adds 6 bits to the usual 16-bit address, thus translating a 16-bit virtual address into a 22-bit physical address. There are 2 different ways to do this depending on the memory involved and on the operation being performed. 2.6.1 Addressing 16-Kbyte Pages This extension mode is implicitly used to address Data memory space if no DMA is being performed. The Data memory space is divided into 4 pages of 16 Kbytes. Each one of the four 8-bit registers (DPR[3:0], Data Page Registers) selects a different 16-Kbyte page. The DPR registers allow access to the entire memory space which contains 256 pages of 16 Kbytes. Data paging is performed by extending the 14 LSB of the 16-bit address with the contents of a DPR register. The two MSBs of the 16-bit address are interpreted as the identification number of the DPR register to be used. Therefore, the DPR registers Figure 12. Addressing via DPR[3:0] are involved in the following virtual address ranges: DPR0: from 0000h to 3FFFh; DPR1: from 4000h to 7FFFh; DPR2: from 8000h to BFFFh; DPR3: from C000h to FFFFh. The contents of the selected DPR register specify one of the 256 possible data memory pages. This 8-bit data page number, in addition to the remaining 14-bit page offset address forms the physical 22-bit address (see Figure 12). A DPR register cannot be modified via an addressing mode that uses the same DPR register. For instance, the instruction "POPW DPR0" is legal only if the stack is kept either in the register file or in a memory location above 8000h, where DPR2 and DPR3 are used. Otherwise, since DPR0 and DPR1 are modified by the instruction, unpredictable behaviour could result. 16-bit virtual address MMU registers DPR0 DPR1 DPR2 DPR3 00 01 10 11 8 bits 2M SB 14 LSB 22-bit physical address 33/178 1 ST92141 ST92141 - DEVICE ARCHITECTURE ADDRESS SPACE EXTENSION (Cont'd) 2.6.2 Addressing 64-Kbyte Segments This extension mode is used to address Data memory space during a DMA and Program memory space during any code execution (normal code and interrupt routines). Three registers are used: CSR, ISR, and DMASR. The 6-bit contents of one of the registers CSR, ISR, or DMASR define one out of 64 Memory segments of 64 Kbytes within the 4 Mbytes address space. The register contents represent the 6 MSBs of the memory address, whereas the 16 LSBs of the address (intra-segment address) are given by the virtual 16-bit address (see Figure 13). 2.7 MMU REGISTERS The MMU uses 7 registers mapped into Group F, Page 21 of the Register File and 2 bits of the EMR2 register. Most of these registers do not have a default value after reset. 2.7.1 DPR[3:0]: Data Page Registers The DPR[3:0] registers allow access to the entire 4 Mbyte memory space composed of 256 pages of 16 Kbytes. 2.7.1.1 Data Page Register Relocation If these registers are to be used frequently, they may be relocated in register group E, by programming bit 5 of the EMR2-R246 EMR2-R246 register in page 21. If this bit is set, the DPR[3:0] registers are located at R224-227 R224-227 in place of the Port 0-3 Data Registers, which are re-mapped to the default DPR's locations: R240-243 R240-243 page 21. Data Page Register relocation is illustrated in Figure 11. Figure 13. Addressing via CSR, ISR, and DMASR 16-bit virtual address MMU registers CSR 1 1 2 3 DMASR 2 ISR 3 Fetching program instruction Data Memory accessed in DMA Fetching interrupt instruction or DMA access to Program Memory 6 bits 22-bit physical address 34/178 1 ST92141 ST92141 - DEVICE ARCHITECTURE MMU REGISTERS (Cont'd) DATA PAGE REGISTER 0 (DPR0) R240 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R224 if EMR2.5 is set. 7 0 DATA PAGE REGISTER 2 (DPR2) R242 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R226 if EMR2.5 is set. 7 0 DPR0_7 DPR0_6 DPR0_5 DPR0_4 DPR0_3 DPR0_2 DPR0_1 DPR0_0 DPR2_7 DPR2_6 DPR2_5 DPR2_4 DPR2_3 DPR2_2 DPR2_1 DPR2_0 Bit 7:0 = DPR0_[7:0]: These bits define the 16Kbyte Data Memory page number. They are used as the most significant address bits (A21-14 A21-14) to extend the address during a Data Memory access. The DPR0 register is used when addressing the virtual address range 0000h-3FFFh. Bit 7:0 = DPR2_[7:0]: These bits define the 16Kbyte Data memory page. They are used as the most significant address bits (A21-14 A21-14) to extend the address during a Data memory access. The DPR2 register is involved when the virtual address is in the range 8000h-BFFFh. DATA PAGE REGISTER 1 (DPR1) R241 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R225 if EMR2.5 is set. DATA PAGE REGISTER 3 (DPR3) R243 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R227 if EMR2.5 is set. 7 0 7 0 DPR1_7 DPR1_6 DPR1_5 DPR1_4 DPR1_3 DPR1_2 DPR1_1 DPR1_0 DPR3_7 DPR3_6 DPR3_5 DPR3_4 DPR3_3 DPR3_2 DPR3_1 DPR3_0 Bit 7:0 = DPR1_[7:0]: These bits define the 16Kbyte Data Memory page number. They are used as the most significant address bits (A21-14 A21-14) to extend the address during a Data Memory access. The DPR1 register is used when addressing the virtual address range 4000h-7FFFh. Bit 7:0 = DPR3_[7:0]: These bits define the 16Kbyte Data memory page. They are used as the most significant address bits (A21-14 A21-14) to extend the address during a Data memory access. The DPR3 register is involved when the virtual address is in the range C000h-FFFFh. 35/178 1 ST92141 ST92141 - DEVICE ARCHITECTURE MMU REGISTERS (Cont'd) 2.7.2 CSR: Code Segment Register This register selects the 64-Kbyte code segment being used at run-time to access instructions. It can also be used to access data if the spm instruction has been executed (or ldpp, ldpd, lddp). Only the 6 LSBs of the CSR register are implemented, and bits 6 and 7 are reserved. The CSR register allows access to the entire memory space, divided into 64 segments of 64 Kbytes. To generate the 22-bit Program memory address, the contents of the CSR register is directly used as the 6 MSBs, and the 16-bit virtual address as the 16 LSBs. Note: The CSR register should only be read and not written for data operations (there are some exceptions which are documented in the following paragraph). It is, however, modified either directly by means of the jps and calls instructions, or indirectly via the stack, by means of the rets instruction. CODE SEGMENT REGISTER (CSR) R244 - Read/Write Register Page: 21 Reset value: 0000 0000 (00h) 7 0 0 0 CSR_5 CSR_4 CSR_3 CSR_2 CSR_1 CSR_0 Bit 7:6 = Reserved, keep in reset state. Bit 5:0 = CSR_[5:0]: These bits define the 64Kbyte memory segment (among 64) which contains the code being executed. These bits are used as the most significant address bits (A21-16 A21-16). 0 0 0 36/178 1 Bit 7:6 = Reserved, keep in reset state. Bit 5:0 = ISR_[5:0]: These bits define the 64-Kbyte memory segment (among 64) which contains the interrupt vector table and the code for interrupt service routines and DMA transfers (when the PS bit of the DAPR register is reset). These bits are used as the most significant address bits (A21-16 A21-16). The ISR is used to extend the address space in two cases: ­ Whenever an interrupt occurs: ISR points to the 64-Kbyte memory segment containing the interrupt vector table and the interrupt service routine code. See also the Interrupts chapter. ­ During DMA transactions between the peripheral and memory when the PS bit of the DAPR register is reset : ISR points to the 64 K-byte Memory segment that will be involved in the DMA transaction. 2.7.4 DMASR: DMA Segment Register DMA SEGMENT REGISTER (DMASR) R249 - Read/Write Register Page: 21 Reset value: undefined 7 0 0 0 DMA SR_5 DMA SR_4 DMA SR_3 DMA SR_2 DMA SR_1 DMA SR_0 Bit 7:6 = Reserved, keep in reset state. 2.7.3 ISR: Interrupt Segment Register INTERRUPT SEGMENT REGISTER (ISR) R248 - Read/Write Register Page: 21 Reset value: undefined 7 ISR and ENCSR bit (EMR2 register) are also described in the chapter relating to Interrupts, please refer to this description for further details. ISR_5 ISR_4 ISR_3 ISR_2 ISR_1 ISR_0 Bit 5:0 = DMASR_[5:0]: These bits define the 64Kbyte Memory segment (among 64) used when a DMA transaction is performed between the peripheral's data register and Memory, with the PS bit of the DAPR register set. These bits are used as the most significant address bits (A21-16 A21-16). If the PS bit is reset, the ISR register is used to extend the address. ST92141 ST92141 - DEVICE ARCHITECTURE MMU REGISTERS (Cont'd) Figure 14. Memory Addressing Scheme (example) 4M bytes 3FFFFFh 16K 294000h DPR3 240000h 23FFFFh DPR2 DPR1 DPR0 16K 20C000h 16K 200000h 1FFFFFh 64K 040000h 03FFFFh 030000h DMASR 020000h ISR 64K CSR 16K 64K 010000h 00C000h 000000h 37/178 1 ST92141 ST92141 - DEVICE ARCHITECTURE 2.8 MMU USAGE 2.8.1 Normal Program Execution Program memory is organized as a set of 64Kbyte segments. The program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps, calls and rets instructions, which automatically modify the CSR, must be used to jump across segment boundaries. Writing to the CSR is forbidden during normal program execution because it is not synchronized with the opcode fetch. This could result in fetching the first byte of an instruction from one memory segment and the second byte from another. Writing to the CSR is allowed when it is not being used, i.e during an interrupt service routine if ENCSR is reset. Note that a routine must always be called in the same way, i.e. either always with call or always with calls, depending on whether the routine ends with ret or rets. This means that if the routine is written without prior knowledge of the location of other routines which call it, and all the program code does not fit into a single 64-Kbyte segment, then calls/rets should be used. In typical microcontroller applications, less than 64 Kbytes of RAM are used, so the four Data space pages are normally sufficient, and no change of DPR[3:0] is needed during Program execution. It may be useful however to map part of the ROM into the data space if it contains strings, tables, bit maps, etc. If there is to be frequent use of paging, the user can set bit 5 (DPRREM) in register R246 (EMR2) of Page 21. This swaps the location of registers DPR[3:0] with that of the data registers of Ports 03. In this way, DPR registers can be accessed without the need to save/set/restore the Page Pointer Register. Port registers are therefore moved to page 21. Applications that require a lot of paging typically use more than 64 Kbytes of external memory, and as ports 0, 1 and 2 are required to address it, their data registers are unused. 2.8.2 Interrupts The ISR register has been created so that the interrupt routines may be found by means of the same vector table even after a segment jump/call. When an interrupt occurs, the CPU behaves in one of 2 ways, depending on the value of the ENCSR bit in the EMR2 register (R246 on Page 21). If this bit is reset (default condition), the CPU works in original ST9 compatibility mode. For the duration of the interrupt service routine, the ISR is used instead of the CSR, and the interrupt stack 38/178 1 frame is kept exactly as in the original ST9 (only the PC and flags are pushed). This avoids the need to save the CSR on the stack in the case of an interrupt, ensuring a fast interrupt response time. The drawback is that it is not possible for an interrupt service routine to perform segment calls/jps: these instructions would update the CSR, which, in this case, is not used (ISR is used instead). The code size of all interrupt service routines is thus limited to 64 Kbytes. If, instead, bit 6 of the EMR2 register is set, the ISR is used only to point to the interrupt vector table and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and the flags, and then the CSR is loaded with the ISR. In this case, an iret will also restore the CSR from the stack. This approach lets interrupt service routines access the whole 4-Mbyte address space. The drawback is that the interrupt response time is slightly increased, because of the need to also save the CSR on the stack. Compatibility with the original ST9 is also lost in this case, because the interrupt stack frame is different; this difference, however, would not be noticeable for a vast majority of programs. Data memory mapping is independent of the value of bit 6 of the EMR2 register, and remains the same as for normal code execution: the stack is the same as that used by the main program, as in the ST9. If the interrupt service routine needs to access additional Data memory, it must save one (or more) of the DPRs, load it with the needed memory page and restore it before completion. 2.8.3 DMA Depending on the PS bit in the DAPR register (see DMA chapter) DMA uses either the ISR or the DMASR for memory accesses: this guarantees that a DMA will always find its memory segment(s), no matter what segment changes the application has performed. Unlike interrupts, DMA transactions cannot save/restore paging registers, so a dedicated segment register (DMASR) has been created. Having only one register of this kind means that all DMA accesses should be programmed in one of the two following segments: the one pointed to by the ISR (when the PS bit of the DAPR register is reset), and the one referenced by the DMASR (when the PS bit is set). ST92141 ST92141 - INTERRUPTS 3 INTERRUPTS 3.1 INTRODUCTION 3.2 INTERRUPT VECTORING The ST9 responds to peripheral and external events through its interrupt channels. Current program execution can be suspended to allow the ST9 to execute a specific response routine when such an event occurs, providing that interrupts have been enabled, and according to a priority mechanism. If an event generates a valid interrupt request, the current program status is saved and control passes to the appropriate Interrupt Service Routine (refer to Figure 15). The ST9 CPU can receive requests from the following sources: ­ On-chip peripherals ­ External pins ­ Top-Level Pseudo-non-maskable interrupt According to the on-chip peripheral features, an event occurrence can generate an Interrupt request which depends on the selected mode. Up to eight external interrupt channels, with programmable input trigger edge, are available. In addition, a dedicated interrupt channel, set to the Top-level priority, can be devoted either to the external NMI pin (where available) to provide a NonMaskable Interrupt, or to the Timer/Watchdog. Interrupt service routines are addressed through a vector table mapped in Memory. The ST9 implements an interrupt vectoring structure which allows the on-chip peripheral to identify the location of the first instruction of the Interrupt Service Routine automatically. When an interrupt request is acknowledged, the peripheral interrupt module provides, through its Interrupt Vector Register (IVR), a vector to point into the vector table of locations containing the start addresses of the Interrupt Service Routines (defined by the programmer). Each peripheral has a specific IVR mapped within its Register File pages. The Interrupt Vector table, containing the addresses of the Interrupt Service Routines, is located in the first 256 locations of Memory pointed to by the ISR register, thus allowing 8-bit vector addressing. For a description of the ISR register refer to the chapter describing the MMU. The user Power on Reset vector is stored in the first two physical bytes in memory, 000000h and 000001h. The Top Level Interrupt vector is located at addresses 0004h and 0005h in the segment pointed to by the Interrupt Segment Register (ISR). With one Interrupt Vector register, it is possible to address several interrupt service routines; in fact, peripherals can share the same interrupt vector register among several interrupt channels. The most significant bits of the vector are user programmable to define the base vector address within the vector table, the least significant bits are controlled by the interrupt module, in hardware, to select the appropriate vector. Note: The first 256 locations of the memory segment pointed to by ISR can contain program code. 3.2.1 Divide by Zero trap The Divide by Zero trap vector is located at addresses 0002h and 0003h of each code segment; it should be noted that for each code segment a Divide by Zero service routine is required. Warning. Although the Divide by Zero Trap operates as an interrupt, the FLAG Register is not pushed onto the system Stack automatically. As a result it must be regarded as a subroutine, and the service routine must end with the RET instruction (not IRET). Figure 15. Interrupt Response n NORMAL PROGRAM FLOW INTERRUPT INTERRUPT SERVICE ROUTINE CLEAR PENDING BIT IRET INSTRUCTION VR001833 VR001833 39/178 1 ST92141 ST92141 - INTERRUPTS 3.2.2 Segment Paging During Interrupt Routines The ENCSR bit in the EMR2 register can be used to select between original ST9 backward compatibility mode and ST9+ interrupt management mode. ST9 backward compatibility mode (ENCSR = 0) If ENCSR is reset, the CPU works in original ST9 compatibility mode. For the duration of the interrupt service routine, ISR is used instead of CSR, and the interrupt stack frame is identical to that of the original ST9: only the PC and Flags are pushed. This avoids saving the CSR on the stack in the event of an interrupt, thus ensuring a faster interrupt response time. It is not possible for an interrupt service routine to perform inter-segment calls or jumps: these instructions would update the CSR, which, in this case, is not used (ISR is used instead). The code segment size for all interrupt service routines is thus limited to 64K bytes. ST9+ mode (ENCSR = 1) If ENCSR is set, ISR is only used to point to the interrupt vector table and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and flags, and CSR is then loaded with the contents of ISR. In this case, iret will also restore CSR from the stack. This approach allows interrupt service routines to access the entire 4 Mbytes of address space. The drawback is that the interrupt response time is slightly increased, because of the need to also save CSR on the stack. Full compatibility with the original ST9 is lost in this case, because the interrupt stack frame is different. ENCSR Bit 0 1 Mode ST9 Compatible ST9+ Pushed/Popped PC, FLAGR, PC, FLAGR Registers CSR Max. Code Size 64KB No limit for interrupt Within 1 segment Across segments service routine 40/178 1 3.3 INTERRUPT PRIORITY LEVELS The ST9 supports a fully programmable interrupt priority structure. Nine priority levels are available to define the channel priority relationships: ­ The on-chip peripheral channels and the eight external interrupt sources can be programmed within eight priority levels. Each channel has a 3bit field, PRL (Priority Level), that defines its priority level in the range from 0 (highest priority) to 7 (lowest priority). ­ The 9th level (Top Level Priority) is reserved for the Timer/Watchdog or the External Pseudo Non-Maskable Interrupt. An Interrupt service routine at this level cannot be interrupted in any arbitration mode. Its mask can be both maskable (TLI) or non-maskable (TLNM). 3.4 PRIORITY LEVEL ARBITRATION The 3 bits of CPL (Current Priority Level) in the Central Interrupt Control Register contain the priority of the currently running program (CPU priority). CPL is set to 7 (lowest priority) upon reset and can be modified during program execution either by software or automatically by hardware according to the selected Arbitration Mode. During every instruction, an arbitration phase takes place, during which, for every channel capable of generating an Interrupt, each priority level is compared to all the other requests (interrupts or DMA). If the highest priority request is an interrupt, its PRL value must be strictly lower (that is, higher priority) than the CPL value stored in the CICR register (R230) in order to be acknowledged. The Top Level Interrupt overrides every other priority. 3.4.1 Priority level 7 (Lowest) Interrupt requests at PRL level 7 cannot be acknowledged, as this PRL value (the lowest possible priority) cannot be strictly lower than the CPL value. This can be of use in a fully polled interrupt environment. 3.4.2 Maximum depth of nesting No more than 8 routines ca