ST72E311 ST72T311 PSDIP42 CSDIP42W PSDIP56 CSDIP56W TQFP64 TQFP44 ST72T311J - Datasheet Archive

 

ST72T311 8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS DATASHEET s s s s s s s s s s s

 

ST72E311 ST72E311 ST72T311 ST72T311 8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS DATASHEET s s s s s s s s s s s s s s s s s User Program Memory (OTP/EPROM): 8 to 16K bytes Data RAM: 384 to 512 bytes including 256 bytes of stack Master Reset and Power-On Reset Low Voltage Detector Reset option Run and Power Saving modes 44 or 32 multifunctional bidirectional I/O lines: ­ 15 or 9 programmable interrupt inputs ­ 8 or 4 high sink outputs ­ 8 or 6 analog alternate inputs ­ 13 alternate functions ­ EMI filtering Software or Hardware Watchdog (WDG) Two 16-bit Timers, each featuring: ­ 2 Input Captures 1) ­ 2 Output Compares 1) ­ External Clock input (on Timer A) ­ PWM and Pulse Generator modes Synchronous Serial Peripheral Interface (SPI) Asynchronous Serial Communications Interface (SCI) 8-bit ADC with 8 channels 2) 8-bit Data Manipulation 63 basic Instructions and 17 main Addressing Modes 8 x 8 Unsigned Multiply Instruction True Bit Manipulation Complete Development Support on DOS/ WINDOWSTM Real-Time Emulator Full Software Package on DOS/WINDOWSTM (C-Compiler, Cross-Assembler, Debugger) PSDIP42 PSDIP42 CSDIP42W CSDIP42W PSDIP56 PSDIP56 CSDIP56W CSDIP56W TQFP64 TQFP64 TQFP44 TQFP44 (See ordering information at the end of datasheet) Notes: 1. One only on Timer A. 2. Six channels only for ST72T311J ST72T311J. Device Summary Features Program Memory - bytes RAM (stack) - bytes Peripherals Operating Supply CPU Frequency Temperature Range Package ST72T311J2 ST72T311J2 ST72T311J4 ST72T311J4 ST72T311N2 ST72T311N2 ST72T311N4 ST72T311N4 8K 16K 8K 16K 384 (256) 512 (256) 384 (256) 512 (256) Watchdog, Timers, SPI, SCI, ADC and optional Low Voltage Detector Reset 3 to 5.5 V 8MHz max (16MHz oscillator) - 4MHz max over 85°C - 40°C to + 125°C TQFP44 TQFP44 - SDIP42 SDIP42 TQFP64 TQFP64 - SDIP56 SDIP56 Note: The ROM versions are supported by the ST72314 ST72314 family. Rev. 1.8 May 2001 1/101 1 Table of Contents 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.4 Low Voltage Detector Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4.2 Slow Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4.3 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4.4 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1.3 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.4 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 16-BIT 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 . 35 . 5.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2/101 2 Table of Contents 6 7 8 9 5.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.4 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.4.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.6 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.6.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.1.7 Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.4 RESET CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.5 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.6 PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.1 EPROM ERASURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.2 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3/101 3 ST72E311 ST72E311 ST72T311 ST72T311 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST72T311 ST72T311 HCMOS Microcontroller Unit (MCU) is a member of the ST7 family. The device is based on an industry-standard 8-bit core and features an enhanced instruction set. The device is normally operated at a 16 MHz oscillator frequency. Under software control, the ST72T311 ST72T311 may be placed in either Wait, Slow or Halt modes, thus reducing power consumption. The enhanced instruction set and addressing modes afford real programming potential. In addition to standard 8-bit data management, the ST72T311 ST72T311 features true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes on the whole memory. The device includes a low consumption and fast start on-chip oscillator, CPU, program memory (OTP/EPROM versions), RAM, 44 (ST72T311N ST72T311N) or 32 (ST72T311J ST72T311J) I/O lines, a Low Voltage Detector (LVD) and the following on-chip peripherals: Analog-to-Digital converter (ADC) with 8 (ST72T311N ST72T311N) or 6 (ST72T311J ST72T311J) multiplexed analog inputs, industry standard synchronous SPI and asynchronous SCI serial interfaces, digital Watchdog, two independent 16-bit Timers, one featuring an External Clock Input, and both featuring Pulse Generator capabilities, 2 Input Captures and 2 Output Compares (only 1 Input Capture and 1 Output Compare on Timer A). Figure 1. ST72T311 ST72T311 Block Diagram OSCIN Internal CLOCK OSC PORT A PA0 -> PA7 (8 bits for ST72T311N ST72T311N) (5 bits for ST72T311J ST72T311J) CONTROL AND LVD PORT B PB0 -> PB7 (8 bits for ST72T311N ST72T311N) (5 bits for ST72T311J ST72T311J) OSCOUT RESET TIMER B 8-BIT CORE ALU RAM (384 - 512 Bytes) ADDRESS AND DATA BUS PROGRAM MEMORY (8 - 16K Bytes) PORT C PC0 -> PC7 (8 bits) SPI PORT D 8-BIT ADC PD0 -> PD7 (8 bits for ST72T311N ST72T311N) (6 bits for ST72T311J ST72T311J) PORT E PF0 -> PF2,4,6,7 (6 bits) PE0 -> PE7 PORT F SCI TIMER A VDD VSS 4/101 4 WATCH DOG POWER SUPPLY (6 bits for ST72T311N ST72T311N) (2 bits for ST72T311J ST72T311J) VDDA VSSA ST72E311 ST72E311 ST72T311 ST72T311 1.2 PIN DESCRIPTION 1. V PP on EPROM/OTP only 1 (EI3) 2 (EI3) 3 (EI3) 4 (EI3) 5 6 7 8 9 10 11 12 13 14 15 (EI1) 16 (EI1) 17 (EI1) 18 19 20 21 22 23 24 25 26 27 28 (EI2) 56 (EI2) 55 (EI2) 54 (EI2) 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 (EI0) 34 (EI0) 33 (EI0) 32 (EI0) 31 30 29 PP PA5 PA4 PA7 PA6 RESET TEST/V PP1) OSCOUT VSS_2 OSCIN PE0/TD0 VDD_2 44 43 42 41 40 39 38 37 36 35 34 33 1 32 2 (EI2) (EI0) 31 3 (EI2) 30 4 (EI2) 29 5 (EI2) 28 6 (EI3) VSS_1 VD D_1 PA3 PC7/SS PC6/SCK PC5/MOSI PC4/MISO PC3/ICAP1_B PC2/ICAP2_B PC1/OCMP1_B PC0/OCMP2_B CLKOUT/PF0 PF1 PF2 OCMP1_A/PF4 ICAP1_A/PF6 EXTCLK_A/PF7 VDD_0 VSS_0 (EI1) (EI1) (EI1) 27 7 26 8 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 AIN5/PD5 VDDA VSSA 1. V Figure 3. 56-Pin Shrink DIP Package Pinout PC0/OCMP2_B PC1/OCMP1_B PC2/ICAP2_B PC3/ICAP1_B PC4/MISO PC5/MOSI PE1/RDI PB0 PB1 PB2 PB3 PB4 AIN0/PD0 AIN1/PD1 AIN2/PD2 AIN3/PD3 AIN4/PD4 EXTCLK_A/PF7 NC ICAP1_A/PF6 VSS_1 VDD _1 PA3 PA2 PA1 PA0 PC7/SS PC6/SCK PC5/MOSI PC4/MISO PC3/ICAP1_B PC2/ICAP2_B PC1/OCMP1_B PC0/OCMP2_B VSS_0 VDD _0 on EPR OM/OTP only PB4 PB5 PB6 PB7 AIN0/PD0 AIN1/PD1 AIN2/PD2 AIN3/PD3 AIN4/PD4 AIN5/PD5 AIN6/PD6 AIN7/PD7 V DD A VSSA CLKOUT/PF0 PF1 PF2 OCMP1_A/PF4 ICAP1_A/PF6 EXTCLK_A/PF7 VDD_0 VSS_0 Figure 4. 44-Pin Thin QFP Package Pinout PA5 PA4 PA7 PA6 NC RESET TEST/V PP1) PF2 NC OCMP1_A/PF4 (EI1) (EI1) (EI1) CLKOUT/PF0 PF1 VSSA VDD_3 VSS_3 AIN7/PD7 V DDA AIN4/PD4 AIN5/PD5 AIN6/PD6 PP V SS_2 NC 64 63 62 61 60 59 58 5756 55 54 53 52 51 50 49 48 1 47 2 (EI0) 46 3 (EI0) 45 4 (EI0) 44 5 (EI2) (EI0) 43 6 (EI2) 7 (EI2) 42 8 (EI2) 41 (EI3) 9 40 10 (EI3) 39 11 (EI3) 38 (EI3) 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PE4 PE5 PE6 PE7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 AIN0/PD0 AIN1/PD1 AIN2/PD2 AIN3/PD3 1. V V DD_2 OSCIN OSCOUT PE1/RDI PE0/TDO NC NC Figure 2. 64-Pin Thin QFP Package Pinout on EPROM/OTP only Figure 5. 42-Pin Shrink DIP Package Pinout PB3 PB2 PB1 PB0 PE7 PE6 PE5 PE4 PE1/RDI PE0/TD0 VDD _2 OSCIN OSCOUT VSS_2 PB4 AIN0/PD0 AIN1/PD1 AIN2/PD2 AIN3/PD3 AIN4/PD4 AIN5/PD5 VD DA VSSA CLKOUT/PF0 PF1 PF2 OCMP1_A/PF4 ICAP1_A/PF6 EXTCLK_A/PF7 PC0/OCMP2_B PC1/OCMP1_B PC2/ICAP2_B PC3/ICAP1_B PC4/MISO PC5/MOSI RESET TEST/VPP 1) PA7 PA6 PA5 PA4 VSS_1 VD D_1 PA3 PA2 PA1 PA0 PC7/SS PC6/SCK 1. V PP 1 (EI3) 2 3 4 5 6 7 8 9 10 (EI1) 11 (EI1) 12 (EI1) 13 14 15 16 17 18 19 20 21 (EI2) (EI2) (EI2) (EI2) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 (EI0) 24 23 22 PB3 PB2 PB1 PB0 PE1/RDI PE0/TD0 VD D_2 OSCIN OSCOUT VSS_2 RESET TEST/V PP1) PA7 PA6 PA5 PA4 VSS_1 VD D_1 PA3 PC7/SS PC6/SCK on EPROM/OTP only 5/101 5 ST72E311 ST72E311 ST72T311 ST72T311 Table 1. ST72T311Nx Pin Description Pin n° Pin n° QFP64 QFP64 SDIP56 SDIP56 Pin Name Type Description Remarks 1 49 PE4 I/O Port E4 High Sink 2 50 PE5 I/O Port E5 High Sink 3 51 PE6 I/O Port E6 High Sink 4 52 PE7 I/O Port E7 High Sink 5 53 PB0 I/O Port B0 External Interrupt: EI2 6 54 PB1 I/O Port B1 External Interrupt: EI2 7 55 PB2 I/O Port B2 External Interrupt: EI2 8 56 PB3 I/O Port B3 External Interrupt: EI2 9 1 PB4 I/O Port B4 External Interrupt: EI3 10 2 PB5 I/O Port B5 External Interrupt: EI3 11 3 PB6 I/O Port B6 External Interrupt: EI3 12 4 PB7 I/O Port B7 External Interrupt: EI3 13 5 PD0/AIN0 I/O Port D0 or ADC Analog Input 0 14 6 PD1/AIN1 I/O Port D1 or ADC Analog Input 1 15 7 PD2/AIN2 I/O Port D2 or ADC Analog Input 2 16 8 PD3/AIN3 I/O Port D3 or ADC Analog Input 3 17 9 PD4/AIN4 I/O Port D4 or ADC Analog Input 4 18 10 PD5/AIN5 I/O Port D5 or ADC Analog Input 5 19 11 PD6/AIN6 I/O Port D6 or ADC Analog Input 6 20 12 PD7/AIN7 I/O Port D7 or ADC Analog Input 7 21 13 VDDA S Power Supply for analog peripheral (ADC) 22 14 VSSA S Ground for analog peripheral (ADC) 23 VDD_3 S Main power supply 24 VSS_3 S Ground 25 15 PF0/CLKOUT I/O Port F0 or CPU Clock Output External Interrupt: EI1 26 16 PF1 I/O Port F1 External Interrupt: EI1 27 17 PF2 I/O Port F2 External Interrupt: EI1 28 NC 29 18 30 PF4/OCMP1_A Not Connected I/O NC Port F4 or Timer A Output Compare 1 Not Connected 31 19 PF6/ICAP1_A I/O Port F6 or Timer A Input Capture 1 32 20 PF7/EXTCLK_A I/O Port F7 or External Clock on Timer A 33 21 VDD_0 S Main power supply 34 22 VSS_0 S Ground 35 23 PC0/OCMP2_B I/O Port C0 or Timer B Output Compare 2 36 24 PC1/OCMP1_B I/O Port C1 or Timer B Output Compare 1 37 25 PC2/ICAP2_B I/O Port C2 or Timer B Input Capture 2 38 26 PC3/ICAP1_B I/O Port C3 or Timer B Input Capture 1 39 27 PC4/MISO I/O Port C4 or SPI Master In / Slave Out Data 40 28 PC5/MOSI I/O Port C5 or SPI Master Out / Slave In Data 41 29 PC6/SCK I/O Port C6 or SPI Serial Clock 42 30 PC7/SS I/O Port C7 or SPI Slave Select 43 31 PA0 I/O Port A0 External Interrupt: EI0 44 32 PA1 I/O Port A1 External Interrupt: EI0 6/101 6 ST72E311 ST72E311 ST72T311 ST72T311 Pin n° Pin n° QFP64 QFP64 SDIP56 SDIP56 Type Pin Name Description Remarks 45 33 PA2 I/O Port A2 External Interrupt: EI0 46 34 PA3 I/O Port A3 External Interrupt: EI0 47 35 VDD_1 S Main power supply 48 36 VSS_1 S Ground 49 37 PA4 I/O Port A4 High Sink 50 38 PA5 I/O Port A5 High Sink 51 39 PA6 I/O Port A6 High Sink 52 40 PA7 I/O Port A7 High Sink 53 41 TEST/VPP1) S Test mode pin. In the EPROM programming This pin must be tied mode, this pin acts as the programming voltage low in user mode input VPP. 54 42 RESET I/O Bidirectional. Active low. Top priority non maskable interrupt. 55 NC 56 NC Not Connected Not Connected 57 43 VSS_2 S Ground 58 44 OSCOUT O 59 45 OSCIN I Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source to the on-chip oscillator. 60 46 VDD_2 S Main power supply 61 47 PE0/TDO I/O Port E1 or SCI Transmit Data Out 62 48 PE1/RDI I/O Port E1 or SCI Receive Data In 63 NC Not Connected 64 NC Not Connected Note 1: VPP on EPROM/OTP only. Table 2. ST72T311Jx Pin Description Pin n° Pin n° Pin Name QFP44 QFP44 SDIP42 SDIP42 1 38 PE1/RDI Type Description Remarks I/O Port E1 or SCI Receive Data In 2 39 PB0 I/O Port B0 External Interrupt: EI2 3 40 PB1 I/O Port B1 External Interrupt: EI2 4 41 PB2 I/O Port B2 External Interrupt: EI2 5 42 PB3 I/O Port B3 External Interrupt: EI2 6 7 1 2 PB4 PD0/AIN0 I/O I/O Port B4 Port D0 or ADC Analog Input 0 External Interrupt: EI3 8 3 PD1/AIN1 I/O Port D1 or ADC Analog Input 1 9 10 4 5 PD2/AIN2 PD3/AIN3 I/O I/O Port D2 or ADC Analog Input 2 Port D3 or ADC Analog Input 3 11 6 PD4/AIN4 I/O Port D4 or ADC Analog Input 4 12 7 PD5/AIN5 I/O Port D5 or ADC Analog Input 5 13 8 VDDA S Power Supply for analog peripheral (ADC) 14 15 9 10 VSSA PF0/CLKOUT S I/O Ground for analog peripheral (ADC) Port F0 or CPU Clock Output External Interrupt: EI1 16 11 PF1 I/O Port F1 External Interrupt: EI1 17 18 12 13 PF2 PF4/OCMP1_A I/O I/O Port F2 Port F4 or Timer A Output Compare 1 External Interrupt: EI1 7/101 7 ST72E311 ST72E311 ST72T311 ST72T311 Pin n° Pin n° QFP44 QFP44 SDIP42 SDIP42 Pin Name Type 19 14 PF6/ICAP1_A 20 15 PF7/EXTCLK_A I/O S Remarks Port F7 or External Clock on Timer A VDD_0 Main power supply 21 I/O Description Port F6 or Timer A Input Capture 1 22 23 16 VSS_0 PC0/OCMP2_B S I/O Ground Port C0 or Timer B Output Compare 2 24 17 PC1/OCMP1_B I/O Port C1 or Timer B Output Compare 1 25 26 18 19 PC2/ICAP2_B PC3/ICAP1_B I/O I/O Port C2 or Timer B Input Capture 2 Port C3 or Timer B Input Capture 1 27 20 PC4/MISO I/O Port C4 or SPI Master In / Slave Out Data 28 21 PC5/MOSI I/O Port C5 or SPI Master Out / Slave In Data 29 22 PC6/SCK I/O Port C6 or SPI Serial Clock 30 23 PC7/SS I/O Port C7 or SPI Slave Select 31 32 24 25 PA3 VDD_1 I/O S Port A3 Main power supply 33 26 VSS_1 S Ground 34 35 27 28 PA4 PA5 I/O I/O Port A4 Port A5 High Sink High Sink 36 29 PA6 I/O Port A6 High Sink 37 30 PA7 I/O Port A7 High Sink 38 31 TEST/VPP1) S Test mode pin. In the EPROM programming mode, this pin acts as the programming voltage input VPP. This pin must be tied low in user mode 39 32 RESET I/O Bidirectional. Active low. Top priority non maskable interrupt. 40 33 VSS_2 S Ground 41 34 OSCOUT O 42 43 35 36 OSCIN VDD_2 I S Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source to the on-chip oscillator. 44 37 PE0/TDO I/O Note 1: VPP on EPROM/OTP only. 8/101 8 Main power supply Port E0 or SCI Transmit Data Out External Interrupt: EI0 ST72E311 ST72E311 ST72T311 ST72T311 1.3 EXTERNAL CONNECTIONS The following figure shows the recommended external connections for the device. The VPP pin is only used for programming OTP and EPROM devices and must be tied to ground in user mode. The 10 nF and 0.1 µF decoupling capacitors on the power supply lines are a suggested EMC performance/cost tradeoff. The external reset network is intended to protect the device against parasitic resets, especially in noisy environments. Unused I/Os should be tied high to avoid any unnecessary power consumption on floating lines. An alternative solution is to program the unused ports as inputs with pull-up. Figure 6. Recommended External Connections VPP VDD 10nF VDD + 0.1µF VSS See A/D Converter Section Optional if Low Voltage Detector (LVD) is used VDDA VSSA V DD 4.7K 0.1µF RESET EXTERNAL RESET CIRCUIT 0.1µF See Clocks Section OSCIN OSCOUT Or configure unused I/O ports by software as input with pull-up VDD 10K Unused I/O 9/101 9 ST72E311 ST72E311 ST72T311 ST72T311 1.4 MEMORY MAP Figure 7. Program Memory Map 0080h Short Addressing RAM (zero page) 0000h HW Registers (see Table 4) 00FFh 0100h 007Fh 0080h 256 Bytes Stack/ 16-bit Addressing RAM 01FFh 384 Bytes RAM 01FFh 027Fh 512 Bytes RAM 0200h / 0280h 0080h 00FFh Reserved Short Addressing RAM (zero page) 0100h 256 Bytes Stack/ BFFFh 16-bit Addressing RAM C000h E000h FFDFh FFE 0h FFFF h 8K Bytes Program Memory 01FFh 16K Bytes Program Memoryl 0200h 027Fh 16-bit Addressing RAM Interrupt & Reset Vectors (see Table 3) Table 3. Interrupt Vector Map Vector Address Description FFE0-FFE1h Not Used FFE2-FFE3h Not Used FFE4-FFE5h Not Used Internal Interrupt FFE6-FFE7h SCI Interrupt Vector Internal Interrupt FFE8-FFE9h TIMER B Interrupt Vector Internal Interrupt FFEA-FFEBh TIMER A Interrupt Vector Internal Interrupt FFEC-FFEDh SPI interrupt vector Internal Interrupt FFEE-FFEFh Not Used FFF0-FFF1h External Interrupt Vector EI3 External Interrupt FFF2-FFF3h External Interrupt Vector EI2 External Interrupt FFF4-FFF5h External Interrupt Vector EI1 External Interrupt FFF6-FFF7h External Interrupt Vector EI0 External Interrupt FFF8-FFF9h Not Used FFFA-FF FBh Not Used FFFC-FFFDh TRAP (software) Interrupt Vector FFFE-FFFFh RESET Vector Remarks 10/101 10 CPU Interrupt ST72E311 ST72E311 ST72T311 ST72T311 Table 4. Hardware Register Memory Map Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h to 001Fh 0020h 0021h 0022h 0023h 0024h to 0029h 002Ah 002Bh 002Ch to 0030h Block Port A Register Label PADR PADDR PAOR Port C PCDR PCDDR PCOR Port B PBDR PBDDR PBOR Port E PEDR PEDDR PEOR Port D PDDR PDDDR PDOR Port F PFDR PFDDR PFOR Register Name Data Register Data Direction Register Option Register Reserved Area (1 byte) Data Register Data Direction Register Option Register Reserved Area (1 byte) Data Register Data Direction Register Option Register Reserved Area (1 byte) Data Register Data Direction Register Option Register Reserved Area (1 byte) Data Register Data Direction Register Option Register Reserved Area (1 byte) Data Register Data Direction Register Option Register Reset Status 00h 00h 00h Remarks R/W R/W R/W 1) 00h 00h 00h R/W R/W R/W 00h 00h 00h R/W R/W R/W 1) 00h 00h 0Ch R/W R/W R/W 1) 00h 00h 00h R/W R/W R/W 1) 00h 00h 28h R/W R/W R/W 1) 00h xxh xxh 00h R/W R/W Read Only Reserved Area (9 bytes) SPI MISCR SPIDR SPICR SPISR Miscellaneous Register SPI Data I/O Register SPI Control Register SPI Status Register Reserved Area (6 bytes) WDG WDGCR Watchdog Control Register 7Fh R/W WDGSR Watchdog Status Register 00h R/W 3) Reserved Area (5 bytes) 11/101 11 ST72E311 ST72E311 ST72T311 ST72T311 Address Block 0031h 0032h 0033h 0034h-0035h 0036h-0037h 0038h-0039h Timer A 003Ah-003Bh 003Ch-003Dh 003Eh-003Fh 0040h 0041h 0042h 0043h 0044h-0045h 0046h-0047h 0048h-0049h Timer B 004Ah-004Bh 004Ch-004Dh 004Eh-004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h to 006Fh 0070h 0071h 0072h to 007Fh SCI Register Label TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR Register Name Control Register2 Control Register1 Status Register Input Capture1 High Register Input Capture1 Low Register Output Compare1 High Register Output Compare1 Low Register Counter High Register Counter Low Register Alternate Counter High Register Alternate Counter Low Register Input Capture2 High Register Input Capture2 Low Register Output Compare2 High Register Output Compare2 Low Register Reserved Area (1 byte) Control Register2 Control Register1 Status Register Input Capture1 High Register Input Capture1 Low Register Output Compare1 High Register Output Compare1 Low Register Counter High Register Counter Low Register Alternate Counter High Register Alternate Counter Low Register Input Capture2 High Register Input Capture2 Low Register Output Compare2 High Register Output Compare2 Low Register SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved SCI Extended Transmit Prescaler Register Reset Status 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h Remarks R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only 2) Read Only 2) R/W 2) R/W 2) 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h C0h xxh 00x-xb xxh 00h 00h -00h R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W Read Only R/W R/W R/W R/W R/W Reserved R/W 00h 00h Read Only R/W Reserved Area (24 bytes) ADC ADCDR ADCCSR ADC Data Register ADC Control/Status Register Reserved Area (14 bytes) Notes: 1. The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value. 2. External pin not available. 3. Not used in versions without Low Voltage Detector Reset. 12/101 12 ST72E311 ST72E311 ST72T311 ST72T311 1.5 OPTION BYTE The user has the option to select software watchdog or hardware watchdog (see description in the Watchdog chapter). When programming EPROM or OTP devices, this option is selected in a menu by the user of the EPROM programmer before burning the EPROM/OTP. The Option Byte is located in a non-user map. No address has to be specified. The Option Byte is at FFh after UV erasure and must be properly programmed to set desired options. OPTBYTE 7 - 0 - - - b3 b2 - WDG Bit 7:4 = Not used Bit 3 = Reserved, must be cleared. Bit 2 = Reserved, must be set on ST72T311N ST72T311N devices and must be cleared on ST72T311J ST72T311J devices. Bit 1 = Not used Bit 0 = WDG Watchdog disable 0: The Watchdog is enabled after reset (Hardware Watchdog). 1: The Watchdog is not enabled after reset (Software Watchdog). 13/101 13 ST72E311 ST72E311 ST72T311 ST72T311 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 MAIN FEATURES s s s s s s s s 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt 2.3 CPU REGISTERS The 6 CPU registers shown in Figure 1 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB). Figure 8. CPU Registers 7 0 ACCUMULATOR RESET VALUE = XXh 7 0 X INDEX REGISTER RESET VALUE = XXh 7 0 Y INDEX REGISTER RESET VALUE = XXh 15 PCH 8 7 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 1 1 1 H I 0 N Z C CONDITIO N CODE REGISTER RESET VALUE = 1 1 1 X 1 X X X 15 8 7 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 14/101 14 ST72E311 ST72E311 ST72T311 ST72T311 CPU REGISTERS (Cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx 7 1 0 1 1 H I N Z because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. C The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. 15/101 15 ST72E311 ST72E311 ST72T311 ST72T311 CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01FFh 15 8 0 0 0 0 0 0 0 7 SP7 1 0 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 9). Since the stack is 256 bytes deep, the 8th most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 9. ­ When an interrupt is received, the SP is decremented and the context is pushed on the stack. ­ On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area. Figure 9. Stack Manipulation Example CALL Subroutine PUSH Y Interrupt Event POP Y RET or RSP IRET @ 0100h SP SP SP CC A Y CC A X X X PCH PCH PCH PCL PCL PCL PCH PCH PCH PCH PCH PCL PCL PCL PCL PCL SP @ 01FFh Stack Higher Address = 01FFh Stack Lower Address = 0100h 16/101 16 CC A SP SP ST72E311 ST72E311 ST72T311 ST72T311 3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES 3.1 CLOCK SYSTEM 3.1.1 General Description The MCU accepts either a crystal or ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (fCPU) is derived from the external oscillator frequency (f OSC). The external Oscillator clock is first divided by 2, and an additional division factor of 2, 4, 8, or 16 can be applied, in Slow Mode, to reduce the frequency of the fCPU; this clock signal is also routed to the onchip peripherals. The CPU clock signal consists of a square wave with a duty cycle of 50%. The internal oscillator is designed to operate with an AT-cut parallel resonant quartz crystal resonator in the frequency range specified for fosc. The circuit shown in Figure 11 is recommended when using a crystal, and Table 5 lists the recommended capacitance and feedback resistance values. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time. Use of an external CMOS oscillator is recommended when crystals outside the specified frequency ranges are to be used. 3.1.2 External Clock An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure 10. Table 5 Recommended Values for 16 MHz Crystal Resonator (C0 < 7pF) R SMAX 40 60 56pF 47pF 56pF 47pF 22pF RSMAX: Parasitic series resistance of the quartz crystal (upper limit). C0: Parasitic shunt capacitance of the quartz crystal (upper limit 7pF). COSCOUT , COSCIN: Maximum total capacitance on pins OSCIN and OSCOUT (the value includes the external capacitance tied to the pin plus the parasitic capacitance of the board and of the device). OSCOUT NC EXTERNAL CLOCK Figure 11. Crystal/Ceramic Resonator OSCIN OSCOUT COSCIN C OSCOUT Figure 12. Clock Prescaler Block Diagram 22pF COSCOUT OSCIN 150 COSCIN Figure 10. External Clock Source Connections %2 OSCIN COSCIN OSCOUT % 2, 4, 8, 16 fCPU to CPU and Peripherals COSCOUT 17/101 17 ST72E311 ST72E311 ST72T311 ST72T311 3.2 RESET 3.2.1 Introduction There are four sources of Reset: ­ RESET pin (external source) ­ Power-On Reset (Internal source) ­ WATCHDOG (Internal Source) ­ Low Voltage Detection Reset (internal source) The Reset Service Routine vector is located at address FFFEh-FFFFh. 3.2.2 External Reset The RESET pin is both an input and an open-drain output with integrated pull-up resistor. When one of the internal Reset sources is active, the Reset pin is driven low for a duration of tRESET to reset the whole application. 3.2.3 Reset Operation The duration of the Reset state is a minimum of 4096 internal CPU Clock cycles. During the Reset state, all I/Os take their reset value. A Reset signal originating from an external source must have a duration of at least tPULSE in order to be recognised. This detection is asynchronous and therefore the MCU can enter Reset state even in Halt mode. At the end of the Reset cycle, the MCU may be held in the Reset state by an External Reset signal. The RESET pin may thus be used to ensure VDD has risen to a point where the MCU can operate correctly before the user program is run. Following a Reset event, or after exiting Halt mode, a 4096 CPU Clock cycle delay period is initiated in order to allow the oscillator to stabilise and to ensure that recovery has taken place from the Reset state. In the high state, the RESET pin is connected internally to a pull-up resistor (RON). This resistor can be pulled low by external circuitry to reset the device. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to use the external connections shown in Figure 6. Figure 13. Reset Block Diagram INTERNAL TO ST7 RESET COUNTER RESET OSCILLATOR SIGNAL RESET VDD RON 18/101 18 POWER-ON RESET WATCHDOG RESET LOW VOLTAGE DETECTOR RESET ST72E311 ST72E311 ST72T311 ST72T311 RESET (Cont'd) 3.2.4 Low Voltage Detector Reset The on-chip Low Voltage Detector (LVD) generates a static reset when the supply voltage is below a reference value. The LVD functions both during power-on as well as when the power supply drops (brown-out). The reference value for a voltage drop is lower than the reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: VLVDUP when VDD is rising VLVDDOWN when VDD is falling Provided the minimun VDD value (guaranteed for the oscillator frequency) is above VLVDDOWN , the MCU can only be in two modes: - under full software control or - in static safe reset In this condition, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. In noisy environments, the power supply may drop for short periods and cause the Low Voltage Detector to generate a Reset too frequently. In such cases, it is recommended to use devices without the LVD Reset option and to rely on the watchdog function to detect application runaway conditions. Figure 14. Low Voltage Detector Reset Function VDD LOW VOLTAGE DETECTOR RESET RESET FROM WATCHDOG RESET Figure 15. Low Voltage Detector Reset Signal VLVDUP VLVDDOWN VDD RESET Note: See electrical characteristics for values of VLVDUP and VLVDDOWN Figure 16. Temporization timing diagram after an internal Reset VLVDUP VDD Temporization (4096 CPU clock cycles) Addresses $FFFE 19/101 19 ST72E311 ST72E311 ST72T311 ST72T311 4 INTERRUPTS The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 1. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: ­ Normal processing is suspended at the end of the current instruction execution. ­ The PC, X, A and CC registers are saved onto the stack. ­ The I bit of the CC register is set to prevent additional interrupts. ­ The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority Management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the "Exit from HALT" column in the Interrupt Mapping Table). 4.1 NON MASKABLE SOFTWARE INTERRUPT This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. 20/101 20 It will be serviced according to the flowchart on Figure 1. 4.2 EXTERNAL INTERRUPTS External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically ANDed and inverted before entering the edge/level detection block. Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of an ANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity. 4.3 PERIPHERAL INTERRUPTS Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: ­ The I bit of the CC register is cleared. ­ The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: ­ Writing "0" to the corresponding bit in the status register or ­ Access to the status register while the flag is set followed by a read or write of an associated register. Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is executed. ST72E311 ST72E311 ST72T311 ST72T311 INTERRUPTS (Cont'd) Figure 17. Interrupt Processing Flowchart FROM RESET I BIT SET? N N Y Y FETCH NEXT INSTR UCTION N IRET? Y INTE RRUPT PENDING ? STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTO R EXECU TE INSTRUCTION RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT 21/101 21 ST72E311 ST72E311 ST72T311 ST72T311 Table 6. Interrupt Mapping Source Block RESET TRAP EI0 EI1 EI2 EI3 SPI TIMER A TIMER B SCI 22/101 22 Description Reset Software NOT USED NOT USED Ext. Interrupt (Ports PA0:PA3) Ext. Interrupt (Ports PF0:PF2) Ext. Interrupt (Ports PB0:PB3) Ext. Interrupt (Ports PB4:PB7) NOT USED Transfer Complete Mode Fault Input Capture 1 Output Compare 1 Input Capture 2 Output Compare 2 Timer Overflow Input Capture 1 Output Compare 1 Input Capture 2 Output Compare 2 Timer Overflow Transmit Buffer Empty Transmit Complete Receive Buffer Full Idle Line Detect Overrun NOT USED NOT USED NOT USED Register Label Flag N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A SPISR TASR TBSR SCISR SPIF MODF ICF1_A OCF1_A ICF2_A OCF2_A TOF_A ICF1_B OCF1_B ICF2_B OCF2_B TOF_B TDRE TC RDRF IDLE OR Exit from HALT yes no yes Vector Address Priority Order FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh Highest Priority FFECh-FFEDh FFEAh-FFEBh no FFE8h-FFE9h FFE6h-FFE7h Lowest Priority FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h ST72E311 ST72E311 ST72T311 ST72T311 4.4 POWER SAVING MODES 4.4.1 Introduction There are three Power Saving modes. Slow Mode is selected by setting the relevant bits in the Miscellaneous register. Wait and Halt modes may be entered using the WFI and HALT instructions. Figure 18. WAIT Flow Chart WFI INSTRUCTION 4.4.2 Slow Mode In Slow mode, the oscillator frequency can be divided by a value defined in the Miscellaneous Register. The CPU and peripherals are clocked at this lower frequency. Slow mode is used to reduce power consumption, and enables the user to adapt clock frequency to available supply voltage. 4.4.3 Wait Mode Wait mode places the MCU in a low power consumption mode by stopping the CPU. All peripherals remain active. During Wait mode, the I bit (CC Register) is cleared, so as to enable all interrupts. All other registers and memory remain unchanged. The MCU will remain in Wait mode until an Interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the Interrupt or Reset Service Routine. The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 18 below. OSCILLATOR PERIPH. CLOCK CPU CLOCK ON ON OFF I-BIT CLEARED N RESET N Y INTERRUPT ON OSCILLATOR PERIPH. CLOCK CPU CLOCK ON ON I-BIT Y SET 4096 CPU CLOCK CYCLES DELAY OSCILLATOR PERIPH. CLOCK CPU CLOCK ON ON ON I-BIT SET FETCH RESET VECTOR OR SERVICE INTERRUPT Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped. 23/101 23 ST72E311 ST72E311 ST72T311 ST72T311 POWER SAVING MODES (Cont'd) 4.4.4 Halt Mode The Halt mode is the MCU lowest power consumption mode. The Halt mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. The Halt mode cannot be used when the watchdog is enabled, if the HALT instruction is executed while the watchdog system is enabled, a watchdog reset is generated thus resetting the entire MCU. When entering Halt mode, the I bit in the CC Register is cleared so as to enable External Interrupts. If an interrupt occurs, the CPU becomes active. The MCU can exit the Halt mode upon reception of an interrupt or a reset. Refer to the Interrupt Mapping Table. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 4096 CPU clock cycles. After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. Figure 19. HALT Flow Chart HALT INSTRUCTION WATCHDOG Y WDG ENABLED? RESET N OSCILLATOR PERIPH. CLOCK CPU CLOCK OFF OFF OFF I-BIT CLEARED N RESET N EXTERNAL INTERRUPT1) Y Y OSCILLATOR PERIPH. CLOCK2) CPU CLOCK ON OFF ON I-BIT SET 4096 CPU CLOCK CYCLES DELAY OSCILLATOR PERIPH. CLOCK CPU CLOCK ON ON ON I-BIT SET FETCH RESET VECTOR OR SERVICE INTERRUPT 1) or some specific interrupts 2) if reset PERIPH. CLOCK = ON ; if interrupt PERIPH. CLOCK = OFF Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped. 24/101 24 ST72E311 ST72E311 ST72T311 ST72T311 4.5 MISCELLANEOUS REGISTER The Miscellaneous register allows to select the SLOW operating mode, the polarity of external interrupt requests and to output the internal clock. Register Address: 0020h - Read/ Write Reset Value: 0000 0000 (00h) 7 0 PEI3 PEI2 MCO PEI1 PEI0 PSM1 PSM0 SMS Bit 7:6 = PEI[3:2] External Interrupt EI3 and EI2 Polarity Options. These bits are set and cleared by software. They determine which event on EI2 and EI3 causes the external interrupt according to Table 7. Table 7. EI2 and EI3 External Interrupt Polarity Options MODE PEI3 0 0 Falling edge only 1 0 Rising edge only 0 1 Rising and falling edge 1 1 Table 8. EI0 and EI1 External Interrupt Polarity Options MODE PEI1 PEI0 Falling edge and low level (Reset state) 0 0 Falling edge only 1 0 Rising edge only 0 1 Rising and falling edge 1 1 Note: Any modification of one of these two bits resets the interrupt request related to this interrupt vector. PEI2 Falling edge and low level (Reset state) Bit 4:3 = PEI[1:0] External Interrupt EI1 and EI0 Polarity Options. These bits are set and cleared by software. They determine which event on EI0 and EI1 causes the external interrupt according to Table 8. Note: Any modification of one of these two bits resets the interrupt request related to this interrupt vector. Bit 2:1 = PSM[1:0] Prescaler for Slow Mode These bits are set and cleared by software. They determine the CPU clock when the SMS bit is set according to the following table. Table 9. fCPU Value in Slow Mode fCPU Value PSM1 PSM0 Bit 5 = MCO Main Clock Out This bit is set and cleared by software. When set, it enables the output of the Internal Clock on the PPF0 I/O port. 0 - PF0 is a general purpose I/O port. 1 - MCO alternate function (fCPU is output on PF0 pin). fOSC / 4 0 0 fOSC / 16 0 1 fOSC / 8 1 0 fOSC / 32 1 1 Bit 0 = SMS Slow Mode Select This bit is set and cleared by software. 0: Normal Mode - fCPU = fOSC/ 2 (Reset state) 1: Slow Mode - the fCPU value is determined by the PSM[1:0] bits. 25/101 25 ST72E311 ST72E311 ST72T311 ST72T311 5 ON-CHIP PERIPHERALS 5.1 I/O PORTS 5.1.1 Introduction The I/O ports offer different functional modes: ­ transfer of data through digital inputs and outputs and for specific pins: ­ analog signal input (ADC) ­ alternate signal input/output for the on-chip peripherals. ­ external interrupt generation An I/O port is composed of up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 5.1.2 Functional Description Each port is associated to 2 main registers: ­ Data Register (DR) ­ Data Direction Register (DDR) and some of them to an optional register: ­ Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, for specific ports which do not provide this register refer to the I/O Port Implementation Section 4.1.3. The generic I/O block diagram is shown on Figure 21. 5.1.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. All the inputs are triggered by a Schmitt trigger. 2. When switching from input mode to output mode, the DR register should be written first to output the correct value as soon as the port is configured as an output. 26/101 26 Interrupt function When an I/O is configured in Input with Interrupt, an event on this I/O can generate an external Interrupt request to the CPU. The interrupt polarity is given independently according to the description mentioned in the Miscellaneous register or in the interrupt register (where available). Each pin can independently generate an Interrupt request. Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupts section). If several input pins are configured as inputs to the same interrupt vector, their signals are logically ANDed before entering the edge/level detection block. For this reason if one of the interrupt pins is tied low, it masks the other ones. 5.1.2.2 Output Mode The pin is configured in output mode by setting the corresponding DDR register bit. In this mode, writing "0" or "1" to the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Note: In this mode, the interrupt function is disabled. 5.1.2.3 Digital Alternate Function When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input mode. In this case, the pin's state is also digitally readable by addressing the DR register. Notes: 1. Input pull-up configuration can cause an unexpected value at the input of the alternate peripheral input. 2. When the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (DDR = 0). Warning: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. ST72E311 ST72E311 ST72T311 ST72T311 I/O PORTS (Cont'd) 5.1.2.4 Analog Alternate Function When the pin is used as an ADC input the I/O must be configured as input, floating. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. Warning : The analog input voltage level must be within the limits stated in the Absolute Maximum Ratings. 5.1.3 I/O Port Implementation The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input (see Figure 21) or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 20. Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Figure 20. Recommended I/O State Transition Diagram INPUT with interrupt INPUT no interrupt OUTPUT OUTPUT open-drain push-pull 27/101 27 ST72E311 ST72E311 ST72T311 ST72T311 I/O PORTS (Cont'd) Figure 21. I/O Block Diagram ALTERNATE ENABLE ALTERNATE 1 M OUTPUT U X 0 DATA BUS COMMON ANALOG RAIL DR LATCH VDD P-BUFFER (S EE TABLE BELOW) ALTERNATE ENABLE PULL-UP VDD DIODE (SEE TABLE BELOW) PULL-UP CONDITIO N DDR LATCH PAD OR LATCH ANALOG ENABLE (ADC) (SEE TABLE BELOW) ANALOG SWITCH (SEE N OTE BELOW) OR SEL GND DDR SEL N-BUFFER DR SEL M U X 1 ALTERNATE ENABLE GND 0 ALTERNATE INPUT CMOS EXTERNAL INTERRUPT SOURCE (EIx) POLARITY SEL FROM OTHER BITS SCHMITT TRIGGER Table 10. Port Mode Configuration Pull-up 0 1 0 not present 0 Legend: 0present, not activated 1present and activated Notes: ­ No OR Register on some ports (see register map). ­ ADC Switch on ports with analog alternate functions. 28/101 28 P-buffer 0 0 1 not present 0 V DD Diode 1 1 1 not present 1 Configuratio n Mode Floating Pull-up Push-pull True Open Drain Open Drain (logic level) ST72E311 ST72E311 ST72T311 ST72T311 I/O PORTS (Cont'd) Table 11. Port Configuration Port Pin name PA0:PA2 Port A Input (DDR = 0) Output (DDR = 1) PA3 OR = 0 OR = 1 OR = 0 OR =1 floating* pull-up with interrupt open-drain push-pull floating* 1) pull-up with interrupt open-drain push-pull PA4:PA7 PB0:PB4 floating* true open drain, high sink capability floating* pull-up with interrupt open-drain push-pull floating* pull-up with interrupt open-drain push-pull PC0:PC7 floating* pull-up open-drain push-pull PD0:PD5 floating* pull-up open-drain push-pull PD6:PD7 1) floating* pull-up open-drain push-pull PE0:PE1 floating* pull-up open-drain push-pull Port B PB5:PB7 Port C Port D Port E 1) PE4:PE7 1) true open drain, high sink capability3) floating*2) PF0:PF2 floating* pull-up with interrupt open-drain push-pull PF4, PF6, PF7 floating* pull-up open-drain push-pull Port F Notes: 1. ST72T311N ST72T311N only 2. For OTP/EPROM version, when OR=0: floating & when OR=1: reserved 3. For OTP/EPROM version, when OR=0: open-drain, high sink capability & when OR=1: reserved * Reset state (The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value). Warning: All bits of the DDR register which correspond to unconnected I/Os must be left at their reset value. They must not be modified by the user otherwise a spurious interrupt may be generated. 29/101 29 ST72E311 ST72E311 ST72T311 ST72T311 I/O PORTS (Cont'd) 5.1.4 Register Description 5.1.4.1 Data registers Port A Data Register (PADR) Port B Data Register (PBDR) Port C Data Register (PCDR) Port D Data Register (PDDR) Port E Data Register (PEDR) Port F Data Register (PFDR) Read/Write Reset Value: 0000 0000 (00h) 5.1.4.3 Option registers Port A Option Register (PAOR) Port B Option Register (PBOR) Port C Option Register (PBOR) Port D Option Register (PBOR) Port E Option Register (PBOR) Port F Option Register (PFOR) Read/Write Reset Value: see Register Memory Map Table 4 7 D7 0 D6 D5 D4 D3 D2 D1 7 D0 O7 Bit 7:0 = D7-D0 Data Register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken in account even if the pin is configured as an input. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). 5.1.4.2 Data direction registers Port A Data Direction Register (PADDR) Port B Data Direction Register (PBDDR) Port C Data Direction Register (PCDDR) Port D Data Direction Register (PDDDR) Port E Data Direction Register (PEDDR) Port F Data Direction Register (PFDDR) Read/Write Reset Value: 0000 0000 (00h) (input mode) 7 DD7 0 DD6 DD5 DD4 DD3 DD2 DD1 DD0 Bit 7:0 = DD7-DD0 Data Direction Register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bits is set and cleared by software. 0: Input mode 1: Output mode 30/101 30 0 O6 O5 O4 O3 O2 O1 O0 Bit 7:0 = O7-O0 Option Register 8 bits. The OR register allow to distinguish in input mode if the interrupt capability or the floating configuration is selected. In output mode it select push-pull or open-drain capability. Each bit is set and cleared by software. Input mode: 0: floating input 1: input pull-up with interrupt Output mode: 0: open-drain configuration 1: push-pull configuration ST72E311 ST72E311 ST72T311 ST72T311 I/O PORTS (Cont'd) Table 12. I/O Port Register Map Address (Hex.) Register Label 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 0000h PADR 0001h PADDR 0002h PAOR O7 O6 O5 O4 O3 O2 O1 O0 0004h PCDR D7 D6 D5 D4 D3 D2 D1 D0 0005h PCDDR DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 0006h PCOR O7 O6 O5 O4 O3 O2 O1 O0 0008h PBDR D7 D6 D5 D4 D3 D2 D1 D0 0009h PBDDR DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 000Ah PBOR O7 O6 O5 O4 O3 O2 O1 O0 000Ch PEDR D7 D6 D5 D4 D3 D2 D1 D0 000Dh PEDDR DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 000Eh PEOR O7 O6 O5 O4 O3 O2 O1 O0 0010h PDDR D7 D6 D5 D4 D3 D2 D1 D0 0011h PDDDR DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 0012h PDOR O7 O6 O5 O4 O3 O2 O1 O0 0014h PFDR D7 D6 D5 D4 D3 D2 D1 D0 0015h PFDDR DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 0016h PFOR O7 O6 O5 O4 O3 O2 O1 O0 31/101 31 ST72E311 ST72E311 ST72T311 ST72T311 5.2 WATCHDOG TIMER (WDG) 5.2.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. 5.2.2 Main Features s Programmable timer (64 increments of 12288 CPU cycles) s Programmable reset s Reset (if watchdog activated) after a HALT instruction or when the T6 bit reaches zero s s Hardware Watchdog selectable by option byte Watchdog Reset indicated by status flag (in versions with Safe Reset option only) 5.2.3 Functional Description The counter value stored in the CR register (bits T[6:0]), is decremented every 12,288 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. Figure 22. Watchdog Block Diagram RESET WATCHDOG CONTROL REGISTER (CR) WDGA T6 T5 T4 T3 T2 7-BIT DOWNCOUNTER fCPU 32/101 32 CLOCK DIVIDER ÷12288 T1 T0 ST72E311 ST72E311 ST72T311 ST72T311 WATCHDOG TIMER (Cont'd) The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see Table 1): ­ The WDGA bit is set (watchdog enabled) ­ The T6 bit is set to prevent generating an immediate reset ­ The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. Table 13.Watchdog Timing (fCPU = 8 MHz) CR Register initial value WDG timeout period (ms) Max FFh 98.304 Min C0h 1.536 Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). If the watchdog is activated, the HALT instruction will generate a Reset. 5.2.4 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. Refer to the device-specific Option Byte description. 5.2.5 Low Power Modes Mode WAIT Description No effect on Watchdog. HALT Immediate reset generation as soon as the HALT instruction is executed if the Watchdog is activated (WDGA bit is set). 5.2.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0111 1111 (7Fh) 7 0 WDGA T6 T5 T4 T3 T2 T1 T0 Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). STATUS REGISTER (SR) Read/Write Reset Value*: 0000 0000 (00h) 7 - 0 - - - - - - WDOGF Bit 0 = WDOGF Watchdog flag. This bit is set by a watchdog reset and cleared by software or a power on/off reset. This bit is useful for distinguishing power/on off or external reset and watchdog reset. 0: No Watchdog reset occurred 1: Watchdog reset occurred * Only by software and power on/off reset Note: This register is not used in versions without LVD Reset. 5.2.6 Interrupts None. 33/101 33 ST72E311 ST72E311 ST72T311 ST72T311 Table 14. WDG Register Map Address (Hex.) Register Label 7 6 5 4 3 2 1 0 2A WDGCR Reset Value WDGA 0 T6 1 T5 1 T4 1 T3 1 T2 1 T1 1 T0 1 2B WDGSR Reset Value 0 0 0 0 0 0 0 WDOGF 0 34/101 34 ST72E311 ST72E311 ST72T311 ST72T311 5.3 16-BIT 16-BIT TIMER 5.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of up to two input signals (input capture) or generating up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 5.3.2 Main Features s Programmable prescaler: fCPU divided by 2, 4 or 8. s Overflow status flag and maskable interrupt s External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge s Output compare functions with: ­ 2 dedicated 16-bit registers ­ 2 dedicated programmable signals ­ 2 dedicated status flags ­ 1 dedicated maskable interrupt s Input capture functions with: ­ 2 dedicated 16-bit registers ­ 2 dedicated active edge selection signals ­ 2 dedicated status flags ­ 1 dedicated maskable interrupt s Pulse Width Modulation mode (PWM) s One Pulse mode s 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* 5.3.3 Functional Description 5.3.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): ­ Counter High Register (CHR) is the most significant byte (MS Byte). ­ Counter Low Register (CLR) is the least significant byte (LS Byte). Alternate Counter Register (ACR) ­ Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). ­ Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register (SR). (See note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 1. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU /4, fCPU/8 or an external frequency. The Block Diagram is shown in Figure 1. *Note: Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be `1'. 35/101 35 ST72E311 ST72E311 ST72T311 ST72T311 16-BIT 16-BIT TIMER (Cont'd) Figure 23. Timer Block Diagram ST7 INTERNAL BUS fCPU MCU-PERIPHERAL INTERFACE 8 low 8 8 8 low low 8 high 8 8 high EXEDG 8 low high 8 high 8-bit buffer low 8 high 16 1/2 1/4 REGISTER 1/8 OUTPUT COMPARE REGISTER 2 OUTPUT COMPARE REGISTER 1 COUNTER ALTERNATE COUNTER REGISTER EXTCLK pin INPUT CAPTURE REGISTER 1 INPUT CAPTURE REGISTER 2 16 16 16 CC[1:0] TIMER INTERNAL BUS 16 16 OVERFLOW DETECT CIRCUIT 6 EDGE DETECT CIRCUIT1 ICAP1 pin EDGE DETECT CIRCUIT2 OUTPUT COMPARE CIRCUIT ICAP2 pin LATCH1 ICF1 OCF1 TOF ICF2 OCF2 0 0 OCMP1 pin LATCH2 OCMP2 pin 0 (Status Register) SR ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 (Control Register 1) CR1 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG (Control Register 2) CR2 (See note) TIMER INTERRUPT 36/101 36 Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table) ST72E311 ST72E311 ST72T311 ST72T311 16-BIT 16-BIT TIMER (Cont'd) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence At t0 Read MS Byte LS Byte is buffered Other instructions Read At t0 +t LS Byte Returns the buffered LS Byte value at t0 Sequence completed The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: ­ The TOF bit of the SR register is set. ­ A timer interrupt is generated if: ­ TOIE bit of the CR1 register is set and ­ I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true. Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Note: The TOF bit is not cleared by accessing the ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset). 5.3.3.2 External Clock The external clock (where available) is selected if CC0=1 and CC1=1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronised with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency. 37/101 37 ST72E311 ST72E311 ST72T311 ST72T311 16-BIT 16-BIT TIMER (Cont'd) Figure 24. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK FFFD FFFE FFFF 0000 COUNTER REGISTER 0001 0002 0003 TIMER OVERFLOW FLAG (TOF) Figure 25. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000 0001 TIMER OVERFLOW FLAG (TOF) Figure 26. Counter Timing Diagram, internal clock divided by 8 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000 TIMER OVERFLOW FLAG (TOF) Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running. 38/101 38 ST72E311 ST72E311 ST72T311 ST72T311 16-BIT 16-BIT TIMER (Cont'd) 5.3.3.3 Input Capture In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected by the ICAP i pin (see figure 5). ICiR MS Byte ICiHR LS Byte ICiLR The ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the input capture function, select the following in the CR2 register: ­ Select the timer clock (CC[1:0]) (see Table 1). ­ Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as a floating input). And select the following in the CR1 register: ­ Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin ­ Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as a floating input). When an input capture occurs: ­ The ICFi bit is set. ­ The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 6). ­ A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, the transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. In One Pulse mode and PWM mode only the input capture 2 function can be used. 5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input capture function. Moreover if one of the ICAPi pin is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with an interrupt in order to measure events that exceed the timer range (FFFFh). 39/101 39 ST72E311 ST72E311 ST72T311 ST72T311 16-BIT 16-BIT TIMER (Cont'd) Figure 27. Input Capture Block Diagram ICAP1 pin ICAP2 pin (Control Register 1) CR1 EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1 ICIE IEDG1 (Status Register) SR IC2R Register IC1R Register ICF1 ICF2 0 16-BIT 16-BIT FREE RUNNING CC1 CC0 COUNTER Figure 28. Input Capture Timing Diagram TIMER CLOCK FF01 FF02 FF03 ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: Active edge is rising edge. 40/101 40 0 (Control Register 2) CR2 16-BIT 16-BIT COUNTER REGISTER 0 FF03 IEDG2 ST72E311 ST72E311 ST72T311 ST72T311 16-BIT 16-BIT TIMER (Cont'd) 5.3.3.4 Output Compare In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: ­ Assigns pins with a programmable value if the OCIE bit is set ­ Sets a flag in the status register ­ Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle. OCiR MS Byte OCiHR LS Byte OCiLR These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0] ). Procedure: To use the output compare function, select the following in the CR2 register: ­ Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. ­ Select the timer clock (CC[1:0]) (see Table 1). And select the following in the CR1 register: ­ Select the OLVL i bit to applied to the OCMPi pins after the match occurs. ­ Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: ­ OCFi bit is set. ­ The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). ­ A timer interrupt is generated if the OCIE bit is set in the CR2 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula: OCiR = t * fCPU PRESC Where: t = Output compare period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 1) If the timer clock is an external clock, the formula is: OCiR = t * fEXT Where: t = Output compare period (in seconds) fEXT = External timer clock frequency (in hertz) Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: ­ Write to the OCiHR register (further compares are inhibited). ­ Read the SR register (first step of the clearance of the OCFi bit, which may be already set). ­ Write to the OCiLR register (enables the output compare function and clears the OCFi bit). 41/101 41 ST72E311 ST72E311 ST72T311 ST72T311 16-BIT 16-BIT TIMER (Cont'd) Notes: 1. After a processor write cycle to the OCi HR register, the output compare function is inhibited until the OCiLR register is also written. 2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3. When the timer clock is fCPU/2, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 8). This behaviour is the same in OPM or PWM mode. When the timer clock is fCPU/4, fCPU/8 or in external clock mode, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see Figure 9). 4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5. The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. Forced Compare Output capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. FOLVLi bits have no effect in either One-Pulse mode or PWM mode. Figure 29. Output Compare Block Diagram 16 BIT FREE RUNNING COUNTER OC1E OC2E CC1 CC0 (Control Register 2) CR2 16-bit (Control Register 1) CR1 OUTPUT COMPARE CIRCUIT 16-bit OCIE FOLV2 FOLV1 OLVL2 OLVL1 16-bit Latch 2 OC1R Register OCF1 OCF2 0 0 0 OC2R Register (Status Register) SR 42/101 42 Latch 1 OCMP1 Pin OCMP2 Pin ST72E311 ST72E311 ST72T311 ST72T311 16-BIT 16-BIT TIMER (Cont'd) Figure 30. Output Compare Timing Diagram, fTIMER =fCPU/2 INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 OUTPUT COMPARE REGISTER i (OCR i) 2ED3 OUTPUT COMPARE FLAG i (OCF i) OCMPi PIN (OLVLi=1) Figure 31. Output Compare Timing Diagram, fTIMER =fCPU/4 INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCR i) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3 COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 43/101 43 ST72E311 ST72E311 ST72T311 ST72T311 16-BIT 16-BIT TIMER (Cont'd) 5.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use One Pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2. Select the following in the CR1 register: ­ Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. ­ Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. ­ Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: ­ Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. ­ Set the OPM bit. ­ Select the timer clock CC[1:0] (see Table 1). One Pulse mode cycle When event occurs on ICAP1 OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set When Counter = OC1R OCMP1 = OLVL1 Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and the OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set. 44/101 44 Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the following formula: OCiR Value = t * fCPU -5 PRESC Where: t = Pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 1) If the timer clock is an external clock the formula is: OCiR = t * f EXT -5 Where: t = Pulse period (in seconds) fEXT = External timer clock frequency (in hertz) When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin (see Figure 10). Notes: 1. The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. 3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5. When One Pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the OLVL2 level is dedicated to One Pulse mode. ST72E311 ST72E311 ST72T311 ST72T311 16-BIT 16-BIT TIMER (Cont'd) Figure 32. One Pulse Mode Timing Example COUNTER FFFC FFFD FFFE 2ED0 2ED1 2ED2 FFFC FFFD 2ED3 ICAP1 OLVL2 OCMP1 OLVL1 OLVL2 compare1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 33. Pulse Width Modulation Mode Timing Example COUNTER 34E2 FFFC FFFD FFFE 2ED0 2ED1 2ED2 OLVL2 OCMP1 compare2 OLVL1 compare1 34E2 FFFC OLVL2 compare2 Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1 45/101 45 ST72E311 ST72E311 ST72T311 ST72T311 16-BIT 16-BIT TIMER (Cont'd) 5.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so these functions cannot be used when the PWM mode is activated. Procedure To use Pulse Width Modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corresponding to the period of the pulse if OLVL1=0 and OLVL2=1, using the formula in the opposite column. 3. Select the following in the CR1 register: ­ Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC1R register. ­ Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC2R register. 4. Select the following in the CR2 register: ­ Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. ­ Set the PWM bit. ­ Select the timer clock (CC[1:0]) (see Table 1). If OLVL1=1 and OLVL2=0, the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. Pulse Width Modulation cycle When Counter = OC1R When Counter = OC2R OCMP1 = OLVL1 OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set 46/101 46 The OCiR register value required for a specific timing application can be calculated using the following formula: OCiR Value = t * fCPU -5 PRESC Where: t = Signal or pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 1) If the timer clock is an external clock the formula is: OCiR = t * f EXT -5 Where: t = Signal or pulse period (in seconds) = External timer clock frequency (in hertz) fEXT The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 11) Notes: 1. After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode, therefore the Output Compare interrupt is inhibited. 3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected from the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset after each period and ICF1 can also generate an interrupt if ICIE is set. 5. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. ST72E311 ST72E311 ST72T311 ST72T311 16-BIT 16-BIT TIMER (Cont'd) 5.3.4 Low Power Modes Mode WAIT HALT Description No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with "exit from HALT mode" capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register. 5.3.5 Interrupts Event Flag Interrupt Event Input Capture 1 event/Counter reset in PWM mode Input Capture 2 event Output Compare 1 event (not available in PWM mode) Output Compare 2 event (not available in PWM mode) Timer Overflow event ICF1 ICF2 OCF1 OCF2 TOF Enable Control Bit ICIE OCIE TOIE Exit from Wait Yes Yes Yes Yes Yes Exit from Halt No No No No No Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 5.3.6 Summary of Timer modes MODES Input Capture (1 and/or 2) Output Compare (1 and/or 2) One Pulse mode PWM Mode 1) 2) 3) Input Capture 1 Yes Yes No No AVAILABLE RESOURCES Input Capture 2 Output Compare 1 Output Compare 2 Yes Yes Yes Yes Yes Yes Not Recommended 1) Not Recommended 3) No No Partially 2) No See note 4 in Section 0.1.3.5 One Pulse Mode See note 5 in Section 0.1.3.5 One Pulse Mode See note 4 in Section 0.1.3.6 Pulse Width Modulation Mode 47/101 47 ST72E311 ST72E311 ST72T311 ST72T311 16-BIT 16-BIT TIMER (Cont'd) 5.3.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h) 7 0 Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1