ST72260G ST72262G ST72264G 16-BIT SDIP32 ST72260G1 ST72262G1 ST72262G2 - Datasheet Archive

 

ST72264G 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES s s s s s Memories ­ 4 K or 8

 

ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT 16-BIT TIMERS, I2C, SPI, SCI INTERFACES s s s s s Memories ­ 4 K or 8 Kbytes Program memory: ROM or Single voltage extended Flash (XFlash) with read-out protection write protection and InCircuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention: 20 years at 55°C. ­ 256 bytes RAM Clock, Reset and Supply Management ­ Enhanced reset system ­ Enhanced low voltage supply supervisor (LVD) with 3 programmable levels and auxiliary voltage detector (AVD) with interrupt capability for implementing safe power-down procedures ­ Clock sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock ­ PLL for 2x frequency multiplication ­ Clock-out capability ­ 4 Power Saving Modes: Halt, Active Halt,Wait and Slow Interrupt Management ­ Nested interrupt controller ­ 10 interrupt vectors plus TRAP and RESET ­ 22 external interrupt lines (on 2 vectors) 22 I/O Ports ­ 22 multifunctional bidirectional I/O lines ­ 20 alternate function lines ­ 8 high sink outputs 4 Timers ­ Main Clock Controller with Real time base and Clock-out capabilities ­ Configurable watchdog timer SDIP32 SDIP32 SO28 LFBGA 6x6mm s s s s ­ Two 16-bit timers with: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes 3 Communications Interfaces ­ SPI synchronous serial interface ­ I2C multimaster interface ­ SCI asynchronous serial interface (LIN compatible) 1 Analog peripheral ­ 10-bit ADC with 6 input channels Instruction Set ­ 8-bit data manipulation ­ 63 basic instructions ­ 17 main addressing modes ­ 8 x 8 unsigned multiply instruction Development Tools ­ Full hardware/software development package Device Summary Features Program memory - bytes RAM (stack) - bytes Peripherals Operating Supply CPU Frequency Operating Temperature Packages ST72260G1 ST72260G1 ST72262G1 ST72262G1 ST72262G2 ST72262G2 ST72264G1 ST72264G1 ST72264G2 ST72264G2 4K 4K 8K 4K 8K 256 (128) Watchdog timer, RTC, Two16-bit timers, SPI Watchdog timer, RTC Two 16-bit timers, SPI, ADC Watchdog timer, RTC Two 16-bit timers, SPI, SCI, I2C, ADC 2.4 V to 5.5 V Up to 8 MHz (with oscillator up to 16 MHz) PLL 4/8 Mhz -40° C to +85° C SO28 / SDIP32 SDIP32 0° C to +70° C LFBGA Rev. 1.7 August 2003 1/171 1 Table of Contents ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.5 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.5 9.6 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 . 41 . 9.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2/171 2 Table of Contents 9.8 I/O PORT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.3 MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (MCC/RTC) . . . . . . . . . . . . . 53 11.3 16-BIT 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 11.6 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.7 10-BIT 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 149 13.12 10-BIT 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 157 15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 159 15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 ERRATA SHEET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 3/171 3 ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G 17 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 REFERENCE SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SILICON LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.1 EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 166 166 166 19.2 I/O PORT B AND C CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 19.3 16-BIT 16-BIT TIMER PWM MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 19.4 SPI MULTIMASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 19.5 MINIMUM OPERATING VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 19.6 CSS FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 67 19.7 INTERNAL AND EXTERNAL RC OSCILLATOR WITH LVD . . . . . . . . . . . . . . . . . . . . 167 19.8 EXTERNAL CLOCK WITH PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 19.9 HALT MODE POWER CONSUMPTION WITH ADC ON . . . . . . . . . . . . . . . . . . . . . . . 168 19.10 ACTIVE HALT WAKE-UP BY EXTERNAL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . 168 19.11 A/D CONVERTER ACCURACY FOR FIRST CONVERSION . . . . . . . . . . . . . . . . . . . . 168 19.12 NEGATIVE INJECTION IMPACT ON ADC ACCURACY . . . . . . . . . . . . . . . . . . . . . . . 168 19.13 ADC CONVERSION SPURIOUS RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 19.14 FUNCTIONAL EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 20 DEVICE MARKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 21 ERRATA SHEET REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 To obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet Please note that an errata sheet can be found at the end of this document on page 166. 4/171 ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G 1 INTRODUCTION with byte-by-byte In-Circuit Programming (ICP) capabilities. Under software control, all devices can be placed in WAIT, SLOW, Active-HALT or HALT mode, reducing power consumption when the application is in idle or stand-by state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. For easy reference, all parametric data is located in Section 13 on page 122. The ST72260G ST72260G, ST72262G ST72262G and ST72264G ST72264G devices are members of the ST7 microcontroller family. They can be grouped as follows : ­ ST72264G ST72264G devices are designed for mid-range applications with ADC, I2C and SCI interface capabilities. ­ ST72262G ST72262G devices target the same range of applications but without I2C interface or SCI. ­ ST72260G ST72260G devices are for applications that do not need ADC, I2C peripherals or SCI. All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set. The ST72F260G ST72F260G, ST72F262G ST72F262G, and ST72F264G ST72F264G versions feature single-voltage FLASH memory Figure 1. General Block Diagram OSC1 OSC2 MULTI OSC + CLOCK FILTER Internal CLOCK I2C* SCI* MCC/RTC PORT A PA7:0 (8 bits) LVD VDD RESET CONTROL 8-BIT CORE ALU PROGRAM MEMORY (4 or 8K Bytes) RAM (256 Bytes) ICD ADDRESS AND DATA BUS VSS POWER SUPPLY SPI PORT B PB7:0 (8 bits) 16-BIT 16-BIT TIMER A PORT C PC5:0 (6 bits) 10-BIT 10-BIT ADC* 16-BIT 16-BIT TIMER B WATCHDOG *Not available on some devices, see device summary on page 1. 5/171 ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G 2 PIN DESCRIPTION Figure 2. 28-Pin SO Package Pinout RESET 1 28 VDD OSC1 OSC2 2 27 VSS 3 26 ICCSEL SS/PB7 4 25 PA0 (HS)/ICCCLK SCK/PB6 5 24 PA1 (HS)/ICCDATA MISO/PB5 6 23 PA2 (HS) 22 PA3 (HS) 21 PA4 (HS)/SCLI3 MOSI/PB4 7 OCMP2_A/PB3 8 ICAP2_A/PB2 9 20 PA5(HS)/RDI3 OCMP1_A/PB1 ICAP1_A/PB0 10 19 11 18 PA6 (HS)/SDAI3 PA7 (HS)/TDO3 AIN5/EXTCLK_A/PC5 12 17 2 ei1 AIN4 /OCMP2_B/PC4 13 AIN32/ICAP2 AIN32/ICAP2_B/PC3 ei0 16 15 14 ei0 or ei11 PC0/ICAP1_B/AIN02 B/AIN02 PC1/OCMP1_B/AIN12 B/AIN12 PC2/MCO/AIN22 PC2/MCO/AIN22 (HS) 20mA high sink capability eiX associated external interrupt vector 1 Configurable by option byte Alternate function not available on ST72260 ST72260 3 Alternate function not available on ST72260 ST72260 and ST72262 ST72262 2 Figure 3. 32-Pin SDIP Package Pinout RESET 32 1 VDD OSC1 OSC2 2 31 VSS 3 30 SS/PB7 4 29 ICCSEL PA0 (HS)/ICCCLK SCK/PB6 5 28 PA1 (HS)/ICCDATA MISO/PB5 MOSI/PB4 NC 6 27 7 26 PA2 (HS) PA3 (HS) 8 25 NC 9 24 10 23 NC NC PA4 (HS)/SCLI3 22 PA5 (HS)/RDI3 21 18 PA6 (HSI/SDAI3 PA7 (HS)/TDO3 PC0/ICAP1_B/AIN02 B/AIN02 PC1/OCMP1_B/AIN12 B/AIN12 17 PC2/MCO/AIN22 PC2/MCO/AIN22 OCMP2_A/PB3 ICAP2_A/PB2 11 OCMP1_A/PB1 12 ICAP1_A/PB0 ei0 14 AIN32/ICAP2 AIN32/ICAP2_B/PC3 ei1 ei0 13 AIN52/EXTCLK AIN52/EXTCLK_A/PC5 AIN42/OCMP2 AIN42/OCMP2_B/PC4 ei1 16 15 20 19 ei0 or ei1 1 1 Configurable by option byte Alternate function not available on ST72260 ST72260 3 Alternate function not available on ST72260 ST72260 and ST72262 ST72262 2 6/171 (HS) 20mA high sink capability eiX associated external interrupt vector ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G Figure 4. TFBGA Package Pinout (view through package) 1 2 3 4 5 6 A B C D E F 7/171 ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G PIN DESCRIPTION (Cont'd) For external pin connection guidelines, refer to Section 13 "ELECTRICAL CHARACTERISTICS" on page 122. Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: CT= CMOS 0.3 VDD/0.7 VDD with input trigger Output level: HS = 20 mA high sink (on N-buffer only) Port and control configuration: ­ Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog ­ Output: OD = open drain 2), PP = push-pull Refer to Section 9 "I/O PORTS" on page 38 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Table 1. Device Pin Description Level Port / Control Main Output Function (after reset) I 3 3 B3 OSC2 3) O 4 4 A2 PB7/SS I/O CT X ei1 X X Port B7 SPI Slave Select (active low) 5 5 A1 PB6/SCK I/O CT X ei1 X X Port B6 SPI Serial Clock 6 6 B1 PB5/MISO I/O CT X ei1 X X Port B5 SPI Master In/ Slave Out Data 7 7 B2 PB4/MOSI I/O CT X ei1 X X Port B4 SPI Master Out / Slave In Data 8 PP Input C2 NC Alternate Function Top priority non maskable interrupt (active low) External clock input or Resonator oscillator inverter input or resistor input for RC oscillator Resonator oscillator inverter output or capacitor input for RC oscillator X C1 NC 9 X OD C4 OSC1 3) ana 2 int 2 I/O CT wpu A3 RESET float 1 Pin Name Output 1 BGA SO28 Input SDIP32 SDIP32 Type Pin n° Not Connected D1 NC 10 8 C3 PB3/OCMP2_A I/O CT X ei1 X X Port B3 Timer A Output Compare 2 11 9 D2 PB2/ICAP2_A I/O CT X ei1 X X Port B2 Timer A Input Capture 2 12 10 E1 PB1 /OCMP1_A I/O CT X ei1 X X Port B1 Timer A Output Compare 1 13 11 F1 PB0 /ICAP1_A I/O CT X ei1 X X Port B0 Timer A Input Capture 1 14 12 F2 PC5/EXTCLK_A/AIN5 I/O CT X ei0/ei1 X X X Port C5 15 13 E2 PC4/OCMP2_B/AIN4 I/O CT X ei0/ei1 X X X Port C4 16 14 F3 PC3/ ICAP2_B/AIN3 I/O CT X ei0/ei1 X X X Port C3 8/171 Timer A Input Clock or ADC Analog Input 5 Timer B Output Compare 2 or ADC Analog Input 4 Timer B Input Capture 2 or ADC Analog Input 3 ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G Pin n° Port / Control Type float wpu OD PP 17 15 E3 PC2/MCO/AIN2 I/O CT X ei0/ei1 X X X Port C2 18 16 F4 PC1/OCMP1_B/AIN1 I/O CT X ei0/ei1 X X X Port C1 19 17 D3 PC0/ICAP1_B/AIN0 I/O CT X ei0/ei1 X X X Port C0 20 18 E4 PA7/TDO I/O CT HS X X X Port A7 SCI output 21 19 F5 PA6/SDAI I/O CT HS X Port A6 I2C DATA 22 20 F6 PA5 /RDI I/O CT HS X Port A5 SCI input 23 21 E6 PA4/SCLI I/O CT HS X Port A4 I2C CLOCK 24 ei0 ei0 ei0 ei0 D6 NC ana int Input Input T X X T Alternate Function Main clock output (fCPU) or ADC Analog Input 2 Timer B Output Compare 1 or ADC Analog Input 1 Timer B Input Capture 1 or ADC Analog Input 0 E5 NC 25 Output Pin Name BGA SO28 Main Output Function (after reset) SDIP32 SDIP32 Level Not Connected D5 NC 26 22 C6 PA3 I/O CT HS X ei0 X X Port A3 27 23 D4 PA2 I/O CT HS X ei0 X X Port A2 C5 NC Not Connected B6 NC 28 24 A6 PA1/ICCDATA I/O CT HS X ei0 X X Port A1 In Circuit Communication Data 29 25 A5 PA0/ICCCLK I/O CT HS X ei0 X X Port A0 In Circuit Communication Clock 30 26 B5 ICCSEL I 31 27 A4 VSS S Ground 32 28 B4 VDD S Main power supply CT X ICC mode pin, must be tied low Notes: 1. In the interrupt input column, "eiX" defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is a pull-up interrupt input, otherwise the configuration is a floating interrupt input. Port C is mapped to ei0 or ei1 by option byte. 2. In the open drain output column, "T" defines a true open drain I/O (P-Buffer and protection diode to VDD are not implemented). See Section 9 "I/O PORTS" on page 38 for more details. 3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to the on-chip oscillator see Section 2 "PIN DESCRIPTION" on page 6 and Section 6.2 "MULTI-OSCILLATOR (MO)" on page 21 for more details. 9/171 ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G 3 REGISTER & MEMORY MAP As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register location, 256 bytes of RAM and up to 8 Kbytes of user program memory. The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh. The highest address bytes contain the user reset and interrupt vectors. The Flash memory contains two sectors (see Figure 5) mapped in the upper part of the ST7 ad- dressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh). The size of Flash Sector 0 and other device options are configurable by Option byte (refer to Section 15.1 on page 157). IMPORTANT: Memory locations marked as "Reserved" must never be accessed. Accessing a reseved area can have unpredictable effects on the device. Figure 5. Memory Map 0000h HW Registers (see Table 2) 0080h RAM (256 Bytes) 00FFh 0100h 007Fh 0080h 017Fh 0180h 017Fh E000h Program Memory (4K, 8 KBytes) FFDFh FFE0h FFFFh 10/171 EFFFh F000h FFFFh Interrupt & Reset Vectors (see Table 5 on page 32) Stack or 16-bit Addressing RAM (128 Bytes) 8K FLASH PROGRAM MEMORY Reserved DFFFh E000h Short Addressing RAM Zero page (128 Bytes) 4 Kbytes SECTOR 1 4 Kbytes SECTOR 0 ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G Table 2. Hardware Register Map Address 0000h 0001h 0002h Block Port C Register Label PCDR PCDDR PCOR Register Name Port C Data Register Port C Data Direction Register Port C Option Register 0003h 0004h 0005h 0006h Remarks xx000000h1) R/W 2) 00h R/W 2) 00h R/W 2) Reserved (1 Byte) Port B PBDR PBDDR PBOR Port B Data Register Port B Data Direction Register Port B Option Register 0007h 0008h 0009h 000Ah Reset Status 00h 1) 00h 00h R/W R/W R/W. 00h 1) 00h 00h R/W R/W Reserved (1 Byte) Port A PADR PADDR PAOR Port A Data Register Port A Data Direction Register Port A Option Register 000Bh to 001Bh R/W Reserved (17 Bytes) 001Ch ISPR0 Interrupt software priority register0 FFh R/W 001Dh ISPR1 Interrupt software priority register1 FFh R/W 001Eh ITC ISPR2 Interrupt software priority register2 FFh R/W 001Fh ISPR3 Interrupt software priority register3 FFh R/W 0020h MISCR1 Miscellanous register 1 00h R/W 0021h 0022h 0023h SPI SPIDR SPICR SPICSR SPI Data I/O Register SPI Control Register SPI Status Register xxh 0xh 00h R/W R/W R/W 0024h WATCHDOG WDGCR Watchdog Control Register 7Fh R/W SICSR System Integrity Control / Status Register 000x 000x R/W MCCSR Main Clock Control / Status Register 00h R/W I2CCR I2CSR1 I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR I2C 00h 00h 00h 00h 00h 40h 00h R/W Read Only Read Only R/W R/W R/W R/W 0025h 0026h MCC 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h Reserved (1 Byte) I2C Control Register I2C Status Register 1 I2C Status Register 2 I2C Clock Control Register I2C Own Address Register 1 I2C Own Address Register2 I2C Data Register Reserved (2 Bytes) 11/171 ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G Address Block Register Label Register Name R/W R/W R/W Read Read R/W R/W Read Read Read Read Read Read R/W R/W Miscellanous register 2 00h R/W TIMER B TBCR2 TBCR1 TBSCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W R/W Read Read R/W R/W Read Read Read Read Read Read R/W R/W SCI SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register1 SCI Control Register2 SCI Extended Receive Prescaler Register SCI Extended Transmit Prescaler Register Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer 0040h MISCR2 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h TIMER A 0057h to 006Eh ADC 0072h FLASH 12/171 A Control Register 2 A Control Register 1 A Control/Status Register A Input Capture 1 High Register A Input Capture 1 Low Register A Output Compare 1 High Register A Output Compare 1 Low Register A Counter High Register A Counter Low Register A Alternate Counter High Register A Alternate Counter Low Register A Input Capture 2 High Register A Input Capture 2 Low Register A Output Compare 2 High Register A Output Compare 2 Low Register B Control Register 2 B Control Register 1 B Control/Status Register B Input Capture 1 High Register B Input Capture 1 Low Register B Output Compare 1 High Register B Output Compare 1 Low Register B Counter High Register B Counter Low Register B Alternate Counter High Register B Alternate Counter Low Register B Input Capture 2 High Register B Input Capture 2 Low Register B Output Compare 2 High Register B Output Compare 2 Low Register Only Only Only Only Only Only Only Only Only Only Only Only Only Only Only Only C0h xxh 00h x000 0000h 00h 00h 00h Read Only R/W R/W R/W R/W R/W R/W Data Register Low3) Data Register High3) Control/Status Register 00h 00h 00h Read Only Read Only R/W Flash Control Register 00h Reserved (24 Bytes) 006Fh 0070h 0071h 0073h to 007Fh Remarks 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h TACR2 TACR1 TASCSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Reset Status ADCDRL ADCDRH ADCCSR FCSR Reserved (13 Bytes) R/W ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G Legend: x=Undefined, R/W=Read/Write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 3. For compatibility with the ST72C254 ST72C254, the ADCDRL and ADCDRH data registers are located with the LSB on the lower address (6Fh) and the MSB on the higher address (70h). As this scheme is not little Endian, the ADC data registers cannot be treated by C programs as an integer, but have to be treated as two char registers. 13/171 ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G 4 FLASH PROGRAM MEMORY 4.1 Introduction The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Programming. The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 Main Features s s s s s ICP (In-Circuit Programming) IAP (In-Application Programming) ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Sector 0 size configurable by option byte Read-out and write protection against piracy 4.3 PROGRAMMING MODES The ST7 can be programmed in three different ways: ­ Insertion in a programming tool. In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or erased. ­ In-Circuit Programming. In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or erased without removing the device from the application board. ­ In-Application Programming. In this mode, sector 1 can be programmed or erased without removing the device from the application 14/171 board and while the application is running. 4.3.1 In-Circuit Programming (ICP) ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps: Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface. ­ Download ICP Driver code in RAM from the ICCDATA pin ­ Execute ICP Driver code in RAM to program the FLASH memory Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 In Application Programming (IAP) This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G FLASH PROGRAM MEMORY (Cont'd) Tool documentation for recommended resistor values. 2. During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. Pin 9 has to be connected to the OSC1 pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case. 4.4 ICC interface ICP needs a minimum of 4 and up to 7 pins to be connected to the programming tool. These pins are: ­ RESET: device reset ­ VSS: device power supply ground ­ ICCCLK: ICC output serial clock pin ­ ICCDATA: ICC input serial data pin ­ ICCSEL: ICC selection (not required on devices without ICCSEL pin) ­ OSC1: main clock input for external source (not required on devices without OSC1/OSC2 pins) ­ VDD: application board power supply (optional, see Note 3) Notes: 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Figure 6. Typical ICC Interface PROGRAMMING TOOL ICC CONNECTOR ICC Cable ICC CONNECTOR HE10 CONNECTOR TYPE OPTIONAL (See Note 3) OPTIONAL (See Note 4) 9 7 5 3 1 10 8 6 4 APPLICATION BOARD 2 APPLICATION RESET SOURCE See Note 2 10k ICCDATA ICCCLK ST7 RESET See Note 1 APPLICATION I/O ICCSEL OSC1 CL1 OSC2 VDD CL2 VSS APPLICATION POWER SUPPLY 15/171 ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G FLASH PROGRAM MEMORY (Cont'd) 4.5 Memory Protection There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually. 4.5.1 Read out Protection Read out protection, when selected, makes it impossible to extract the memory content from the microcontroller, thus preventing piracy. In flash devices, this protection is removed by reprogramming the option. In this case the program memory is automatically erased and the device can be reprogrammed. Read-out protection selection depends on the device type: ­ In Flash devices it is enabled and removed through the FMP_R bit in the option byte. ­ In ROM devices it is enabled by mask option specified in the Option List. 4.5.2 Flash Write/Erase Protection Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content. 16/171 Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable. Write/erase protection is enabled through the FMP_W bit in the option byte. 4.6 Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read /Write Reset Value: 000 0000 (00h) 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh) 7 0 0 0 0 0 0 OPT LAT PGM Note: This register is reserved for programming using ICP, IAP or other programming methods. It controls the XFlash programming and erasing operations. For details on XFlash programming, refer to the ST7 Flash Programming Reference Manual. When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically. ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G 5 CENTRAL PROCESSING UNIT 5.1 INTRODUCTION 5.3 CPU REGISTERS This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. The 6 CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures. Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB). 5.2 MAIN FEATURES s s s s s s s s Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer Low power HALT and WAIT modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts Figure 7. CPU Registers 7 0 ACCUMULATOR RESET VALUE = XXh 7 0 X INDEX REGISTER RESET VALUE = XXh 7 0 Y INDEX REGISTER RESET VALUE = XXh 15 PCH 8 7 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 1 1 I1 H I0 N Z C CONDITION CODE REGISTER RESET VALUE = 1 1 1 X 1 X X X 15 8 7 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 17/171 ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G CENTRAL PROCESSING UNIT (Cont'd) Bit 1 = Z Zero. Condition Code Register (CC) Read/Write Reset Value: 111x1xxx 7 1 0 1 I1 H I0 N Z C The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Arithmetic Management Bits Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 2 = N Negative . This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It's a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. 18/171 This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. Interrupt Management Bits Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the current interrupt software priority. Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) I1 1 0 0 1 I0 0 1 0 1 These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See the interrupt management chapter for more details. ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 7Fh 15 0 8 0 0 0 0 0 0 7 SP7 1 0 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8). Since the stack is 128 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 8 ­ When an interrupt is received, the SP is decremented and the context is pushed on the stack. ­ On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area. Figure 8. Stack Manipulation Example CALL Subroutine PUSH Y Interrupt Event POP Y RET or RSP IRET @ 0100h SP SP CC A Y CC A SP CC A X X X PCH PCH PCH PCL PCL PCL PCH PCH PCH PCH PCH PCL PCL PCL PCL PCL SP @ 017Fh SP SP Stack Higher Address = 017Fh Stack Lower Address = 0100h 19/171 ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G 6 SUPPLY, RESET AND CLOCK MANAGEMENT 6.1 PHASE LOCKED LOOP The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 10. For more details, refer to dedicated parametric section. If the clock frequency input to the PLL is in the 2 to 4 MHz range, the PLL can be used to multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then fOSC2 = fOSC/2. Caution: The PLL is not recommended for applications where timing accuracy is required. See "PLL Characteristics" on page 134. Main Features s Optional PLL for multiplying the frequency by 2 (not to be used with internal RC oscillator) s Reset Sequence Manager (RSM) s Multi-Oscillator Clock Management (MO) ­ 4 Crystal/Ceramic resonator oscillators ­ 1 Internal RC oscillator s System Integrity Management (SI) ­ Main supply Low Voltage Detector (LVD) ­ Auxiliary Voltage Detector (AVD) with interrupt capability for monitoring the main supply ­ Clock Security System (CSS) with Clock Filter and Backup Safe Oscillator (enabled by option byte) Figure 9. PLL Block Diagram PLL x 2 0 /2 1 fOSC fOSC2 PLL OPTION BIT Figure 10. Clock, Reset and Supply Block Diagram SYSTEM INTEGRITY MANAGEMENT CLOCK SECURITY SYSTEM (CSS) OSC2 MULTIOSCILLATOR OSC1 fOSC PLL fOSC2 (option) (MO) RESET SEQUENCE RESET MANAGER (RSM) CLOCK SAFE FILTER fOSC2 OSC AVD Interrupt Request SICSR 0 AVD AVD LVD IE F RF MAIN CLOCK fCPU CONTROLLER WITH REALTIME CLOCK (MCC/RTC) WATCHDOG TIMER (WDG) 0 CSS CSS WDG IE D RF CSS Interrupt Request LOW VOLTAGE VSS DETECTOR VDD (LVD) AUXILIARY VOLTAGE DETECTOR (AVD) 20/171 ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G 6.2 MULTI-OSCILLATOR (MO) Table 3. ST7 Clock Sources External Clock Hardware Configuration Crystal/Ceramic Resonators External Clock Source In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground. Crystal/Ceramic Oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 5 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to Section 15.1 on page 157 for more details on the frequency ranges). In this mode of the multioscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. Internal RC Oscillator This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing. In this mode, the two oscillator pins have to be tied to ground. Internal RC Oscillator The main clock of the ST7 can be generated by four different source types coming from the multioscillator block: s an external source s 5 crystal or ceramic resonator oscillators s an internal high frequency RC oscillator Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 3. Refer to the electrical characteristics section for more details. Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure Mode and Effects Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an fOSC clock frequency in excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. The product behaviour must therefore be considered undefined when the OSC pins are left unconnected. ST7 OSC1 OSC2 EXTERNAL SOURCE ST7 OSC1 CL1 OSC2 LOAD CAPACITORS CL2 ST7 OSC1 OSC2 21/171 ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G 6.3 RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 12: s External RESET source pulse s Internal LVD RESET (Low Voltage Detection) s Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 11: s Active Phase depending on the RESET source s 4096 CPU clock cycle delay (selected by option byte) s RESET vector fetch The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application. The RESET vector fetch phase duration is 2 clock cycles. Figure 11. RESET Sequence Phases RESET Active Phase INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR 6.3.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 13). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode. Figure 12. Reset Block Diagram VDD RON RESET INTERNAL RESET Filter PULSE GENERATOR 22/171 WATCHDOG RESET LVD RESET ST72260G ST72260G, ST72262G ST72262G, ST72264G ST72264G RESET SEQUENCE MANAGER (Cont'd) The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 6.3.3 External Power-On RESET If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. 6.3.4 Internal Low Voltage Detector (LVD) RESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: s Power-On RESET s Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDD