ST72104G ST72215G ST72216G ST72254G 16-BIT ST72216G1 SDIP32 ST72104G1 ST72104G2 - Datasheet Archive

 

ST72216G, ST72254G 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, I2C INTERFACES PRELIMINARY DATA s s s s s

 

ST72104G ST72104G, ST72215G ST72215G, ST72216G ST72216G, ST72254G ST72254G 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT 16-BIT TIMERS, SPI, I2C INTERFACES PRELIMINARY DATA s s s s s s s Memories ­ 4K or 8K bytes Program memory (ROM and single voltage FLASH) with read-out protection and in-situ programming (remote ISP) ­ 256 bytes RAM Clock, Reset and Supply Management ­ Enhanced reset system ­ Enhanced low voltage supply supervisor with 3 programmable levels ­ Clock sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System ­ Clock-out capability ­ 3 Power Saving Modes: Halt, Wait and Slow Interrupt Management ­ 7 interrupt vectors plus TRAP and RESET ­ 22 external interrupt lines (on 2 vectors) 22 I/O Ports ­ 22 multifunctional bidirectional I/O lines ­ 14 alternate function lines ­ 8 high sink outputs 3 Timers ­ Configurable watchdog timer ­ Two 16-bit timers with: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes (one only on ST72104Gx and ST72216G1 ST72216G1) 2 Communications Interfaces ­ SPI synchronous serial interface ­ I2C multimaster interface (only on ST72254Gx) 1 Analog peripheral ­ 8-bit ADC with 6 input channels (except on ST72104Gx) SDIP32 SDIP32 SO28 s Instruction Set ­ 8-bit data manipulation ­ 63 basic instructions ­ 17 main addressing modes ­ 8 x 8 unsigned multiply instruction ­ True bit manipulation s Development Tools ­ Full hardware/software development package Device Summary Features ST72104G1 ST72104G1 ST72104G2 ST72104G2 ST72216G1 ST72216G1 ST72215G2 ST72215G2 ST72254G1 ST72254G1 ST72254G2 ST72254G2 Program memory - bytes RAM (stack) - bytes 4K 8K 4K 8K 4K 8K Peripherals Operating Supply CPU Frequency Operating Temperature Packages Watchdog timer, One 16-bit timer, SPI 256 (128) Watchdog timer, Watchdog timer, One 16-bit timer, Two 16-bit timers, SPI, ADC SPI, ADC 3.2V to 5.5V Up to 8 MHz (with oscillator up to 16 MHz) -40°C to +85°C (-40°C to +105/125°C optional) SO28 / SDIP32 SDIP32 Watchdog timer, Two 16-bit timers, SPI, I C, ADC Rev. 2.3 June 2000 This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice. 1/136 1 Table of Contents 1 2 3 4 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 4.4 STRUCTURAL ORGANISATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 IN-SITU PROGRAMMING (ISP) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.5 MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 CENTRAL PROCESSING UNIT (Cont'd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.2 7.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.4 7.5 CLOCK SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR) . . . . . . . . . . . . . . . 21 7.6 MAIN CLOCK CONTROLLER (MCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 9.4 23 25 25 25 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.6 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 136 11.3 MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2/136 2 Table of Contents 12.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12.2 16-BIT 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.3 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.4 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12.5 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 94 94 95 14.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 14.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 14.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 14.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 14.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 14.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 14.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 14.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 14.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 122 14.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 15 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 15.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 15.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 15.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 15.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 16 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 130 16.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 16.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 131 16.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 16.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 16.5 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 17 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3/136 3 ST72104G ST72104G, ST72215G ST72215G, ST72216G ST72216G, ST72254G ST72254G 1 INTRODUCTION The ST72104G ST72104G, ST72215G ST72215G, ST72216G ST72216G and ST72254G ST72254G devices are members of the ST7 microcontroller family. They can be grouped as follows: ­ ST72254G ST72254G devices are designed for mid-range applications with ADC and I C interface capabilities. ­ ST72215/6G ST72215/6G devices target the same range of applications but without I C interface. ­ ST72104G ST72104G devices are for applications that do not need ADC and I C peripherals. All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set. The ST72C104G ST72C104G, ST72C215G ST72C215G, ST72C216G ST72C216G and ST72C254G ST72C254G versions feature single-voltage FLASH memory with byte-by-byte In-Situ Programming (ISP) capability. Under software control, all devices can be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. For easy reference, all parametric data are located in Section 14 on page 94. Figure 1. General Block Diagram OSC1 OSC2 MULTI OSC Internal CLOCK I2C + CLOCK FILTER PORT A PA7:0 (8 bits) LVD VDD VSS CONTROL 8-BIT CORE ALU PROGRAM MEMORY (4 or 8K Bytes) RAM (256 Bytes) 4/136 4 ADDRESS AND DATA BUS RESET SPI POWER SUPPLY PORT B PB7:0 (8 bits) 16-BIT 16-BIT TIMER A PORT C 8-BIT ADC 16-BIT 16-BIT TIMER B WATCHDOG PC5:0 (6 bits) ST72104G ST72104G, ST72215G ST72215G, ST72216G ST72216G, ST72254G ST72254G 2 PIN DESCRIPTION Figure 2. 28-Pin SO Package Pinout RESET 1 28 VDD OSC1 2 27 OSC2 3 26 V SS ISPSEL SS/PB7 4 25 PA0 (HS) ISPCLK/SCK/PB6 5 24 PA1 (HS) ISPDATA/MISO/PB5 6 23 PA2 (HS) MOSI/PB4 7 22 PA3 (HS) OCMP2_A/PB3 8 21 PA4 (HS)/SCLI ICAP2_A/PB2 ei1 ei0 9 20 PA5 (HS) OCMP1_A/PB1 ICAP1_A/PB0 10 19 11 18 PA6 (HS)/SDAI PA7 (HS) AIN5/EXTCLK_A/PC5 12 17 PC0/ICAP1_B/AIN0 AIN4/OCMP2_B/PC4 13 16 PC1/OCMP1_B/AIN1 AIN3/ICAP2_B/PC3 14 15 PC2/MCO/AIN2 ei0 or ei1 (HS) 20mA high sink capability eiX associated external interrupt vector Figure 3. 32-Pin SDIP Package Pinout RESET 1 32 VDD OSC1 OSC2 2 31 VSS 3 30 ISPSEL SS/PB7 4 29 PA0 (HS) ISPCLK/SCK/PB6 5 28 PA1 (HS) ISPDATA/MISO/PB5 6 27 PA2 (HS) MOSI/PB4 NC 7 26 PA3 (HS) 8 25 NC NC 9 24 OCMP2_A/PB3 ICAP2_A/PB2 10 23 NC PA4 (HS)/SCLI 22 PA5 (HS) OCMP1_A/PB1 12 21 ICAP1_A/PB0 13 PA6 (HS)/SDAI PA7 (HS) AIN5/EXTCLK_A/PC5 14 AIN4/OCMP2_B/PC4 15 AIN3/ICAP2_B/PC3 16 11 ei1 ei1 ei0 ei0 20 18 PC0/ICAP1_B/AIN0 PC1/OCMP1_B/AIN1 17 PC2/MCO/AIN2 19 ei0or ei1 (HS) 20mA high sink capability eiX associated external interrupt vector 5/136 5 ST72104G ST72104G, ST72215G ST72215G, ST72216G ST72216G, ST72254G ST72254G PIN DESCRIPTION (Cont'd) For external pin connection guidelines, refer to Section 14 "ELECTRICAL CHARACTERISTICS" on page 94. Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3VDD/0.7VDD, CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: ­ Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog ­ Output: OD = open drain 2), PP = push-pull Refer to Section 10 "I/O PORTS" on page 28 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Table 1. Device Pin Description Port / Control PP X Main Function (after reset) Alternate Function 1 RESET 2 2 OSC1 3) I 3 3 OSC2 3) O 4 4 PB7/SS I/O CT X ei1 X X Port B7 SPI Slave Select (active low) 5 5 PB6/SCK/ISPCLK I/O CT X ei1 X X Port B6 SPI Serial Clock or ISP Clock 6 6 PB5/MISO/ISPDATA I/O CT X ei1 X X Port B5 SPI Master In/ Slave Out Data or ISP Data 7 7 PB4/MOSI I/O CT X ei1 X X Port B4 SPI Master Out / Slave In Data Top priority non maskable interrupt (active low) External clock input or Resonator oscillator inverter input or resistor input for RC oscillator Resonator oscillator inverter output or capacitor input for RC oscillator NC 9 X OD ana int Output 1 8 I/O C T wpu Input float Output Input Pin Name Type Level SO28 SDIP32 SDIP32 Pin n° NC Not Connected 10 8 PB3/OCMP2_A I/O CT X ei1 X X Port B3 Timer A Output Compare 2 11 9 PB2/ICAP2_A I/O CT X ei1 X X Port B2 Timer A Input Capture 2 12 10 PB1 /OCMP1_A I/O CT X ei1 X X Port B1 Timer A Output Compare 1 13 11 PB0 /ICAP1_A I/O CT X ei1 X X Port B0 Timer A Input Capture 1 14 12 PC5/EXTCLK_A/AIN5 I/O CT X ei0/ei1 X X Port C5 Timer A Input Clock or ADC Analog Input 5 15 13 PC4/OCMP2_B/AIN4 I/O CT X ei0/ei1 X X Port C4 Timer B Output Compare 2 or ADC Analog Input 4 16 14 PC3/ ICAP2_B/AIN3 I/O CT X ei0/ei1 X X Port C3 Timer B Input Capture 2 or ADC Analog Input 3 6/136 6 X ST72104G ST72104G, ST72215G ST72215G, ST72216G ST72216G, ST72254G ST72254G Level Port / Control wpu int ana OD PP X ei0/ei1 X X X Port C2 18 16 PC1/OCMP1_B/AIN1 I/O CT X ei0/ei1 X X X Port C1 19 17 PC0/ICAP1_B/AIN0 I/O CT X ei0/ei1 X X X Port C0 20 18 PA7 I/O C T HS X ei0 X X Port A7 21 19 PA6 /SDAI I/O C T HS X 22 20 PA5 I/O C T HS X 23 21 PA4 /SCLI I/O CT HS X 24 Input ei0 ei0 ei0 Output T X Port A6 X T Alternate Function Main clock output (fCPU) or ADC Analog Input 2 Timer B Output Compare 1 or ADC Analog Input 1 Timer B Input Capture 1 or ADC Analog Input 0 2 I C Data Port A5 Port A4 I2C Clock NC 25 Output CT Input I/O SO28 17 15 PC2/MCO/AIN2 SDIP32 SDIP32 float Main Function (after reset) Pin Name Type Pin n° NC Not Connected 26 22 PA3 I/O C T HS X ei0 X X Port A3 27 23 PA2 I/O C T HS X ei0 X X Port A2 28 24 PA1 I/O C T HS X ei0 X X Port A1 29 25 PA0 I/O C T HS X ei0 X X Port A0 C X In situ programming selection (Should be tied low in standard user mode). 30 26 ISPSEL I 31 27 VSS S Ground 32 28 VDD S Main power supply Notes: 1. In the interrupt input column, "eiX" defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. In the open drain output column, "T" defines a true open drain I/O (P-Buffer and protection diode to VDD are not implemented). See Section 10 "I/O PORTS" on page 28 and Section 14.8 "I/O PORT PIN CHARACTERISTICS" on page 115 for more details. 3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to the on-chip oscillator see Section 2 "PIN DESCRIPTION" on page 5 and Section 14.5 "CLOCK AND TIMING CHARACTERISTICS" on page 102 for more details. 7/136 ST72104G ST72104G, ST72215G ST72215G, ST72216G ST72216G, ST72254G ST72254G 3 REGISTER & MEMORY MAP As shown in the Figure 4, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register location, 256 bytes of RAM and up to 8Kbytes of user program memory. The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh. The highest address bytes contain the user reset and interrupt vectors. IMPORTANT: Memory locations marked as "Reserved" must never be accessed. Accessing a reseved area can have unpredicable effects on the device. Figure 4. Memory Map 0000h HW Registers (see Table 2) 0080h 256 Bytes RAM 00FFh 0100h 007Fh 0080h 017Fh 0180h Reserved 017Fh Short Addressing RAM Zero page (128 Bytes) Stack or 16-bit Addressing RAM (128 Bytes) DFFFh E000h Program Memory (4K, 8 KBytes) FFDFh FFE 0h FFF Fh 8/136 E000h 8 KBytes F000h Interrupt & Reset Vectors (see Table 5 on page 24) 4 KBytes FFFF h ST72104G ST72104G, ST72215G ST72215G, ST72216G ST72216G, ST72254G ST72254G Table 2. Hardware Register Map Address 0000h 0001h 0002h Block Port C Register Label PCDR PCDDR PCOR 0003h 0004h 0005h 0006h Port B PBDR PBDDR PBOR Port A 00h 1) 00h 00h R/W 2) R/W 2) R/W 2) 00h 1) 00h 00h R/W R/W R/W. 00h 1) 00h 00h R/W R/W Port B Data Register Port B Data Direction Register Port B Option Register PADR PADDR PAOR Port A Data Register Port A Data Direction Register Port A Option Register R/W Reserved (21 Bytes) 0020h MISCR1 SPI 0024h WATCHDOG 0025h Miscellaneous Register 1 00h R/W SPIDR SPICR SPISR SPI Data I/O Register SPI Control Register SPI Status Register xxh 0xh 00h R/W R/W Read Only WDGCR Watchdog Control Register 7Fh R/W CRSR 0021h 0022h 0023h Clock, Reset, Supply Control / Status Register 000x 000x R/W 0026h 0027h 002Fh to 0030h Port C Data Register Port C Data Direction Register Port C Option Register Remarks Reserved (1 Byte) 000Bh to 001Fh 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh Reset Status Reserved (1 Byte) 0007h 0008h 0009h 000Ah Register Name Reserved (2 bytes) I2 C I2CCR I2CSR1 I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR Control Register Status Register 1 Status Register 2 Clock Control Register Own Address Register 1 Own Address Register 2 Data Register 00h 00h 00h 00h 00h 00h 00h R/W Read Only Read Only R/W R/W R/W R/W Reserved (4 Bytes) 9/136 ST72104G ST72104G, ST72215G ST72215G, ST72216G ST72216G, ST72254G ST72254G Address 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Block Register Label Register Name TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer 0040h MISCR2 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR TIMER A TIMER B 0050h to 006Fh 0070h 0071h 0072h to 007Fh A Control Register 2 A Control Register 1 A Status Register A Input Capture 1 High Register A Input Capture 1 Low Register A Output Compare 1 High Register A Output Compare 1 Low Register A Counter High Register A Counter Low Register A Alternate Counter High Register A Alternate Counter Low Register A Input Capture 2 High Register A Input Capture 2 Low Register A Output Compare 2 High Register A Output Compare 2 Low Register Reset Status Remarks 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W Read Read Read R/W R/W Read Read Read Read Read Read R/W R/W Miscellaneous Register 2 00h R/W Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W Read Read Read R/W R/W Read Read Read Read Read Read R/W R/W 00h 00h Read Only R/W B Control Register 2 B Control Register 1 B Status Register B Input Capture 1 High Register B Input Capture 1 Low Register B Output Compare 1 High Register B Output Compare 1 Low Register B Counter High Register B Counter Low Register B Alternate Counter High Register B Alternate Counter Low Register B Input Capture 2 High Register B Input Capture 2 Low Register B Output Compare 2 High Register B Output Compare 2 Low Register Only Only Only Only Only Only Only Only Only Only Only Only Only Only Only Only Only Only Reserved (32 Bytes) ADC ADCDR ADCCSR Data Register Control/Status Register Reserved (14 Bytes) Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 10/136 ST72104G ST72104G, ST72215G ST72215G, ST72216G ST72216G, ST72254G ST72254G 4 FLASH PROGRAM MEMORY s s s s Remote In-Situ Programming (ISP) mode Up to 16 bytes programmed in the same cycle MTP memory (Multiple Time Programmable) Read-out memory protection against piracy 4.3 STRUCTURAL ORGANISATION The FLASH program memory is organised in a single 8-bit wide memory block which can be used for storing both code and data constants. The FLASH program memory is mapped in the upper part of the ST7 addressing space and includes the reset and interrupt user vector area . 4.4 IN-SITU PROGRAMMING (ISP) MODE The FLASH program memory can be programmed using Remote ISP mode. This ISP mode allows the contents of the ST7 program memory to be updated using a standard ST7 programming tools after the device is mounted on the application board. This feature can be implemented with a minimum number of added components and board area impact. An example Remote ISP hardware interface to the standard ST7 programming tool is described below. For more details on ISP programming, refer to the ST7 Programming Specification. Remote ISP Overview The Remote ISP mode is initiated by a specific sequence on the dedicated ISPSEL pin. The Remote ISP is performed in three steps: ­ Selection of the RAM execution mode ­ Download of Remote ISP code in RAM ­ Execution of Remote ISP code in RAM to program the user program into the FLASH Remote ISP hardware configuration In Remote ISP mode, the ST7 has to be supplied with power (VDD and VSS) and a clock signal (oscillator and application crystal circuit for example). HE10 CONNECTOR TYPE TO PROGRAMMING TOOL XTAL 1 CL1 CL0 VDD 4.2 MAIN FEATURES OSC1 FLASH devices have a single voltage non-volatile FLASH memory that may be programmed in-situ (or plugged in a programming tool) on a byte-bybyte basis. This mode needs five signals (plus the VDD signal if necessary) to be connected to the programming tool. This signals are: ­ RESET: device reset ­ VSS: device ground power supply ­ ISPCLK: ISP output serial clock pin ­ ISPDATA: ISP input serial data pin ­ ISPSEL: Remote ISP mode selection. This pin must be connected to VSS on the application board through a pull-down resistor. If any of these pins are used for other purposes on the application, a serial resistor has to be implemented to avoid a conflict if the other device forces the signal level. Figure 5 shows a typical hardware interface to a standard ST7 programming tool. For more details on the pin locations, refer to the device pinout description. Figure 5. Typical Remote ISP Interface OSC2 4.1 INTRODUCTION ISPSEL 10K VSS RESET ST7 ISPCLK ISPDATA 47K APPLICATION 4.5 MEMORY READ-OUT PROTECTION The read-out protection is enabled through an option bit. For FLASH devices, when this option is selected, the program and data stored in the FLASH memory are protected against read-out piracy (including a re-write protection). When this protection option is removed the entire FLASH program memory is first automatically erased. However, the E2PROM data memory (when available) can be protected only with ROM devices. 11/136 ST72104G ST72104G, ST72215G ST72215G, ST72216G ST72216G, ST72254G ST72254G 5 CENTRAL PROCESSING UNIT 5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES s s s s s s s s 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt 5.3 CPU REGISTERS The 6 CPU registers shown in Figure 6 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB). Figure 6. CPU Registers 7 0 ACCUMULATOR RESET VALUE = XXh 7 0 X INDEX REGISTER RESET VALUE = XXh 7 0 Y INDEX REGISTER RESET VALUE = XXh 15 PCH 8 7 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 1 1 1 H I 0 N Z C CONDITIO N CODE REGISTER RESET VALUE = 1 1 1 X 1 X X X 15 8 7 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 12/136 ST72104G ST72104G, ST72215G ST72215G, ST72216G ST72216G, ST72254G ST72254G CPU REGISTERS (Cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx 7 1 0 1 1 H I N Z C The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable because the I bit is set by hardware at the start of Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. 13/136 ST72104G ST72104G, ST72215G ST72215G, ST72216G ST72216G, ST72254G ST72254G 6 CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 7Fh 15 0 8 0 0 0 0 0 0 7 0 1 0 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 7). Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address. The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 7. ­ When an interrupt is received, the SP is decremented and the context is pushed on the stack. ­ On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area. Figure 7. Stack Manipulation Example CALL Subroutine PUSH Y Interrupt Event POP Y RET or RSP IRET @ 0100h SP SP SP CC A Y CC A X X X PCH PCH PCH PCL PCL PCL PCH PCH PCH PCH PCH PCL PCL PCL PCL PCL SP @ 017Fh Stack Higher Address = 017Fh Stack Lower Address = 0100h 14/136 CC A SP SP ST72104G ST72104G, ST72215G ST72215G, ST72216G ST72216G, ST72254G ST72254G 7 SUPPLY, RESET AND CLOCK MANAGEMENT The ST72104G ST72104G, ST72215G ST72215G, ST72216G ST72216G and ST72254G ST72254G microcontrollers include a range of utility features for securing the application in critical situations (for example in case of a power brownout), and reducing the number of external components. An overview is shown in Figure 8. See Section 14 "ELECTRICAL CHARACTERISTICS" on page 94 for more details. Main Features s Supply Manager with main supply low voltage detection (LVD) s Reset Sequence Manager (RSM) s Multi-Oscillator (MO) ­ 4 Crystal/Ceramic resonator oscillators ­ 1 External RC oscillator ­ 1 Internal RC oscillator s Clock Security System (CSS) ­ Clock Filter ­ Backup Safe Oscillator Figure 8. Clock, Reset and Supply Block Diagram MCO CLOCK SECUR ITY SYSTE M (CSS) OSC2 MULTI- CLOCK MAIN CLOCK fOSC SAFE OSC1 FILTER (MO) fCPU CONTROLLER OSCILLATOR OSC (MCC) RESET SEQUEN CE RESET FROM WATCH DOG PERIP HERAL MANAGER (RSM) VDD LOW VOLTAGE VSS (LVD) CSS LVD DETECTO R CRSR 0 0 0 RF 0 IE WDG D RF CSS INTER RUPT 15/136 ST72104G ST72104G, ST72215G ST72215G, ST72216G ST72216G, ST72254G ST72254G 7.1 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: ­ VIT+ when VDD is rising ­ VIT- when VDD is falling The LVD function is illustrated in the Figure 9. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes: ­ under full software control ­ in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: 1. The LVD allows the device to be used without any external RESET circuitry. 2. Three different reference levels are selectable through the option byte according to the application requirement. LVD application note Application software can detect a reset caused by the LVD by reading the LVDRF bit in the CRSR register. This bit is set by hardware when a LVD reset is generated and cleared by software (writing zero). Figure 9. Low Voltage Detector vs Reset VDD Vhyst VIT+ VIT- RESET 16/136 ST72104G ST72104G, ST72215G ST72215G, ST72216G ST72216G, ST72254G ST72254G 7.2 RESET SEQUENCE MANAGER (RSM) 7.2.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 11: s External RESET source pulse s Internal LVD RESET (Low Voltage Detection) s Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 10: s Delay depending on the RESET source s 4096 CPU clock cycle delay s RESET vector fetch The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock cycles. Figure 10. RESET Sequence Phases RESET DELAY INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR Figure 11. Reset Block Diagram VDD INTERNAL RESET RON COUNTER f CPU RESET WATCHDOG RESET LVD RESET 17/136 ST72104G ST72104G, ST72215G ST72215G, ST72216G ST72216G, ST72254G ST72254G RESET SEQUENCE MANAGER (Cont'd) 7.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized. This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. Two RESET sequences can be associated with this RESET source: short or long external reset pulse (see Figure 12). Starting from the external RESET pulse recognition, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. 7.2.3 Internal Low Voltage Detection RESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: s Power-On RESET s Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDD