ST62T65B/E65B RS232 PDIP28 PSO28 CDIP28W ST62T65B ST62E65B ST6265B - Datasheet Archive

 

8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, EEPROM AND SPI s s s s s s s s s s s s s s s s s s s s s 3.0 to 6.0V Supply

 

ST62T65B/E65B ST62T65B/E65B 8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, EEPROM AND SPI s s s s s s s s s s s s s s s s s s s s s 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +85°C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capability in Program Memory Data Storage in Program Memory: User selectable size Data RAM: 128 bytes Data EEPROM: 128 bytes User Programmable Options 21 I/O pins, fully programmable as: ­ Input with pull-up resistor ­ Input without pull-up resistor ­ Input with interrupt generation ­ Open-drain or push-pull output ­ Analog Input 8 I/O lines can sink up to 20mA to drive LEDs or TRIACs directly 8-bit Timer/Counter with 7-bit programmable prescaler 8-bit Auto-reload Timer with 7-bit programmable prescaler (AR Timer) Digital Watchdog 8-bit A/D Converter with 13 analog inputs 8-bit Synchronous Peripheral Interface (SPI) On-chip Clock oscillator can be driven by Quartz Crystal Ceramic resonator or RC network User configurable Power-on Reset One external Non-Maskable Interrupt ST626x-EMU2 Emulation and Development System (connects to an MS-DOS PC via an RS232 RS232 serial line) PDIP28 PDIP28 PSO28 PSO28 CDIP28W CDIP28W (See end of Datasheet for Ordering Information) DEVICE SUMMARY DEVICE ST62T65B ST62T65B ST62E65B ST62E65B July 1996 OTP (Bytes) EPROM (Bytes) I/O Pins 3884 - 21 3884 21 1/70 463 Table of Contents ST62T65B/E65B ST62T65B/E65B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.6 Data RAM/EEPROM Bank Register (DRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4 EEPROM DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.5 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.3 EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.4 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 13 13 14 15 15 15 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 17 19 19 19 20 20 20 22 24 24 26 3.4.1 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 External Interrupt Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 27 27 27 30 3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 Exit from WAIT and STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 31 32 32 4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2/70 464 Table of Contents 4.1.2 I/O Port Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.3 I/O Port Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.4 I/O Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.5 Timer 1 Alternate function Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.6 AR Timer Alternate function Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.7 SPI Alternate function Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.8 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Gated Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.5 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.6 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.7 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 AUTO-RELOAD TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 33 33 33 34 34 34 37 38 38 38 38 38 39 39 40 4.3.1 AR Timer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 AR Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 40 44 46 4.4.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.5 SERIAL PERIPHERAL INTERFACE SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.5.1 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2 SPI Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 51 53 53 5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3 DC TELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.4 AC TELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.2 .ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 ST6265B ST6265B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 1GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.2 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 1.3.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 1.3.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3/70 465 ST62T65B/E65B ST62T65B/E65B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST62T65B ST62T65B and ST62E65B ST62E65B devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to medium complexity applications. All ST62xx devices are based on a building block approach: a common core is surrounded by a number of on-chip peripherals. The ST62E65B ST62E65B is the erasable EPROM version of the ST62T65B ST62T65B device, which may be used to emulate the ST62T65B ST62T65B device, as well as the respective ST6265B ST6265B ROM devices. OTP and EPROM devices are functionally identical. The ROM based versions offer the same functionality selecting as ROM options the options de- fined in the programmable option byte of the OTP/EPROM versions. OTP devices offer all the advantages of user programmability at low cost, which make them the ideal choice in a wide range of applications where frequent code changes, multiple code versions or last minute programmability are required. These compact low-cost devices feature a Timer comprising an 8-bit counter and a 7-bit programmable prescaler, an 8-bit Auto-Reload Timer, EEPROM data capability, a serial port communication interface, an 8-bit A/D Converter with 13 analog inputs and a Digital Watchdog timer, making them well suited for a wide range of automotive, appliance and industrial applications. Figure 1. Block Diagram 8-BIT A/D CONVERTER NMI PA0.PA7 / Ain PORT B TEST/VPP PORT A PB0.PB 5 / 20 mA Sink PB6 / ARTimin / 20 mA Sink PB7 / ARTimout / 20 mA Sink TEST INTERRUPT DATA ROM USER SELECTABLE PORT C OTP/EPR OM Memory DATA RAM 3884 bytes OTP (ST62T65B ST62T65B) 3884 bytes EPROM (ST62 E65B) 128 Bytes DATA EEPROM AUTORELOAD TIMER TIMER 128 Bytes SPI (SERIAL PERIPHERAL INTERF ACE) PC STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 8 BIT CORE STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 POWER SUPPLY 466 RESET VDD VSS 4/70 OSCILLATOR OSCin OSCout RESET DIGITAL WATCH DOG PC0 / Ain PC1 / Tim1 / Ain PC2 / Sin / Ain PC3 / Sout / Ain PC4 / Sck / Ain ST62T65B/E65B ST62T65B/E65B 1.2 PIN DESCRIPTIONS VDD and VSS. Power is supplied to the MCU via these two pins. VDD is the power connection and VSS is the ground connection. OSCin and OSCout. These pins are internally connected to the on-chip oscillator circuit. A quartz crystal, a ceramic resonator or an external clock signal can be connected between these two pins. The OSCin pin is the input pin, the OSCout pin is the output pin. RESET. The active-low RESET pin is used to restart the microcontroller. TEST/VPP. The TEST must be held at VSS for normal operation. If TEST pin is connected to a +12.5V level during the reset phase, the EPROM/OTP programming Mode is entered. NMI. The NMI pin provides the capability for asynchronous interruption, by applying an external non maskable interrupt to the MCU. The NMI input is falling edge sensitive. It is provided with an onchip pullup resistor and Schmitt trigger characteristics. PA0-PA7. These 8 lines are organized as one I/O port (A). Each line may be configured under software control as inputs with or without internal pullup resistors, interrupt generating inputs with pullup resistors, open-drain or push-pull outputs, analog inputs for the A/D converter. PB0-PB5. These 6 lines are organized as one I/O port (B). Each line may be configured under software control as inputs with or without internal pullup resistors, interrupt generating inputs with pullup resistors, open-drain or push-pull outputs. PB0-PB5 can also sink 20mA for direct LED driving. PB6/ARTIMin, PB7/ARTIMout. These pins are either Port B I/O bits or the Input and Output pins of the AR TIMER. To be used as timer input function PB6 has to be programmed as input with or without pull-up. A dedicated bit in the AR TIMER Mode Control Register sets PB7 as timer output function. PB6-PB7 can also sink 20mA for direct LED driving. PC0-PC4. These 5 lines are organized as one I/O port (C). Each line may be configured under software control as input with or without internal pullup resistor, interrupt generating input with pull-up resistor, analog input for the A/D converter, opendrain or push-pull output. PC1 can also be used as Timer I/O bit while PC2-PC4 can also be used as respectively Data in, Data out and Clock I/O pins for the on-chip SPI to carry the synchronous serial I/O signals. Figure 2. ST62T65B ST62T65B and ST62E65B ST62E65B Configuration PB0 PB1 VPP/TEST PB2 PB3 PB4 PB5 ARTIMin/PB6 ARTIMout/PB7 Ain / PA0 V DD VSS Ain/PA1 Ain/PA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Pin PC0/Ain PC1/TIM1/Ain PC1/Sin/Ain PC1/Sout/Ain PC1/SCK/Ain NMI RESET OSCout OSCin PA7/Ain PA6/Ain PA5/Ain PA3/Ain PA3/Ain 5/70 467 ST62T65B/E65B ST62T65B/E65B 1.3 MEMORY MAP 1.3.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Briefly, Program space contains user program code in OTP and user vectors; Data space contains user data in RAM and in OTP, and Stack space accommodates six levels of stack for subroutine and interrupt service routine nesting. Figure 3. Memory Addressing Diagram PROGRAM SPACE DATA SPACE 0000h 000h RAM / EEPROM BANKING AREA 0-63 PROGRAM MEMORY 03Fh 040h DATA READ-ONLY MEMORY WINDOW 070h 080h 081h 082h 083h 084h X REGISTER Y REGISTER V REGISTER W REGISTER RAM 0C0h DATA READ-ONLY MEMORY WINDOW SELECT DATA RAM BANK SELECT 0FFh ACCUMULATOR 0FF0h INTERRUPT & RESET VECTORS 0FFFh 6/70 468 ST62T65B/E65B ST62T65B/E65B MEMORY MAP (Cont'd) 1.3.2 Program Space Program Space comprises the instructions to be executed, the data required for immediate addressing mode instructions, the reserved factory test area and the user vectors. Program Space is addressed via the 12-bit Program Counter register (PC register). 1.3.2.1 Program Memory Protection The Program Memory in OTP or EPROM devices can be protected against external readout of memory by selecting the READOUT PROTECTION option in the option byte. Figure 4. ST62E65B/T65B ST62E65B/T65B Program Memory Map 0000h RESERVED * 007Fh 0080h In the EPROM parts, READOUT PROTECTION option can be disactivated only by U.V. erasure that also results into the whole EPROM context erasure. Note: Once the Readout Protection is activated, it is no longer possible, even for SGS-THOMSON, to gain access to the OTP contents. Returned parts with a protection set can therefore not be accepted. USER PROGRAM MEMORY (OTP/EPROM) 3872 BYTES 0F9Fh 0FA0h 0FEFh 0FF0h 0FF7h 0FF8h 0FFBh 0FFCh 0FFDh 0FFEh 0FFFh RESERVED* INTERRUPT VECTORS RESERVED NMI VECTOR USER RESET VECTOR (*) Reserved areas should be filled with 0FFh 7/70 469 ST62T65B/E65B ST62T65B/E65B MEMORY MAP (Cont'd) 1.3.3 Data Space Data Space accommodates all the data necessary for processing the user program. This space comprises the RAM resource, the processor core and peripheral registers, as well as read-only data such as constants and look-up tables in OTP/EPROM. 1.3.3.1 Data ROM All read-only data is physically stored in program memory, which also accommodates the Program Space. The program memory consequently contains the program code to be executed, as well as the constants and look-up tables required by the application. The Data Space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to access the read-only data stored in OTP/EPROM. 1.3.3.2 Data RAM/EEPROM In ST62T65B ST62T65B and ST62E65B ST62E65B devices, the data space includes 60 bytes of RAM, the accumulator (A), the indirect registers (X), (Y), the short direct registers (V), (W), the I/O port registers, the peripheral data and control registers, the interrupt option register and the Data ROM Window register (DRW register). Additional RAM and EEPROM pages can also be addressed using banks of 64 bytes located between addresses 00h and 3Fh. 1.3.4 Stack Space Stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as well as the current program counter contents. Table 1. Additional RAM/EEPROM Banks Device ST62T65B/E65B ST62T65B/E65B RAM 1 x 64 bytes EEPROM 2 x 64 bytes Table 2. ST62T65B ST62T65B and ST62E65B ST62E65B Data Memory Space RAM and EEPROM X REGISTER Y REGISTER V REGISTER W REGISTER DATA RAM 60 BYTES PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER RESERVED PORT A DIRECTION REGISTE R PORT B DIRECTION REGISTE R PORT C DIRECTION REGIST ER RESERVED INTER RUPT OPTION REGISTER DATA ROM WIND OW REGISTER RESERVED PORT A OPTION REGISTER PORT B OPTION REGISTER PORT C OPTION REGISTER RESERVED A/D DATA REGISTER A/D CONTROL REGISTER TIMER PRESC ALER REGISTER TIMER COUNTER REGISTER TIMER STATUS CONTROL REGIST ER AR TIMER MODE CONTROL REGISTER AR TIMER STATU S/CONTRO L REGISTER1 AR TIMER STATU S/CONTRO L REGISTER2 WATCHD OG REGISTER AR TIMER RELOAD/CAPTUR E REGISTER AR TIMER COMPARE REGISTER AR TIMER LOAD REGISTE R OSCILLATOR CONTROL REGISTE R MISCELLANEOU S RESERVED RESERVED DATA RAM/EEPRO M REGISTER RESERVED EEPROM CONTROL REGISTER RESERVED ACCUMULATOR * WRITE ONLY REGISTER 470 03Fh 040h DATA ROM WINDO W AREA SPI DATA REGISTER SPI DIVIDER REGISTER SPI MODE REGISTER 8/70 000h 07Fh 080h 081h 082h 083h 084h 0BFh 0C0h 0C1h 0C2h 0C3h 0C4h 0C5h 0C6h 0C7h 0C8h* 0C9h* 0CAh 0CBh 0CCh 0CDh 0CEh 0CFh 0D0h 0D1h 0D2h 0D3h 0D4h 0D5h 0D6h 0D7h 0D8h 0D9h 0DAh 0DBh 0DCh* 0DDh 0DEh 0DFh 0E0h 0E1h 0E2h 0E3h 0E7h 0E8h* 0E9h 0EAh 0EBh 0FEh 0FFh ST62T65B/E65B ST62T65B/E65B MEMORY MAP (Cont'd) 1.3.5 Data Window Register (DWR) Data Window Register (DWR) Address: 0C9h - The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes located anywhere in program memory, between address 0000h and 1FFFh (top memory address depends on the specific device). All the program memory can therefore be used to store either instructions or read-only data. Indeed, the window can be moved in steps of 64 bytes along the program memory by writing the appropriate code in the Data Window Register (DWR). Write Only 7 0 - - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0 Bits 6, 7 = Not used. Bit 5-0 = DWR5-DWR0: Data read-only memory Window Register Bits. These are the Data readonly memory Window bits that correspond to the upper bits of the data read-only memory space. The DWR can be addressed like any RAM location in the Data Space, it is however a write-only register and therefore cannot be accessed using single-bit operations. This register is used to position the 64-byte read-only data window (from address 40h to address 7Fh of the Data space) in program memory in 64-byte steps. The effective address of the byte to be read as data in program memory is obtained by concatenating the 6 least significant bits of the register address given in the instruction (as least significant bits) and the content of the DWR register (as most significant bits), as illustrated in Figure 5 below. For instance, when addressing location 0040h of the Data Space, with 0 loaded in the DWR register, the physical location addressed in program memory is 00h. The DWR register is not cleared on reset, therefore it must be written to prior to the first access to the Data read-only memory window area. Caution: This register is undefined on reset. Neither read nor single bit instructions may be used to address this register. Note: Care is required when handling the DWR register as it is write only. For this reason, the DWR contents should not be changed while executing an interrupt service routine, as the service routine cannot save and then restore the register's previous contents. If it is impossible to avoid writing to the DWR during the interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to the DWR, it must also write to the image register. The image register must be written first so that, if an interrupt occurs between the two instructions, the DWR is not affected. Figure 5. Data read-only memory Window Memory Addressing DATA READ-ONLY 13 12 11 10 9 MEMORY WINDOW REG ISTER 7 6 5 4 3 CONTENTS (DWR) 8 7 6 2 1 0 0 1 0 0 0 0 5 4 3 2 1 0 5 4 3 2 1 0 1 0 1 1 0 0 1 0 0 1 1 0 0 1 PRO GRAMS PACE ADDRES S RE AD : DATA S PACE ADDRE SS 40h-7Fh IN INS TRUCTION Exa mple: DWR=28h PROGRAM MEMORY ADDRES S : A19h 1 1 0 0 1 1 0 0 DATA S PACE ADDRE SS : 59h VR0157 VR0157 3C 9/70 471 ST62T65B/E65B ST62T65B/E65B MEMORY MAP (Cont'd) 1.3.6 Data RAM/EEPROM (DRBR) Address: E8h - Write only Bank 7 - Register 0 - - DRBR DRBR 4 3 - DRBR DRBR 1 0 Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM Page 2. Bit 3 - DRBR3. This bit, when set, selects RAM Page 1. Bit2. These bits are not used. Bit 1 - DRBR1. This bit, when set, selects EEPROM Page 1. Bit 0 - DRBR0. This bit, when set, selects EEPROM Page 0. The selection of the bank is made by programming the Data RAM Bank Switch register (DRBR register) located at address E8h of the Data Space according to Table 1. No more than one bank should be set at a time. The DRBR register can be addressed like a RAM Data Space at the address E8h; nevertheless it is a write only register that cannot be accessed with single-bit operations. This register is used to select the desired 64-byte RAM/EEPROM bank of the Data Space. The number of banks has to be loaded in the DRBR register and the instruction has to point to the selected location as if it was in bank 0 (from 00h address to 3Fh address). 10/70 472 This register is not cleared during the MCU initialization, therefore it must be written before the first access to the Data Space bank region. Refer to the Data Space description for additional information. The DRBR register is not modified when an interrupt or a subroutine occurs. Notes : Care is required when handling the DRBR register as it is write only. For this reason, it is not allowed to change the DRBR contents while executing interrupt service routine, as the service routine cannot save and then restore its previous content. If it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a RAM location, and each time the program writes to DRBR it must write also to the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRBR is not affected. In DRBR Register, only 1 bit must be set. Otherwise two or more pages are enabled in parallel, producing errors. Table 3. Data RAM Bank Register Set-up DRBR 00 01 02 08 10h other ST62T65B/E65B ST62T65B/E65B None EEPROM Page 0 EEPROM Page 1 Not Available RAM Page 2 Reserved ST62T65B/E65B ST62T65B/E65B MEMORY MAP (Cont'd) 1.4 EEPROM DESCRIPTION Depending on the specific device, 64 or 128 bytes of EEPROM memory are located in one or two 64byte pages in data space. This memory may be used by the user program for non-volatile data storage. Data space from 00h to 3Fh is paged as described in Table 4. EEPROM locations are accessed directly by addressing these paged sections of data space. The EEPROM does not require dedicated instructions for read or write access. Once selected via the Data RAM Bank Register, the active EEPROM page is controlled by the EEPROM Control Register (EECTL), which is described below. Bit E20FF E20FF of the EECTL register must be reset prior to any write or read access to the EEPROM. If no bank has been selected, or if E2OFF is set, any access is meaningless. Programming must be enabled by setting the E2ENA bit of the EECTL register. The E2BUSY bit of the EECTL register is set when the EEPROM is performing a programming cycle. Any access to the EEPROM when E2BUSY is set is meaningless. Provided E2OFF and E2BUSY are reset, an EEPROM location is read just like any other data location, also in terms of access time. Writing to the EEPROM may be carried out in two modes: Byte Mode (BMODE) and Parallel Mode (PMODE). In BMODE, one byte is accessed at a time, while in PMODE up to 8 bytes in the same row are programmed simultaneously (with consequent speed and power consumption advantages, the latter being particularly important in battery powered circuits). EEPROM Control Register (EECTL) Address: EAh - Read/Write Reset status: 00h 7 D7 0 E2OFF D5 D4 E2PAR1 E2PAR2 E2BUSY E2ENA Bit 7 = D7: Unused. Bit 6 = E2OFF: Stand-by Enable Bit. WRITE ONLY. If this bit is set the EEPROM is disabled (any access will be meaningless) and the power consumption of the EEPROM is reduced to its lowest value. Bit 5-4 = D5-D4: Reserved. MUST be kept reset. Bit 3 = E2PAR1: Parallel Start Bit. WRITE ONLY. Once in Parallel Mode, as soon as the user software sets the E2PAR1 bit, parallel writing of the 8 adjacent registers will start. This bit is internally reset at the end of the programming procedure. Note that less than 8 bytes can be written if required, the undefined bytes being unaffected by the parallel programming cycle; this is explained in greater detail in the Additional Notes on Parallel Mode overleaf. Bit 2 = E2PAR2: Parallel Mode En. Bit. WRITE ONLY. This bit must be set by the user program in order to perform parallel programming. If E2PAR2 is set and the parallel start bit (E2PAR1) is reset, up to 8 adjacent bytes can be written simultaneously. These 8 adjacent bytes are considered as a row, whose address lines A7, A6, A5, A4, A3 are fixed while A2, A1 and A0 are the changing bits, as illustrated in Table 4. E2PAR2 is automatically reset at the end of any parallel programming procedure. It can be reset by the user software before starting the programming procedure, thus leaving the EEPROM registers unchanged. Bit 1 = E2BUSY: EEPROM Busy Bit. READ ONLY. This bit is automatically set by the EEPROM control logic when the EEPROM is in programming mode. The user program should test it before any EEPROM read or write operation; any attempt to access the EEPROM while the busy bit is set will be aborted and the writing procedure in progress will be completed. Bit 0 = E2ENA: EEPROM Enable Bit. WRITE ONLY. This bit enables programming of the EEPROM cells. It must be set before any write to the EEPROM register. Any attempt to write to the EEPROM when E2ENA is low is meaningless and will not trigger a write cycle. 11/70 473 ST62T65B/E65B ST62T65B/E65B MEMORY MAP (Cont'd) General Notes: Data should be written directly to the intended address in EEPROM space. There is no buffer memory between data RAM and the EEPROM space. When the EEPROM is busy (E2BUSY = "1") EECTL cannot be accessed in write mode, it is only possible to read the status of E2BUSY. This implies that as long as the EEPROM is busy, it is not possible to change the status of the EEPROM Control Register. EECTL bits 4 and 5 are reserved and must never be set. Care is required when dealing with the EECTL register, as some bits are write only. For this reason, the EECTL contents must not be altered while executing an interrupt service routine. If it is impossible to avoid writing to this register within an interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to EECTL it must also write to the image register. The image register must be written to first so that, if an interrupt occurs between the two instructions, the EECTL will not be affected. Additional Notes on Parallel Mode: If the user wishes to perform parallel programming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be addressed in write mode, the ROW address will be latched and it will be possible to change it only at the end of the programming cycle, or by resetting E2PAR2 without programming the EEPROM. After the ROW address is latched, the MCU can only "see" the selected EEPROM row and any attempt to write or read other rows will produce errors. The EEPROM should not be read while E2PAR2 is set. As soon as the E2PAR2 bit is set, the 8 volatile ROW latches are cleared. From this moment on, the user can load data in all or in part of the ROW. Setting E2PAR1 will modify the EEPROM registers corresponding to the ROW latches accessed after E2PAR2. For example, if the software sets E2PAR2 and accesses the EEPROM by writing to addresses 18h, 1Ah and 1Bh, and then sets E2PAR1, these three registers will be modified simultaneously; the remaining bytes in the row will be unaffected. Note that E2PAR2 is internally reset at the end of the programming cycle. This implies that the user must set the E2PAR2 bit between two parallel programming cycles. Note that if the user tries to set E2PAR1 while E2PAR2 is not set, there will be no programming cycle and the E2PAR1 bit will be unaffected. Consequently, the E2PAR1 bit cannot be set if E2ENA is low. The E2PAR1 bit can be set by the user, only if the E2ENA and E2PAR2 bits are also set. Table 4. Row Arrangement for Parallel Writing of EEPROM Locations Dataspace addresses. Banks 0 and 1. Byte ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 0 1 2 3 4 5 6 7 38h-3Fh 30h-37h 28h-2Fh 20h-27h 18h-1Fh 10h-17h 08h-0Fh ROW0 00h-07h Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode. The number of available 64-byte banks (1 or 2) is device dependent. 12/70 474 ST62T65B/E65B ST62T65B/E65B 1.5 PROGRAMMING MODES 1.5.1 Option Byte The Option Byte allows configuration capability to the MCUs. Option byte's content is automatically read, and the selected options enabled, when the chip reset is activated. It can only be accessed during the mode. This access is made either (copy from a master device) or by OPTION BYTE PROGRAMMING programmer. programming automatically selecting the mode of the The option byte is located in a non-user map. No address has to be specified. EPROM Code Option Byte 7 PRO- EXTCTECT NTL 0 - - WDACT DELAY OSCIL - PROTECT. This bit allows the protection of the software contents against piracy. When the bit PROTECT is set high, readout of the OTP contents is prevented by hardware. No programming equipment is able to gain access to the user program. When this bit is low, the user program can be read. EXTCNTL. This bit selects the External STOP Mode capability. When EXTCNTL is high, pin NMI controls if the STOP mode can be accessed when the watchdog is active. In addition, PB0 is forced as open drain output. When EXTCNTL is low, the STOP instruction is processed as a WAIT as soon as the watchdog is active. D5-D4. Reserved. Must be cleared to zero. WDACT. This bit controls the watchdog activation. When it is high, hardware activation is selected. The software activation is selected when WDACT is low. DELAY. This bit enables the selection of the delay internally generated after pin RESET is released. When DELAY is low, the delay is 2048 cycles of the oscillator, it is of 32768 cycles when DELAY is high. OSCIL. When this bit is low, the oscillator must be controlled by a quartz crystal, a ceramic resonator or an external frequency. When it is high, the oscillator must be controlled by an RC network, with only the resistor having to be externally provided. D0. Reserved. Must be cleared to zero. The Option byte is written during programming either by using the PC menu (PC driven Mode) or automatically (stand-alone mode) 1.5.2 Program Memory EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/VPP pin. The programming flow of the ST62T65B/E65B ST62T65B/E65B is described in the User Manual of the EPROM Programming Board. The MCUs can be programmed with the ST62E6xB EPROM programming tools available from SGS-THOMSON. Table 5. ST62E65B/T65B ST62E65B/T65B Program Memory Map Device Address Description 0000h-007Fh 0080h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh Reserved User ROM Reserved Interrupt Vectors Reserved NMI Interrupt Vector Reset Vector Note: OTP/EPROM devices can be programmed with the development tools available from SGS-THOMSON (ST62E6X-EPB ST62E6X-EPB or ST626X-KIT ST626X-KIT). 1.5.3 EEPROM Data Memory EEPROM data pages are supplied in the virgin state 00h. Partial or total programming of EEPROM data memory can be performed either through the application software, or through an external programmer. Any SGS-THOMSON tool used for the program memory (OTP/EPROM) can also be used to program the EEPROM data memory. 13/70 475 ST62T65B/E65B ST62T65B/E65B PROGRAMMING MODES (Cont'd) 1.5.4 EPROM Erasing The EPROM of the windowed package of the MCUs may be erased by exposure to Ultra Violet light. The erasure characteristic of the MCUs is such that erasure begins when the memory is exposed to light with a wave lengths shorter than approximately 4000Å. It should be noted that sunlights and some types of fluorescent lamps have wavelengths in the range 3000-4000Å. It is thus recommended that the window of the MCUs packages be covered by an opaque label to 14/70 476 prevent unintentional erasure problems when testing the application in such an environment. The recommended erasure procedure of the MCUs EPROM is the exposure to short wave ultraviolet light which have a wave-length 2537A. The integrated dose (i.e. U.V. intensity x exposure time) for erasure should be a minimum of 15Wsec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000µW/cm 2 power rating. The ST62E65B ST62E65B should be placed within 2.5cm (1Inch) of the lamp tubes during erasure. ST62T65B/E65B ST62T65B/E65B 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought of as an independent central processor communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control buses. In-core communication is arranged as shown in Figure 6; the controller being externally linked to both the Reset and Oscillator circuits, while the core is linked to the dedicated on-chip peripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers. 2.2 CPU REGISTERS The ST6 Family CPU core features six registers and three pairs of flags available to the programmer. These are described in the following paragraphs. Accumulator (A). The accumulator is an 8-bit general purpose register used in all arithmetic calculations, logical operations, and data manipulations. The accumulator can be addressed in Data space as a RAM location at address FFh. Thus the ST6 can manipulate the accumulator just like any other register in Data space. Indirect Registers (X, Y). These two indirect registers are used as pointers to memory locations in Data space. They are used in the register-indirect addressing mode. These registers can be addressed in the data space as RAM locations at addresses 80h (X) and 81h (Y). They can also be accessed with the direct, short direct, or bit direct addressing modes. Accordingly, the ST6 instruction set can use the indirect registers as any other register of the data space. Short Direct Registers (V, W). These two registers are used to save a byte in short direct addressing mode. They can be addressed in Data space as RAM locations at addresses 82h (V) and 83h (W). They can also be accessed using the direct and bit direct addressing modes. Thus, the ST6 instruction set can use the short direct registers as any other register of the data space. Program Counter (PC). The program counter is a 12-bit register which contains the address of the next ROM location to be processed by the core. This ROM location may be an opcode, an operand, or the address of an operand. The 12-bit length allows the direct addressing of 4096 bytes in Program space. Figure 6. ST6 Core Block Diagram 0,01 TO 8MHz RESET OSCin OSCout INTERR UPTS CONTROLLER DATA SPACE OPCODE FLAG VALUES CONTROL SIGNALS DATA ADDRESS/READ LINE 2 RAM/EEPR OM PROGRAM ADDRES S 256 DECODER ROM/EPROM A-DATA B-DATA DATA ROM/EPROM DEDIC ATIONS ACCUMULATO R 12 Program Counter and 6 LAYER STACK FLAGS ALU RESULTS TO DATA SPACE (WRITE LINE) 15/70 477 ST62T65B/E65B ST62T65B/E65B CPU REGISTERS (Cont'd) However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register. The PC value is incremented after reading the address of the current instruction. To execute relative jumps, the PC and the offset are shifted through the ALU, where they are added; the result is then shifted back into the PC. The program counter can be changed in the following ways: - JP (Jump) instructionPC=Jump address - CALL instructionPC= Call address - Relative Branch Instruction.PC= PC +/- offset - Interrupt PC=Interrupt vector - ResetPC= Reset vector - RET & RETI instructionsPC= Pop (stack) - Normal instructionPC= PC + 1 Flags (C, Z). The ST6 CPU includes three pairs of flags (Carry and Zero), each pair being associated with one of the three normal modes of operation: Normal mode, Interrupt mode and Non Maskable Interrupt mode. Each pair consists of a CARRY flag and a ZERO flag. One pair (CN, ZN) is used during Normal operation, another pair is used during Interrupt mode (CI, ZI), and a third pair is used in the Non Maskable Interrupt mode (CNMI, ZNMI). The ST6 CPU uses the pair of flags associated with the current mode: as soon as an interrupt (or a Non Maskable Interrupt) is generated, the ST6 CPU uses the Interrupt flags (resp. the NMI flags) instead of the Normal flags. When the RETI instruction is executed, the previously used set of flags is restored. It should be noted that each flag set can only be addressed in its own context (Non Maskable Interrupt, Normal Interrupt or Main routine). The flags are not cleared during context switching and thus retain their status. The Carry flag is set when a carry or a borrow occurs during arithmetic operations; otherwise it is cleared. The Carry flag is also set to the value of the bit tested in a bit test instruction; it also participates in the rotate left instruction. The Zero flag is set if the result of the last arithmetic or logical operation was equal to zero; otherwise it is cleared. Switching between the three sets of flags is performed automatically when an NMI, an interrupt or a RETI instructions occurs. As the NMI mode is 16/70 478 automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags. Stack. The ST6 CPU includes a true LIFO hardware stack which eliminates the need for a stack pointer. The stack consists of six separate 12-bit RAM locations that do not belong to the data space RAM area. When a subroutine call (or interrupt request) occurs, the contents of each level are shifted into the next higher level, while the content of the PC is shifted into the first level (the original contents of the sixth stack level are lost). When a subroutine or interrupt return occurs (RET or RETI instructions), the first level register is shifted back into the PC and the value of each level is popped back into the previous level. Since the accumulator, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subroutine. The stack will remain in its "deepest" position if more than 6 nested calls or interrupts are executed, and consequently the last return address will be lost. It will also remain in its highest position if the stack is empty and a RET or RETI is executed. In this case the next instruction will be executed. Figure 7. ST6 CPU Programming Mode l b7 X REG. POINTER b0 b7 INDEX REGISTER Y REG. POINTER b0 SHORT DIRECT ADD RESSING MODE b0 b7 W REGISTER b0 b7 b11 V REGISTER b7 ACCUMULATOR b0 b0 PROGRAM COUNTER SIX LEVELS STACK REGISTER NORMAL FLAGS C Z INTERRUPT FLAGS C Z NMI FLAGS C Z VA000423 VA000423 ST62T65B/E65B ST62T65B/E65B 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suitable ceramic resonator, or with an external resistor (RNET). Figure 8. Oscillator Configurations CRYSTAL/R ESONATO R CLOCK CRYSTAL /RESON ATOR option Figure 8 illustrates various possible oscillator configurations using an external crystal or ceramic resonator, an external clock input, an external resistor (RNET). CL1 an CL2 should have a capacitance in the range 12 to 22 pF for an oscillator frequency in the 4-8 MHz range. Thevalue of RNET can be obtained by referring to Figure 33 and Figure 34. Aprogrammable divider isprovided in order to adjust the internal clock of the MCU to the best power consumption and performance trade-off. The internal MCU clock frequency (fINT) drives directly the AR TIMER while it is divided by 12 to drive the TIMER, the A/D converter and the Watchdog timer, and by 13 to drive the CPU core, as may be seen in Figure 9. ST6xxx OSCin OSCout CL1n CL2 EXTERNAL CLOCK CRYSTAL/R ESONATOR option With an 8MHz oscillator frequency, the fastest machine cycle is therefore 1.625µs. ST6xxx A machine cycle is the smallest unit of time needed to execute any operation (for instance, to increment the Program Counter). An instruction may require two, four, or five machine cycles for execution. 3.1.1 Main Oscillator The oscillator configuration may be specified by selecting the appropriate option. When the CRYSTAL/RESONATOR option is selected, it must be used with a quartz crystal, a ceramic resonator or an external signal provided on the OSCin pin. When the RC NETWORK option is selected, the system clock is generated by an external resistor. OSCin OSC out NC RC NETWORK RC NETW ORK option ST6xxx OSCin OSC out NC RNET 17/70 479 ST62T65B/E65B ST62T65B/E65B CLOCK SYSTEM (Cont'd) Oscillator Control Registers Address: DCh - Write only 7 0 - - - OSCR OSCR 3 2 - RS1 RS0 Bit 7-4. These bits are not used. Bit 3. Reserved. Cleared at Reset. THIS BIT MUST BE SET TO 1 BY USER PROGRAM to achieve lowest power consumption. Note: Care is required when handling the OSCR register as some bits are write only. For this reason, it is not allowed to change the OSCR contents while executing interrupt service routine, as the service routine cannot save and then restore its previous content. If it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a RAM location, and each time the program writes to OSCR it must write also to the image register. The image register must be written first, so if an interrupt occurs between the two instructions the OSCR is not affected. Bit 2. Reserved. Must be kept low. RS1-RS0. These bits select the division ratio of the Oscillator Divider in order to generate the internal frequency. The following selctions are available: RS1 0 0 1 1 RS0 0 1 0 1 Division Ratio 1 2 4 4 Figure 9. Clock Circuit Block Diagram POR fOSC Core OSCin : 13 fOSC SPI Timer MAIN OSCILLATOR OSCILLATOR fINT : 12 Watchdog DIVIDER ADC OSCout :1 RS0, RS1 18/70 480 AR Timer ST62T65B/E65B ST62T65B/E65B 3.2 RESETS The MCU can be reset in three ways: ­ by the external Reset input being pulled low; ­ by Power-on Reset; ­ by the digital Watchdog peripheral timing out. 3.2.1 RESET Input The RESET pin may be connected to a device of the application board in order to reset the MCU if required. The RESET pin may be pulled low in RUN, WAIT or STOP mode. This input can be used to reset the MCU internal state and ensure a correct start-up procedure. The pin is active low and features a Schmitt trigger input. The internal Reset signal is generated by adding a delay to the external signal. Therefore even short pulses on the RESET pin are acceptable, provided VDD has completed its rising phase and that the oscillator is running correctly (normal RUN or WAIT modes). The MCU is kept in the Reset state as long as the RESET pin is held low. The internal delay is generated by an on-chip counter. The internal reset line is released 2048 internal clock cycles after release of the external reset. Notes: To ensure correct start-up, the user should take care that the reset signal is not released before the VDD level is sufficient to allow MCU operation at the chosen frequency (see Recommended Operating Conditions). A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. Figure 10. Reset and Interrupt Processing RESE T NMI MAS K SE T INT LAT CH CLEA RED ( IF PRES ENT ) If RESET activation occurs in the RUN or WAIT modes, processing of the user program is stopped (RUN mode only), the Inputs and Outputs are configured as inputs with pull-up resistors and the main Oscillator is restarted. When the level on the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period. If RESET pin activation occurs in the STOP mode, the oscillator starts up and all Inputs and Outputs are configured as inputs with pull-up resistors. When the level of the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period. 3.2.2 Power-on Reset The function of the POR circuit consists in waking up the MCU at an appropriate stage during the power-on sequence. At the beginning of this sequence, the MCU is configured in the Reset state: all I/O ports are configured as inputs with pull-up resistors and no instruction is executed. When the power supply voltage rises to a sufficient level, the oscillator starts to operate, whereupon an internal delay is initiated, in order to allow the oscillator to fully stabilize before executing the first instruction. The initialization sequence is executed immediately following the internal delay. SE LECT NMI MODE FLAGS PUT FFE H ON ADDRESS BUS YES IS RESET ST ILL PRESENT ? NO LOAD PC FROM RESE T LOCATIONS FFE / FFF FE TCH INST RUCTION VA 000427 19/70 481 ST62T65B/E65B ST62T65B/E65B RESETS (Cont'd) 3.2.3 Watchdog Reset The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. This, amongst other things, resets the watchdog counter. The MCU restarts just as though the Reset had been generated by the RESET pin, including the built-in stabilisation delay period. 3.2.4 Application Notes Reset, the Interrupt flag is automatically set, so that the CPU is in Non Maskable Interrupt mode; this prevents the initialisation routine from being interrupted. The initialisation routine should therefore be terminated by a RETI instruction, in order to revert to normal mode and enable interrupts. If no pending interrupt is present at the end of the initialisation routine, the MCU will continue by processing the instruction immediately following the RETI instruction. If, however, a pending interrupt is present, it will be serviced. Figure 11. Reset and Interrupt Processing No external resistor is required between VDD and the Reset pin, thanks to the built-in pull-up device. RESET The POR circuit operates dynamically, in that it triggers MCU initialization on detecting the rising edge of VDD. The typical threshold is in the region of 2 volts, but the actual value of the detected threshold depends on the way in which VDD rises. The POR circuit is NOT designed to supervise static, or slowly rising or falling VDD. 3.2.5 MCU Initialization Sequence When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (located in program ROM starting at address 0FFEh). A jump to the beginning of the user program must be coded at this address. Following a JP RESET VECTOR JP: 2 BYTES/4 CYCLES INITIALIZATION ROUTINE RETI RETI: 1 BYTE/2 CYCLES VA00181 VA00181 Figure 12. Reset Block Diagram VDD fOSC 300k RESET WATCHDOG RESET 20/70 482 COUNTER RESET 2.8k POWER ON RESET ST6 INTER NAL RESET CK RESET ST62T65B/E65B ST62T65B/E65B RESETS (Cont'd) Table 6. Register Reset Status Register Oscillator Control Register Address(es) 0DCh Status EEPROM Control Register 0EAh fINT = fOSC; user must set bit3 to 1 EEPROM disabled Port Data Registers 0C0h to 0C2h I/O are Input with pull-up Port Direction Register 0C4h to 0C6h I/O are Input with pull-up Port Option Register 0CCh to 0CEh I/O are Input with pull-up Interrupt Option Register 0C8h Interrupt disabled TIMER Status/Control 0D4h AR TIMER Mode Control Register 0D5h AR TIMER Status/Control 1 Register 0D6h AR TIMER Status/Control 2Register 0D7h AR TIMER Compare Register 0DAh Miscellaneous Register 0DDh SPI Output not connected to PC3 SPI Registers 0E0h to 0E2h SPI disabled X, Y, V, W, Register 080H TO 083H Accumulator 0FFh Data RAM 084h to 0BFh Data RAM Page REgister 0E8h Data ROM Window Register 0C9h EEPROM 00h to 03Fh A/D Result Register 0D0h AR TIMER Load Register 0DBh AR TIMER Reload/Capture Register TIMER Counter Register 0D9h 0D3h TIMER Prescaler Register 0D2h 7Fh Watchdog Counter Register 0D8h FEh A/D Control Register 0D1h 40h 00h Comment TIMER disabled AR TIMER stopped Undefined As written if programmed FFh Max count loaded A/D in Standby 21/70 483 ST62T65B/E65B ST62T65B/E65B 3.3 DIGITAL WATCHDOG The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. The Watchdog circuit generates a Reset when the downcounter reaches zero. User software can prevent this reset by reloading the counter, and should therefore be written so that the counter is regularly reloaded while the user program runs correctly. In the event of a software mishap (usually caused by externally generated interference), the user program will no longer behave in its usual fashion and the timer register will thus not be reloaded periodically. Consequently the timer will decrement down to 00h and reset the MCU. In order to maximise the effectiveness of the Watchdog function, user software must be written with this concept in mind. Watchdog behaviour is governed by two options, known as "WATCHDOG ACTIVATION" (i.e. HARDWARE or SOFTWARE) and "EXTERNAL STOP MODE CONTROL" (see Table 7). In the SOFTWARE option, the Watchdog is disabled until bit C of the DWDR register has been set. When the Watchdog is disabled, low power Stop mode is available. Once activated, the Watchdog cannot be disabled, except by resetting the MCU. In the HARDWARE option, the Watchdog is permanently enabled. Since the oscillator will run continuously, low power mode is not available. The STOP instruction is interpreted as a WAIT instruction, and the Watchdog continues to countdown. However, when the EXTERNAL STOP MODE CONTROL option has been selected low power consumption may be achieved in Stop Mode. Execution of the STOP instruction is then governed by a secondary function associated with the NMI pin. If a STOP instruction is encountered when the NMI pin is low, it is interpreted as WAIT, as described above. If, however, the STOP instruction is encountered when the NMI pin is high, the Watchdog counter is frozen and the CPU enters STOP mode. When the MCU exits STOP mode (i.e. when an interrupt is generated), the Watchdog resumes its activity. Note: when the EXTERNAL STOP MODE CONTROL option has been selected, port PB0 must be defined as an open-drain output. Table 7. Recommended Option Choices Function s Required Stop Mode & Watchdog Stop Mode Watchdog 22/70 484 Recommended Optio ns "EXTERNAL STOP MODE" & "HARDWARE WATCHDOG" "SOFTWARE WATCHDOG" "HARDWARE WATCHDOG" ST62T65B/E65B ST62T65B/E65B DIGITAL WATCHDOG (Cont'd) Only the 6 most significant bits may be used to define the time period, since it is bit 6 which triggers the Reset when it changes to "0". This offers the user a choice of 64 timed periods ranging from 3,072 to 196,608 clock cycles (with an oscillator frequency of 8MHz, this is equivalent to timer periods ranging from 384µs to 24.576ms). D0 C D1 SR D2 D3 D4 D5 WATCHDOG COUNTER It should be noted that the order of the bits in the DWDR register is inverted with respect to the associated bits in the down counter: bit 7 of the DWDR register corresponds, in fact, to T0 and bit 2 to T5. The user should bear in mind the fact that these bits are inverted and shifted with respect to the physical counter bits when writing to this register. The relationship between the DWDR register bits and the physical implementation of the Watchdog timer downcounter is illustrated in Figure 13. Figure 13. Watchdog Counter Control WATCHDOG CONTROL REGISTER The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, location 0D8h) which is described in greater detail in Section 3.3.1. This register is set to 0FEh on Reset: bit C is cleared to "0", which disables the Watchdog; the timer downcounter bits, T0 to T5, and the SR bit are all set to "1", thus selecting the longest Watchdog timer period. This time period can be set to the user's requirements by setting the appropriate value for bits T0 to T5 in the DWDR register. The SR bit must be set to "1", since it is this bit which generates the Reset signal when it changes to "0"; clearing this bit would generate an immediate Reset. RESET T5 T4 T3 T2 D6 T1 D7 T0 OSC-12 OSC-12 23/70 485 ST62T65B/E65B ST62T65B/E65B DIGITAL WATCHDOG (Cont'd) 3.3.1 Digital Watchdog Register (DWDR) Address: 0D8h 3.3.2 Application Notes - Read/Write Reset status: 1111 1110b 7 T0 0 T1 T2 T3 T4 T5 SR C Bit 0 = C: Watchdog Control bit If the hardware option is selected, this bit is forced high and the user cannot change it (the Watchdog is always active). When the software option is selected, the Watchdog function is activated by setting bit C to 1, and cannot then be disabled (save by resetting the MCU). When C is kept low the counter can be used as a 7-bit timer. This bit is cleared to "0" on Reset. Bit 1 = SR: Software Reset bit This bit triggers a Reset when cleared. When C = "0" (Watchdog disabled) it is the MSB of the 7-bit timer. This bit is set to "1" on Reset. Bits 2-7 = T5-T0: Downcounter bits It should be noted that the register bits are reversed and shifted with respect to the physical counter: bit-7 (T0) is the LSB of the Watchdog downcounter and bit-2 (T5) is the MSB. These bits are set to "1" on Reset. 24/70 486 The Watchdog plays an important supporting role in the high noise immunity of ST62xx devices, and should be used wherever possible. Watchdog related options should be selected on the basis of a trade-off between application security and STOP mode availability. When STOP mode is not required, hardware activation without EXTERNAL STOP MODE CONTROL should be preferred, as it provides maximum security, especially during power-on. When STOP mode is required, hardware activation and EXTERNAL STOP MODE CONTROL should be chosen. NMI should be high by default, to allow STOP mode to be entered when the MCU is idle. The NMI pin can be connected to PB0 (see Figure 14) to allow its state to be controlled by software. PB0 can then be used to keep NMI low while Watchdog protection is required, or to avoid noise or key bounce. When no more processing is required, PB0 is released and the device placed in STOP mode for lowest power consumption. When software activation is selected and the Watchdog is not activated, the downcounter may be used as a simple 7-bit timer (remember that the bits are in reverse order). The software activation option should be chosen only when the Watchdog counter is to be used as a timer. To ensure the Watchdog has not been unexpectedly activated, the following instructions should be executed within the first 27 instructions: jrr 0, WD, #+3 ldi WD, 0FDH ST62T65B/E65B ST62T65B/E65B DIGITAL WATCHDOG (Cont'd) These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. In all modes, a minimum of 28 instructions are executed after activation, before the Watchdog can generate a Reset. Consequently, user software should load the watchdog counter within the first 27 instructions following Watchdog activation (software mode), or within the first 27 instructions executed following a Reset (hardware activation). Figure 14. A typical circuit making use of the EXERNAL STOP MODE CONTROL feature SWITCH NMI PB0 It should be noted that when the GEN bit is low (interrupts disabled), the NMI interrupt is active but cannot cause a wake up from STOP/WAIT modes. VR02002 VR02002 Figure 15. Digital Watchdog Block Diagram RESET Q RSFF R S -27 DB1.7 LOAD SET DB0 -2 8 SET -12 OSCILLATOR CLOCK 8 WRITE RESET DATA BUS VA00010 VA00010 25/70 487 ST62T65B/E65B ST62T65B/E65B 3.4 INTERRUPTS The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is associated with a specific Interrupt Vector which contains a Jump instruction to the associated interrupt service routine. These vectors are located in Program space (see Table 8). When an interrupt source generates an interrupt request, and interrupt processing is enabled, the PC register is loaded with the address of the interrupt vector (i.e. of the Jump instruction), which then causes a Jump to the relevant interrupt service routine, thus servicing the interrupt. Table 8. Interrupt Vector Map Associated Vector Interrupt vector #0 NMI pin (NMI) Port A, B Interrupt vector #1 Port C, SPI Interrupt vector #2 ARTIMER peripheral Interrupt vector #3 TIMER and ADC Interrupt vector #4 peripherals Interrupt Source Vector Address (FFCh-FFDh) (FF6h-FF7h) (FF4h-FF5h) (FF2h-FF3h) (FF0h-FF1h) 3.4.1 Interrupt Vectors Interrupt vectors are Jump addresses to the associated service routine, which reside in specific areas of Program space. The following vectors are present: The interrupt vector associated with the nonmaskable interrupt source is referred to as Interrupt Vector #0. It is located at addresses 0FFCh and 0FFDh in Program space. This vector is associated with the falling edge sensitive Non Maskable Interrupt pin (NMI). 26/70 488 ­ The interrupt vector associated with Port A and B pins is referred to as interrupt vector #1. It is located at addresses 0FF6h, 0FF7h is named. It can be programmed either as falling edge sensitive or as low level sensitive, by setting the Interrupt Option Register (IOR) accordingly. ­ The interrupt vector associated with Port C pins and SPI is referred to as interrupt vector #2. It is located at addresses 0FF4h, 0FF5h is named . It can be programmed either as falling edge sensitive or as rising edge sensitive, by setting the Interrupt Option Register (IOR) accordingly. ­ The two interrupt vectors located respectively at addresses 0FF2h, 0FF3h and addresses 0FF0h, 0FF1h are respectively known as Interrupt Vectors #3 and #4. Vector #3 is associated with the ARTIMER peripheral and vector #4 with the A/D Converter or Timer peripherals. Each on-chip peripheral has an associated interrupt request flag (A/D Converter, OVF, CPF and EF for the ARTIMER, SPRUN for the SPI), which is set to "1" when the peripheral generates an interrupt request. Each on-chip peripheral also has an associated mask bit (A/D Converter, OVIE and EIE for the ARTIMER, SPIE for the SPI), which must be set to "1" to enable the associated interrupt request. 3.4.2 Interrupt Priorities The Non Maskable Interrupt request has the highest priority and can interrupt any interrupt routine at any time; the other four interrupts cannot interrupt each other. If more than one interrupt request is pending, these are processed by the processor core according to their priority level: vector #1 has the higher priority while vector #4 the lower. The priority of each interrupt source is fixed. ST62T65B/E65B ST62T65B/E65B IINTERRUPTS (Cont'd) 3.4.3 Interrupt Option Register (IOR) 3.4.4 External Interrupt Operating Modes The Interrupt Option Register (IOR) is used to enable/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register is write-only and cannot be accessed by single-bit operations. Address: 0C8h - Write Only Reset status: 00h 7 - 0 LES ESB GEN - - - - Bit 7, Bits 3-0 = Unused. Bit 6 = LES: Level/Edge Selection bit. When this bit is set to one, the interrupt #1 (Port A, B) is low level sensitive, when cleared to zero the negative edge sensitive interrupt is selected. Bit 5 = ESB: Edge Selection bit. When this bit is set to one, the interrupt #2 (Port C, SPI) is positive edge sensitive, when cleared to zero the negative edge sensitive interrupt is selected. Bit 4 = GEN: Global Enable Interrupt. When this bit is set to one, all interrupts are enabled. When this bit is cleared to zero all the interrupts (excluding NMI) are disabled. When the GEN bit is low, the NMI interrupt is active but cannot cause a wake up from STOP/WAIT modes. This register is cleared on reset. Table 9. Interrupt Options SET GEN LES ESB CLEARED Enables all interrupts Disables all interrupts (Except NMI) SET Rising edge mode on Port A, B CLEARED Falling edge mode on Port A, B SET Level sensitive mode on Port C, SPI CLEARED Falling edge mode on Port C, SPI The NMI interrupt is associated with the external interrupt pin. This pin is falling edge sensitive and the interrupt pin signal is latched by a flip-flop which is automatically reset by the core at the beginning of the non-maskable interrupt service routine. A Schmitt trigger is present on the NMI pin. The user can choose to have an on-chip pull-up on the NMI pin by specifying the appropriate ROM mask option (see Option List at the end of the Datasheet). The two interrupt sources associated with the falling/rising edge mode of the external interrupt pins (Port A, B-vector #1, Port C, SPI-vector #2) are connected to two internal latches. Each latch is set when a falling/rising edge occurs during the processing of the previous one, will be processed as soon as the first one has been serviced (unless a higher priority interrupt request is present). If more than one interrupt occurs while processing the first one, the subsequent ones will be lost. Storage of interrupt requests is not available in level sensitive detection mode. To be taken into account, the low level must be present on the interrupt pin when the MCU samples the line after instruction execution. At the end of every instruction, the MCU tests the interrupt lines: if there is an interrupt request the next instruction is not executed and the appropriate interrupt service routine is executed instead. When the GEN bit is low, the NMI interrupt is active but cannot cause a wake up from STOP/WAIT modes. 3.4.5 Interrupt Procedure The interrupt procedure is very similar to a call procedure, indeed the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context and the time at which it occurred. As a result, the user should save all Data space registers which may be used within the interrupt routines. There are separate sets of processor flags for normal, interrupt and non-maskable interrupt modes, which are automatically switched and so do not need to be saved. 27/70 489 ST62T65B/E65B ST62T65B/E65B IINTERRUPTS (Cont'd) The following list summarizes the interrupt procedure: software stack. After the RETI instruction is executed, the MCU returns to the main routine. MCU ­ The interrupt is detected. ­ The C and Z flags are replaced by the interrupt flags (or by the NMI flags). ­ The PC contents are stored in the first level of the stack. ­ The normal interrupt lines are inhibited (NMI still active). ­ The first internal latch is cleared. ­ The associated interrupt vector is loaded in the PC. Figure 16. Interrupt Processing Flow Chart User ­ User selected registers are saved within the interrupt service routine (normally on a software stack). ­ The source of the interrupt is found by polling the interrupt flags (if more than one source is associated with the same vector). ­ The interrupt is serviced. ­ Return from interrupt (RETI) MCU ­ Automatically the MCU switches back to the normal flag set (or the interrupt flag set) and pops the previous PC value from the stack. INSTRUCTION FETCH INSTRUCTION EXECUTE INSTRUCTION WAS THE INSTRUCTION A RETI NO LOAD PC FROM INTERRUPT VECTOR ( FFC / FFD ) YES YES IS THE CORE ALREADY IN NORMAL MODE ? ? SET INTERRUPT MASK NO CLEAR INTERRUPT MASK PUSH THE PC INTO THE STACK SELECT PROGRAM FLAGS SELECT INTERNAL MODE FLAG " POP " THE STACKED PC NO CHECK IF THERE IS AN INTERRUPT REQUEST AND INTERRUPT MASK ? YES The interrupt routine usually begins by the identifying the device which generated the interrupt request (by polling). The user should save the registers which are used within the interrupt routine in a VA0 000 14 Table 10. Interrupt Requests and Mask Bits GENERAL TIMER A/D CONVERTER IOR TSCR1 ADCR Address Register C8h D4h D1h AR TIMER ARMC D5h SPI Port PAn Port PBn Port PCn SPIMOD ORPA-DRPA ORPB-DRPB ORPC-DRPC E2h C0h-C4h C1h-C5h C2h-C6h Peripheral 28/70 490 Register Mask bit Masked Interrupt Source GEN ETI EAI OVIE CPIE EIE SPIE ORPAn-DRPAn ORPBn-DRPBn ORPCn-DRPCn Interrupt vector All Interrupts, excluding NMI TMZ: TIMER Overflow EOC: End of Conversion OVF: AR TIMER Overflow CPF: Successful compare EF: Active edge on ARTIMin SPRUN: End of Transmission PAn pin PBn pin PCn pin Vector 4 Vector 4 Vector 3 Vector Vector Vector Vector 2 1 1 2 ST62T65B/E65B ST62T65B/E65B INTERRUPTS (Cont'd) Figure 17. Interrupt Block Diagram FROM REGISTER PORT A,B,C SINGLE BIT ENABLE PBE V DD FF CLK Q CLR PORT A PORT B Bits PBE 0 INT #1 (FF6,7) I Start MUX 1 1 IOR REG. C8H, bit 6 PORT C Bits FF CLK Q CLR PBE RESTART FROM STOP/WAIT INT #2 (FF4,5) SPI IOR REG. C8H, bit 5 I 2 Start OVF OVIE AR TIMER CPF CPIE INT #3 (FF2,3) EF EIE NMI TIMER1 TMZ ETI ADC VDD EOC EAI INT #4 (FF0,1) FF CLK Q CLR NMI (FFC,D) I0 Start Bit GEN (IOR Register) VA0426K VA0426K 29/70 491 ST62T65B/E65B ST62T65B/E65B 3.5 POWER SAVING MODES The WAIT and STOP modes have been implemented in the ST62xx family of MCUs in order to reduce the product's electrical consumption during idle periods. These two power saving modes are described in the following paragraphs. 3.5.1 WAIT Mode The MCU goes into WAIT mode as soon as the WAIT instruction is executed. The microcontroller can be considered as being in a "software frozen" state where the core stops processing the program instructions, the RAM contents and peripheral registers are preserved as long as the power supply voltage is higher than the RAM retention voltage. In this mode the peripherals are still active. WAIT mode can be used when the user wants to reduce the MCU power consumption during idle periods, while not losing track of time or the capability of monitoring external events. The active oscillator is not stopped in order to provide a clock signal to the peripherals. Timer counting may be enabled as well as the Timer interrupt, before entering the WAIT mode: this allows the WAIT mode to be exited when a Timer interrupt occurs. The same applies to other peripherals which use the clock signal. If the WAIT mode is exited due to a Reset (either by activating the external pin or generated by the Watchdog), the MCU enters a normal reset procedure. If an interrupt is generated during WAIT mode, the MCU's behaviour depends on the state 30/70 492 of the processor core prior to the WAIT instruction, but also on the kind of interrupt request which is generated. This is described in the following paragraphs. The processor core does not generate a delay following the occurrence of the interrupt, because the oscillator clock is still available and no stabilisation period is necessary. 3.5.2 STOP Mode If the Watchdog is disabled, STOP mode is available. When in STOP mode, the MCU is placed in the lowest power consumption mode. In this operating mode, the microcontroller can be considered as being "frozen", no instruction is executed, the oscillator is stopped, the RAM contents and peripheral registers are preserved as long as the power supply voltage is higher than the RAM retention voltage, and the ST62xx core waits for the occurrence of an external interrupt request or a Reset to exit the STOP state. If the STOP state is exited due to a Reset (by activating the external pin) the MCU will enter a normal reset procedure. Behaviour in response to interrupts depends on the state of the processor core prior to issuing the STOP instruction, and also on the kind of interrupt request that is generated. This case will be described in the following paragraphs. The processor core generates a delay after occurrence of the interrupt request, in order to wait for complete stabilisation of the oscillator, before executing the first instruction. ST62T65B/E65B ST62T65B/E65B POWER SAVING MODE (Cont'd) 3.5.3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an interrupt occurs (not a Reset). It should be noted that the restart sequence depends on the original state of the MCU (normal, interrupt or non-maskable interrupt mode) prior to entering WAIT or STOP mode, as well as on the interrupt type. Interrupts do not affect the oscillator selection. 3.5.3.1 Normal Mode If the MCU was in the main routine when the WAIT or STOP instruction was executed, exit from Stop or Wait mode will occur as soon as an interrupt occurs; the related interrupt routine is executed and, on completion, the instruction which follows the STOP or WAIT instruction is then executed, providing no other interrupts are pending. 3.5.3.2 Non Maskable Interrupt Mode If the STOP or WAIT instruction has been executed during execution of the non-maskable interrupt routine, the MCU exits from the Stop or Wait mode as soon as an interrupt occurs: the instruction which follows the STOP or WAIT instruction is executed, and the MCU remains in non-maskable interrupt mode, even if another interrupt has been generated. 3.5.3.3 Normal Interrupt Mode If the MCU was in interrupt mode before the STOP or WAIT instruction was executed, it exits from STOP or WAIT mode as soon as an interrupt occurs. Nevertheless, two cases must be considered: ­ If the interrupt is a normal one, the interrupt routine in which the WAIT or STOP mode was en- tered will be completed, starting with the execution of the instruction which follows the STOP or the WAIT instruction, and the MCU is still in the interrupt mode. At the end of this routine pending interrupts will be serviced in accordance with their priority. ­ In the event of a non-maskable interrupt, the non-maskable interrupt service routine is processed first, then the routine in which the WAIT or STOP mode was entered will be completed by executing the instruction following the STOP or WAIT instruction. The MCU remains in normal interrupt mode. Notes: To achieve the lowest power consumption during RUN or WAIT modes, the user program must take care of: ­ configuring unused I/Os as inputs without pull-up (these should be externally tied to well defined logic levels); ­ placing all peripherals in their power down modes before entering STOP mode; When the hardware activated Watchdog is selected, or when the software Watchdog is enabled, the STOP instruction is disabled and a WAIT instruction will be executed in its place. If all interrupt sources are disabled (GEN low), the MCU can only be restarted by a Reset. Although setting GEN low does not mask the NMI as an interrupt, it will stop it generating a wake-up signal. The WAIT and STOP instructions are not executed if an enabled interrupt request is pending. 31/70 493 ST62T65B/E65B ST62T65B/E65B 4 ON-CHIP PERIPHERALS 4.1 I/O PORTS The MCU features 21 Input/Output lines which may be individually programmed as any of the following input or output configurations: ­ Input without pull-up or interrupt ­ Input with pull-up and interrupt ­ Input with pull-up, but without interrupt ­ Analog input (PA0-PA7, PC0-PC4) ­ Artimer I/O lines : PB6-PB7 ­ Push-pull output ­ Standard Open drain output ­ 20mA Open drain output (PB0-PB5, PB6-PB7) The lines are organized as three Ports (A, B and C). Each port is associated with 3 registers in Data space. Each bit of these registers is associated with a particular line (for instance, bits 0 of Port A Data, Direction and Option registers are associated with the PA0 line of Port A). The three DATA registers (DRA, DRB and DRC), are used to read the voltage level values of the lines which have been configured as inputs, or to write the logic value of the signal to be output on the lines configured as outputs. The port data registers can be read to get the effective logic levels of the pins, but they can be also written by user software, in conjunction with the related option registers, to select the different input mode options. Single-bit operations on I/O registers are possible but care is necessary because reading in input mode is done from I/O pins while writing will directly affect the Port data register causing an undesired change of the input configuration. The three Data Direction registers (DDRA, DDRB AND DRC) allow the data direction (input or output) of each pin to be set. The three Option registers (ORA, ORB and ORC) are used to select the different port options available both in input and in output mode. All I/O registers can be read or written to just as any other RAM location in Data space, so no extra RAM cells are needed for port data storage and manipulation. During MCU initialization, all I/O registers are cleared and the input mode with pullups and no interrupt generation is selected for all the pins, thus avoiding pin conflicts. Figure 18. I/O Port Block Diagram SIN CONTROLS RESET VDD DATA DIRECTION REGISTER VDD INPUT /OUTPUT DATA REGISTER SHIFT REGISTER OPTION REGISTER SOUT TO INTER RUPT TO ADC 32/70 494 ST62T65B/E65B ST62T65B/E65B I/O PORTS (Cont'd) 4.1.1 Operating Modes Each pin may be individually programmed as input or output with various configurations (except for PB0 on devices with the EXTERNAL STOP MODE CONTROL option). This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and Option registers (OR). Table 11 illustrates the various port configurations which can be selected by user software. 4.1.1.1 Input Options Pull-up, High Impedance Option. All input lines can be individually programmed with or without an internal pull-up by programming the OR and DR registers accordingly. If the pull-up option is not selected, the input pin will be in the high-impedance state. 4.1.1.2 Interrupt Options All input lines can be individually connected by software to the interrupt system by programming the OR and DR registers accordingly. The pins of Port A and B are AND-connected to the interrupt associated with Vector #1. The pins of Port care AND-connected to the interrupt associated with Vector #2. The interrupt trigger modes (falling edge, rising edge and low level) can be selected by software for each port by programming the IOR register accordingly. 4.1.1.3 Analog Input Options The seven pins, PA0-PA5, PC0-PC4, can be configured as analog inputs by programming the OR and DR registers accordingly. These analog inputs are connected to the on-chip 8-bit Analog to Digital Converter. ONLY ONE pin should be programmed as an analog input at any time, since by selecting more than one input simultaneously their pins will be effectively shorted. 4.1.2 I/O Port Option Registers ORA/B/C (CCh PA, CDh PB, CEh PC) Read/Write 7 Px7 0 Px6 Px5 Px4 Px3 Px2 Px1 Px0 Bit 7-0 = Px7 - Px0: Port A, B and C Option Register bits. 4.1.3 I/O Port Data Direction Registers DDRA/B/C (C4h PA, C5h PB, C6h PC) Read/Write 7 Px7 0 Px6 Px5 Px4 Px3 Px2 Px1 Px0 Bit 7-0 = Px7 - Px0: Port A, B and C Data Direction Registers bits. 4.1.4 I/O Port Data Registers DRA/B/C (C0h PA, C1h PB, C2h PC) Read/Write 7 Px7 0 Px6 Px5 Px4 Px3 Px2 Px1 Px0 Bit 7-0 = Px7 - Px0: Port A, B and C Data Registers bits. 4.1.5 Timer 1 Alternate function Option When bit TOUT of register TSCR1 is low, pin PC1/Timer 1 is configured through the port registers as any standard pin of Port B. It is in addition connected to the Timer 1 input for Gated and Event counter modes. When bit TOUT of register TSCR1 is high, pin PC1/Timer 1 is forced as Timer 1 output, independently of the port registers configuration. Table 11. I/O Port Option Selection DDR 0 0 0 OR 0 0 1 DR 0 1 0 0 1 1 1 1 1 0 0 1 X X X Mode Input Input Input Input Input Output Output Output Option With pull-up, no interrupt (Reset state) No pull-up, no interrupt With pull-up and with interrupt No pull-up, no interrupt (PB0-PB7) Analog input (PA0-PA3, PC0-PC4) 20mA sink open-drain output (PB0-PB7) Standard open-drain output (PA0-PA7, PC0-PC4) 20mA sink push-pull output (PB0-PB7) Note: X = Don't care 33/70 495 ST62T65B/E65B ST62T65B/E65B I/O PORTS (Cont'd) 4.1.6 AR Timer Alternate function Option When bit PWMOE of register ARMC is low, pin ARTIMout/PB7 is configured as any standard pin of port B through the port registers. When PWMOE is high, ARTIMout/PB7 is the PWM output, independently of the port registers configuration. ARTIMin/PB6 is connected to the AR Timer input. It is configured through the port registers as any standard pin of port B. To use ARTIMin/PB6 as AR Timer input, it must be configured as input through DDRB. 4.1.7 SPI Alternate function Option PC2/PC4 are used as standard I/O as long as bit SPCLK of the SPI Mode Register is kept low.When PC2/Sin is configured as input, it is automatically connected to the SPI shift register input, independent of the state at SPCLK. PC3/SOUT is configured as SPI push-pull output by setting bit 0 of the Miscellaneous Register (address DDh), regardless of the state of Port C registers. PC4/SCK is configured as push-pull output clock (master mode) by programming it as push-pull output through DDRC register and by setting bit SPCLK of the SPI Mode Register. PC4/SCK is configured as input clock (slave mode) by programming it as input through DDRC register and by clearing bit SPCLK of the SPI Mode Register. With this configuration, PC4 can simultaneously be used as an input. 4.1.8 Safe I/O State Switching Sequence Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recommended safe transitions are illustrated in Figure 19. All other transitions are potentially risky and should be avoided when changing the I/O operat- ing mode, as it is most likely that undesirable sideeffects will be experienced, such as spurious interrupt generation or two pins shorted together by the analog multiplexer. Single bit instructions (SET, RES, INC and DEC) should be used with great caution on Ports A, B and C Data registers, since these instructions make an implicit read and write back of the entire register. In port input mode, however, the data register reads from the input pins directly, and not from the data register latches. Since data register information in input mode is used to set the characteristics of the input pin (interrupt, pull-up, analog input), these may be unintentionally reprogrammed depending on the state of the input pins. As a general rule, it is better to limit the use of single bit instructions on data registers to when the whole (8-bit) port is in output mode. In the case of inputs or of mixed inputs and outputs, it is advisable to keep a copy of the data register in RAM. Single bit instructions may then be used on the RAM copy, after which the whole copy register can be written to the port data register: SET bit, datacopy LD a, datacopy LD DRA, a Care must also be taken to not use INC or DEC instructions on a port register when the 8 bits are not available on the devices. The WAIT and STOP instructions allow the ST62xx to be used in situations where low power consumption is needed. The lowest power consumption is achieved by configuring I/Os in input mode with well-defined logic levels. The user must take care not to switch outputs with heavy loads during the conversion of one of the analog inputs in order to avoid any disturbance to the conversion. Figure 19. Diagram showing Safe I/O State Transitions Interrupt pull-up 010* 011 Input Analog Input pull-up (Reset state) 000 001 Input Output Open Drain 100 101 Output Open Drain Output Push-pull 110 111 Output Push-pull Note *. xxx = DDR, OR, DR Bits respectively 34/70 496 ST62T65B/E65B ST62T65B/E65B I/O PORTS (Cont'd) Table 12. I/O Port Option Selections MODE AVAILABLE ON(1) SCHEMATIC PA0-PA7 Input PB0-PB5, PB6-PB7 Data in PC0-PC4 Interrupt Input with pull up PA0-PA7 PB0-PB5, PB6-PB7 Data in PC0-PC4 Interrupt Input with pull up with interrupt PA0-PA7 PB0-PB5, PB6-PB7 Data in PC0-PC4 Interrupt Analog Input PA0-PA7 PC0-PC4 Open drain output PA0-PA7 5mA ADC PC0-PC4 Data out Open drain output PB0-PB5, PB6-PB7 20mA Push-pull output PA0-PA7 5mA PC0-PC4 Data out Push-pull output PB0-PB5, PB6-PB7 20mA Note 1. Provided the correct configuration has been selected. 35/70 497 ST62T65B/E65B ST62T65B/E65B I/O PORTS (Cont'd) Figure 20. Peripheral Interface Configuration of SPI, Timer 1 and AR Timer VDD PP/OD PC3/Sout MUX OUT 1 0 DR b0 MISC. REGISTER OR IN DR PC2/Sin SPI CLOCK IN PC4/SCK MUX CLOCK OUT 1 0 DR SPCLK MOD REGISTER OR IN OR TOUT PC1/TIM1 TIMER 1 OUT 1 MUX 0 DR ARTIMin DR ARTIMin AR TIMER OR PWMOE PP/OD ARTIMout MUX 1 0 ARTIMout DR VR0C1661 VR0C1661 36/70 498 ST62T65B/E65B ST62T65B/E65B 4.2 TIMER The prescaler input can be the internal frequency fINT divided by 12 or an external clock applied to the TIMER pin. The prescaler decrements on the rising edge. Depending on the division factor programmed by PS2, PS1 and PS0 bits in the TSCR (see Table 14), the clock input of the timer/counter register is multiplexed to different sources. For division factor 1, the clock input of the prescaler is also that of timer/counter; for factor 2, bit 0 of the prescaler register is connected to the clock input of TCR. This bit changes its state at half the frequency of the prescaler input clock. For factor 4, bit 1 of the PSC is connected to the clock input of TCR, and so forth. The prescaler initialize bit, PSI, in the TSCR register must be set to "1" to allow the prescaler (and hence the counter) to start. If it is cleared to "0", all the prescaler bits are set to "1" and the counter is inhibited from counting. The prescaler can be loaded with any value between 0 and 7Fh, if bit PSI is set to "1". The prescaler tap is selected by means of the PS2/PS1/PS0 bits in the control register. The MCU features an on-chip Timer peripheral, consisting of an 8-bit counter with a 7-bit programmable prescaler, giving a maximum count of 215. The peripheral may be configured in three different operating modes. Figure 21 shows the Timer Block Diagram. The external TIMER pin is available to the user. The content of the 8-bit counter can be read/written in the Timer/Counter register, TCR, which can be addressed in Data space as a RAM location at address 0D3h. The state of the 7-bit prescaler can be read in the PSC register at address 0D2h. The control logic device is managed in the TSCR register as described in the following paragraphs. The 8-bit counter is decrement by the output (rising edge) coming from the 7-bit prescaler and can be loaded and read under program control. When it decrements to zero then the TMZ (Timer Zero) bit in the TSCR is set to "1". If the ETI (Enable Timer Interrupt) bit in the TSCR is also set to "1", an interrupt request, associated with interrupt vector #3, is generated. The Timer interrupt can be used to exit the MCU from WAIT mode. Figure 22 illustrates the Timer's working principle. Figure 21. Timer Block Diagram . DATA BUS 8 8 6 5 4 3 2 1 0 PSC 8 8-BIT COUNTER SELECT 1 OF 8 8 b7 b6 b5 b4 b3 b2 b1 b0 STATUS/CONTROL REGISTER TMZ ETI TOUT DOUT PSI PS2 PS1 PS0 / 3 TIMER INTERRUPT LINE SYNCHRONIZATION LOGIC fINT LATCH : -12 VA00009 VA00009 . 37/70 499 ST62T65B/E65B ST62T65B/E65B TIMER (Cont'd) 4.2.1 Timer Operating Modes There are three operating modes, which are selected by the TOUT and DOUT bits (see TSCR register). These three modes correspond to the two clocks which can be connected to the 7-bit prescaler (fINT ÷ 12 or TIMER pin signal), and to the output mode. 4.2.2 Gated Mode The user can select the desired prescaler division ratio through the PS2, PS1, PS0 bits. When the TCR count reaches 0, it sets the TMZ bit in the TSCR. The TMZ bit can be tested under program control to perform a timer function whenever it goes high. The low-to-high TMZ bit transition is used to latch the DOUT bit of the TSCR and transfer it to the TIMER pin. This operating mode allows external signal generation on the TIMER pin. (TOUT = "0", DOUT = "1") Table 13. Timer Operating Modes TOUT 0 0 1 1 In this mode the prescaler is decremented by the Timer clock input (fINT ÷ 12), but ONLY when the signal on the TIMER pin is held high (allowing pulse width measurement). This mode is selected by clearing the TOUT bit in the TSCR register to "0" (i.e. as input) and setting the DOUT bit to "1". 4.2.3 Clock Input Mode DOUT 0 1 0 1 Timer Pin Input Input Output Output Timer Function Event Counter Gated Input Output "0" Output "1" (TOUT = "0", DOUT = "0") 4.2.5 Timer Interrupt In this mode, the TIMER pin is an input and the prescaler is decremented on the rising edge. 4.2.4 Output Mode When the counter register decrements to zero with the ETI (Enable Timer Interrupt) bit set to one, an interrupt request associated with Interrupt Vector #3 is generated. When the counter decrements to zero, the TMZ bit in the TSCR register is set to one. (TOUT = "1", DOUT = data out) The TIMER pin is connected to the DOUT latch, hence the Timer prescaler is clocked by the prescaler clock input (fINT ÷ 12). Figure 22. Timer Working Principle 7-BIT PRESCALER BIT0 CLOCK 0 BIT1 1 BIT0 BIT2 2 BIT1 BIT3 BIT4 4 3 8-1 MULTIPLEXER BIT2 BIT3 BIT4 BIT5 5 BIT6 7 6 PS0 PS1 PS2 BIT5 BIT6 BIT7 8-BIT COUNTER VA00186 VA00186 38/70 500 ST62T65B/E65B ST62T65B/E65B TIMER (Cont'd) 4.2.6 Application Notes The user can select the presence of an on-chip pull-up on the TIMER pin as a ROM mask option (see Option List at the end of the Datasheet). When low, this bit selects the input mode for the TIMER pin. When high the output mode is selected. Bit 4 = DOUT: Data Output TMZ is set when the counter reaches zero; however, it may also be set by writing 00h in the TCR register or by setting bit 7 of the TSCR register. The TMZ bit must be cleared by user software when servicing the timer interrupt to avoid undesired interrupts when leaving the interrupt service routine. After reset, the 8-bit counter register is loaded with 0FFh, while the 7-bit prescaler is loaded with 07Fh, and the TSCR register is cleared. This means that the Timer is stopped (PSI="0") and the timer interrupt is disabled. Data sent to the timer output when TMZ is set high (output mode only). Input mode selection (input mode only). If the Timer is programmed in output mode, the DOUT bit is transferred to the TIMER pin when TMZ is set to one (by software or due to counter decrement). When TMZ is high, the latch is transparent and DOUT is copied to the timer pin. When TMZ goes low, DOUT is latched. Bit 2, 1, 0 = PS2, PS1, PS0: Prescaler Mux. Select. These bits select the division ratio of the prescaler register. Bit 3 = PSI: Prescaler Initialize Bit Used to initialize the prescaler and inhibit its counting. When PSI="0" the prescaler is set to 7Fh and the counter is inhibited. When PSI="1" the prescaler is enabled to count downwards. As long as PSI="0" both counter and prescaler are not running. Table 14. Prescaler Division Factors PS2 0 0 0 0 1 1 1 1 A write to the TCR register will predominate over the 8-bit counter decrement to 00h function, i.e. if a write and a TCR register decrement to 00h occur simultaneously, the write will take precedence, and the TMZ bit is not set until the 8-bit counter reaches 00h again. The values of the TCR and the PSC registers can be read accurately at any time . 4.2.7 Timer Registers PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 Divided by 1 2 4 8 16 32 64 128 Timer Status Control Register (TSCR) Address: 0D4h - Read/Write Timer Counter Register TCR 7 TMZ 0 ETI TOUT DOUT PSI PS2 PS1 PS0 Bit 7 = TMZ: Timer Zero bit A low-to-high transition indicates that the timer count register has decrement to zero. This bit must be cleared by user software before starting a new count. Bit 6 = ETI: Enable Timer Interrupt When set, enables the timer interrupt request (vector #3). If ETI=0 the timer interrupt is disabled. If ETI=1 and TMZ=1 an interrupt request is generated. Bit 5 = TOUT: Timers Output Control Address: 0D3h - Read/Write 7 D7 0 D6 D5 D4 D3 D2 D1 D0 Bit 7-0 = D7-D0: Counter Bits. Prescaler Register PSC Address: 0D2h - Read/Write 7 D7 0 D6 D5 D4 D3 D2 D1 D0 Bit 7 = D7: Always read as "0". Bit 6-0 = D6-D0: Prescaler Bits. 39/70 501 ST62T65B/E65B ST62T65B/E65B 4.3 AUTO-RELOAD TIMER The Auto-Reload Timer (AR Timer) on-chip peripheral consists of an 8-bit timer/counter with compare and capture/reload capabilities and of a 7-bit prescaler with a clock multiplexer, enabling the clock input to be selected as fINT, fINT/3 or an external clock source. A Mode Control Register, ARMC, two Status Control Registers, ARSC0 and ARSC1, an output pin, ARTIMout, and an input pin, ARTIMin, allow the Auto-Reload Timer to be used in 4 modes: ­ Auto-reload (PWM generation), ­ Output compare and reload on external event (PLL), ­ Input capture and output compare for time measurement. ­ Input capture and output compare for period measurement. The AR Timer can be used to wake the MCU from WAIT mode either with an internal or with an external clock. It also can be used to wake the MCU from STOP mode, if used with an external clock signal connected to the ARTIMin pin. A Load register allows the program to read and write the counter on the fly. 4.3.1 AR Timer Description The AR COUNTER is an 8-bit up-counter incremented on the input clock's rising edge. The counter is loaded from the ReLoad/Capture Register, ARRC, for auto-reload or capture operations, as well as for initialization. Direct access to the AR counter is not possible; however, by reading or writing the ARLR load register, it is possible to read or write the counter's contents on the fly. The AR Timer's input clock can be either the internal clock (from the Oscillator Divider), the internal clock divided by 3, or the clock signal connected to the ARTIMin pin. Selection between these clock sources is effected by suitably programming bits CC0-CC1 of the ARSC1 register. The output of the AR Multiplexer feeds the 7-bit programmable AR Prescaler, ARPSC, which selects one of the 8 available taps of the prescaler, as defined by PSC0-PSC2 in the AR Mode Control Register. Thus the division factor of the prescaler can be set to 2n (where n = 0, 1,.7). The clock input to the AR counter is enabled by the TEN (Timer Enable) bit in the ARMC register. When TEN is reset, the AR counter is stopped and 40/70 502 the prescaler and counter contents are frozen. When TEN is set, the AR counter runs at the rate of the selected clock source. The counter is cleared on system reset. The AR counter may also be initialized by writing to the ARLR load register, which also causes an immediate copy of the valu