ST626X-DBE MB097 MB174 CLZ80 ST626X-EMU ST626X ST629X ST620X/1X/2X ST625X/ - Datasheet Archive

 

REAL TIME EMULATION DEVELOPMENT TOOLS FOR ST620x/1x/2x/5x/6x MCUs HARDWARE FEATURES s Supports ST62 and ST63 family s Real time

 

ST626x-EMU2 REAL TIME EMULATION DEVELOPMENT TOOLS FOR ST620x/1x/2x/5x/6x MCUs HARDWARE FEATURES s Supports ST62 and ST63 family s Real time emulation s 32 KBytes of emulation memory s Breakpoint on a single address or on an address area s Break events can be defined on Program Space, Data space mixed with up to 4 external signals s 2 full programmable output for synchronisation s Read/Write registers on the fly (without wait state) s Selective trace in Range or Start/Stop s Break on Stack Overflow s 1K of real trace memory s Tracing of up to 32 bits including 4 external signals SOFTWARE FEATURES s Symbolic debugger at source level s On-line assembler/disassembler s Log files capable of storing any displayed screen s Command files able to execute a set of debugger commands February 1998 This is advance information from STMicroelectronics. Details are subject to change without notice. 1/38 5 Table of Contents ST626x-EMU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 DELIVERY CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 ST6 HDS2 NEW MAINFRAME EMULATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 MAIN BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 ST6 HDS2 MAIN BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2.1 External output: OUT1 and OUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Data acquisition signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 LEDs RUN, STOP, WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 INSTALLING THE PROBE: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 7 8 2.4 INSTALLING AN ST6 EMU2 DEVELOPMENT TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 INSTALLING A ST626X-DBE ST626X-DBE DEDICATION BOARD IN AN ST6 HDS2 . . . . . . . . . . . . . . . 8 2.6 COMPONENTS LAYOUT OF ST6 MAIN BOARD (MB097 MB097) . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 COMPONENTS LAYOUT OF ST6 MAIN BOARD (MB174 MB174) . . . . . . . . . . . . . . . . . . . . . . . 10 3 ST6 MAINFRAME EMULATOR (FIRST GENERATION) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 MOTHER BOARD (CLZ80 CLZ80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 REAL TIME BOARD (GPFM/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 INTERFACE BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 ST626X-EMU ST626X-EMU DEVELOPMENT TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 INSTALLING ST626X-DBE ST626X-DBE DEDICATION BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 INSTALLING THE PROBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 DEDICATION BOARD (DBE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 VOLTAGE FUNCTIONING RANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 JUMPER DESCRIPTION ON DEDICATION BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.1 Choosing the emulated device: W7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Mask option on Port B: W3 and W4 for ST626X ST626X and ST629X ST629X . . . . . . . . . . . . . . . . 4.2.3 Hardware WATCHDOG selection: W1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 MIXT option: Wake UP by NMI in STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.5 Clock Source Selection: W2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.6 Reset delay duration: W5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 EMULATED PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 Timer A, Timer 2, Watchdog . . . . . . . . . . 4.3.4 Analog to Digital Converter . . . . . . . . . . . 4.3.5 Serial Peripheral Interface (SPI) . . . . . . . 4.3.6 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.8 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.9 Low Voltage Inhibit, Pin VCC (LVI) . . . . . 4.3.10 NMI/CKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2/38 6 15 16 16 16 17 17 18 18 18 18 18 18 19 19 20 20 20 Table of Contents 5 TROUBLESHOOTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 - AT POWER UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 DURING EMULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 DISCREPANCIES BETWEEN EMULATOR AND ROM OR EPROM DEVICE . . . . . . . . . 21 5.4 AVOID THE MOST FREQUENT PROBLEMS WHEN PROGRAMMING ST6 MICROS! . 22 5.4.1 Execution of Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 Execution of WAIT and STOP instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ANNEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 COMPONENTS LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 22 23 23 6.2 ST626X-DBE ST626X-DBE SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 PROBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3/38 7 ST626x-EMU2 - DELIVERY CHECK 1 DELIVERY CHECK This development tool is able to emulate all components belonging to the ST620X/1X/2X ST620X/1X/2X, ST625X/ ST625X/ 6X and to ST629X ST629X family. The dedication board is common for emulating the three families.Tthe choice of emulated ROM Device is made by properly setting the configuration on the dedication board, and connecting the appropriate PROBE on the appropriate connectors. The development tool is delivered with: ­ the ST6 mainframe emulator or the new ST6 HDS2 emulator ­ a 5 Volts power supply is added with the new ST6 HDS2 emulator ­ 2 flat cables for connecting one of the probes to the dedication board To emulate ST626X/9X ST626X/9X families: ­ a 28 pin DIL emulation probe for ST625X/6X ST625X/6X and ST629X ST629X (Ref. DB051 DB051 with DIL28 DIL28 footprint). ­ a 20 pin DIL emulation probe for ST625X/6X ST625X/6X and ST629X ST629X (Ref. DB051 DB051 with DIL20 DIL20 footprint). To emulate ST620X/1X ST620X/1X /2X families: 4/38 8 ­ a 28 pin DIL emulation probe for ST620X/1X/2X ST620X/1X/2X (Ref. DB210 DB210 with DIL28 DIL28 footprint). ­ a 20 pin DIL emulation probe for ST620/1X/2X ST620/1X/2X (Ref. DB210 DB210 with DIL20 DIL20 footprint). ­ a 16 pin DIL emulation probe for ST620X/1X/2X ST620X/1X/2X (Ref. DB210 DB210 with DIL16 DIL16 footprint). Finally, a DIL footprint to SO footprint adapter is also included in the package: ­ DB090 DB090: a 28 pin DIL to 28 pin SO adapter ­ DB093/20 DB093/20: a 20 pin DIL to 20 pin SO adapter ­ DB093/1 DB093/1: a16 pin DIL to 16 pin SO adapter Instructions for use - Warning This development tool conforms with the EN55022 EN55022 emissions standard for ITE, and with generic 50082-1 immunity standards. Then, it complies with the 89/336/EEC 89/336/EEC directive. The product is a A Class apparatus. In a residential environment this device may cause radioelectrical disturbance which may require that the user adopts appropriate precautions. ST626x-EMU2 - ST6 HDS2 NEW MAINFRAME EMULATOR 2 ST6 HDS2 NEW MAINFRAME EMULATOR The new ST6 HDS2 mainframe has been designed to replace the old one. The main modifications are: ­ communication transfer rate: it is now much faster thanks to the use of parallel port. ­ dimension and weight: the old 3 boards, basic part of the system, have been redesigned in one board. ­ the cost of the overall system has been well reduced In the second version of ST6 HDS2, (metal box with MB174 MB174 main Board) modified for EMC conformity, new features have been introduced: ­ Read/Write registers on the fly during execution of program without any wait state. ­ Selective record of bus in logical analyseur in Range or Start/Stop mode. ­ Output OUT1 and OUT2 for synchronisation of an external equipment, programmable in the same way as Selective trace, in Range or Start/ Stop mode. ­ Stack overflow: a break is automatically generated (by default) in case of stack overflow. ­ Break execution: in this new version, the program stops before the execution of the fetch. These new mainframes consist of a basic part, common to all ST6 devices, and one ST62 or ST63 sub family dedicated board depending on the specific device to emulate. This new emulator is fully compatible with existing dedicated boards, excepting ST638X ST638X and ST631XX ST631XX which have been designed in 2 boards. Only the dedicated board (DBE) has to be changed to emulate a new device within the ST62/ ST62/ ST63 sub families. The use of parallel port allows a very fast communication transfer rate. The symbolic debugger, software part of the real time emulation tool, can be run on a PC, and is common to all ST62 and ST63 devices. The debugger uses a windowed menu driven interface, and enables the user to set the configuration of the emulator. Figure 1. Hardware Development System Emulator HARDWARE DEVELOPMENT SYSTEM EMULATOR (HDS2) Parallel Port connection Dedication Board Power OUT-1 OUT-2 Stop Wait Run 4 3 2 1 Triggers ST6 HDS2 EMULATOR (.EMU2) ST6 probe 5/38 9 ST626x-EMU2 - ST6 HDS2 NEW MAINFRAME EMULATOR 2.1 MAIN BOARD The Main board controls the emulator thanks to a ST9 central processing unit which performs commands coming from host computer through the parallel line. The board contains, all emulation resources, the core of the ST6, Program ROM emulation, break point, trace memory, automaton and all necessary logic for a real time emulation. Two connectors, J1 and J2, are used to exchange signals with the interface board. The amount of program memory in the main board is factory set at 32k, in fact the size of the memory depends on the dedication board, which contains the Program Rom Pagination Register (PRPR) if it exists (no PRPR for memory size lower than 4k). No configuration jumpers are required. 2.2 ST6 HDS2 MAIN BOARD On the rear panel there is: ­ a power plug to connect power: 5 Volts 3 Amp min. (The delivered power is 100 volts to 240 volts input and 5 Amp output). ­ a power switch. ­ a parallel connector for an IBM PC(TM) compatible. On front panel: ­ a led "POWER ON" signal. ­ OUT 1 and OUT 2 signals which can be used for synchronizing an external equipment. ­ 3 leds indicating when the ST6 core is in "STOP", "WAIT" or "RUN" mode. ­ a 16 pin connector for data acquisition signals. The explanation of these signals is done in the debugger manual. 6/38 10 2.2.1 External output: OUT1 and OUT2 For debugging hardware it is very useful to have synchronization signals. The goal of the outputs 1 and 2 is to offer this feature to the user. They can be programmed differently whether the debugger used is the DOS debugger ST6NDB or the Source Level Debugger WGDB6, as explained in the two following paragraph. They are full programmable with WGDB6. Ouptput OUT1 and OUT2 under ST6NDB When using old DOS Version of debugger ST6NDB: This feature is programmable thanks to Hardware Breakpoint Menu. The breakpoint MENU allows to define breaking events. These events will generate an actual breakpoint only if break enable is ON. When break is off, these events are existing in the development tool. In the HDS2 emulator version up to 4.3, the signals OUT1 and OUT2 are connected to these internal breaking events. Therefore these signals can be used to synchronize an external device while running (breakpoint off). Ouptput OUT1 and OUT2 under WGDB6 When using WGDB6 new Version of debugger at source level under WindowsTM : This feature is full programmable thanks to Hardware Events/Trigger Menu. Output OUT1 and OUT2 can be programmed in two ways: ­ Events for synchronisation: it allows to the user to preset pulses synchronisation for an external equipment. The events can be defined by addresses or by range of addresses. ­ Events for Timing Measure: it allows to the user to measure time elapsed during a subroutine for example. In this case, output OUT2 is SET on a user defined address, and RESET on an other one, OUT1 is the ST6 clock cycle gated by OUT2. These 2 functioning modes are clearly displayed on screen. ST626x-EMU2 - ST6 HDS2 NEW MAINFRAME EMULATOR 2.2.2 Data acquisition signals In a same way as are recorded Buses, Flags, Bank registers in the trace memory, the ST6 HDS2 offers to the user the possibility to record 4 external signals. These signals must be connected on the pin of the Analyser probe connector on the front panel of the HDS2, as shown below. These inputs are CMOS compatible at 5 Volts. 2.2.3 LEDs RUN, STOP, WAIT Three leds have been added to indicate to the user the state of the core or of the development tool during emulation. When user's program is running (in real time), led RUN is on. When ST6 core is in WAIT mode, led WAIT is ON. VCC Caution: +5V EMU GND 1 AL3 AL2 AL1 AL0 When ST6 core is in STOP mode, both leds STOP and WAIT are ON. 7/38 11 ST626x-EMU2 - ST6 HDS2 NEW MAINFRAME EMULATOR 2.3 INSTALLING THE PROBE: Before installing the probe, the user must choose the device to be emulated: ST620x/1x/2x or ST625x/6x or ST629x Then, ­ Connect the 2 flat cables on the appropriate connectors, if the board is inside the main frame, unscrew the 2 screws on each side of the dedication board, and press outward on the release buttons to extract the board. ­ The connectors are J1 and J2 for ST625X/6X ST625X/6X and ST629X ST629X family (printed on board). ­ The connectors are J3 and J4 for ST620X/1X/2X ST620X/1X/2X family (printed on board). To prevent mistakes, a bump on connectors impose to set them right. Furthermore, we can verify that the pin 1 for each connector, which is clearly printed on both boards, is on the same side as the red line on the flat cables. Then connect the chosen probe on the opposite side of the flat cables, with respect to the pin 1 of each connector. Schematics of these probes are shown in annex. The ST620X/1X/2X ST620X/1X/2X probes emulate the oscillator function if the jumper on the probe is set on crystal. If set on OSCIN, a clock must be given on OSCIN input. To use this clock issued from probe, the dedication board must be set on external clock. 8/38 12 2.4 INSTALLING AN ST6 EMU2 DEVELOPMENT TOOL When receiving a whole development tool, the dedication board is delivered inside the mainframe. The user has just to: ­ connect the power supply to the mains(100 to 240 volts). ­ connect the output (5Volts) of power supply on the DIN connector of the rear panel ­ connect the parallel cable between the parallel connector and the host computer. 2.5 INSTALLING A ST626X-DBE ST626X-DBE DEDICATION BOARD IN AN ST6 HDS2 If there is already a dedication board in the development tool, the user has simply to: ­ unscrew the 2 screws on each side of the dedication board, and press outward on the release buttons to extract the board. Then insert the new dedication board in the guide rods and push it hardly in the backplane, and: ­ screw the 2 screws on each side of the dedication board. ST626x-EMU2 - ST6 HDS2 NEW MAINFRAME EMULATOR 2.6 COMPONENTS LAYOUT OF ST6 MAIN BOARD (MB097 MB097) A1 902 R V 9/38 13 ST626x-EMU2 - ST6 HDS2 NEW MAINFRAME EMULATOR 2.7 COMPONENTS LAYOUT OF ST6 MAIN BOARD (MB174 MB174) VR02091U VR02091U 10/38 14 ST626x-EMU2 - ST6 MAINFRAME EMULATOR (FIRST GENERATION) 3 ST6 MAINFRAME EMULATOR (FIRST GENERATION) The ST6 mainframe emulator contains positions for 5 boards: ­ Mother board (CLZ80 CLZ80) must be inserted on the first (bottom) position ­ Real time board (GPFM/3) must be on second position ­ interface N (DB014 DB014) must be inserted on third position ­ dedication board ST620X/1X/2X/5X/6X/9X-DBE ST620X/1X/2X/5X/6X/9X-DBE (MB064 MB064) inserted in one of the two top position On the rear panel there is: ­ a main-power selector to select 110 volts or 220 volts. ­ a power plug ­ a power switch On front panel: ­ the RS232 RS232 connector to link the emulator with an IBM PC ­ EXT-SIG connector that allows you to choose between 3 groups of 4 signals to be memorize on trace memory. These signals are independent from the probe data acquisition signals. The explanation of these signals is done in the debugger manual ­ Mother board reset push button ­ ST6 INT push-button 3.1 MOTHER BOARD (CLZ80 CLZ80) The mother board (CLZ80 CLZ80) controls the mainframe emulator and it is linked to an IBM PC through an RS232 RS232 line. On this board only 2 connectors are used: ­ J5 connected to the front panel RS232 RS232 25 pin connector ­ J4 connected to the front panel mother board reset push-button 3.2 REAL TIME BOARD (GPFM/3) Real time board (GPFM/3) contains the emulation resources: ­ ROM Program emulation, break point, trace memory. ­ Two connectors, J3 and J4, are used to exchange signals with the interface board. When emulating ST62XX ST62XX or ST63XX ST63XX, the interface board is an N-WELL interface board. The two connectors are used. For emulating components of other families, the interface board can be a P-WELL interface board: in this case only one connector is used, the jumpers of W2 must be plugged. JUMPERS SETTING for ST62XX ST62XX and ST63XX ST63XX emulation: W1: All jumpers must be removed. W2: One jumper only must be set to link pin 1 to pin 16. CONNECTORS: J3 and J4: Used to link this board with the N-WELL interface board. J5: Used to connect the data acquisition probe. 11/38 15 ST626x-EMU2 - ST6 MAINFRAME EMULATOR (FIRST GENERATION) 3.3 INTERFACE BOARD 3.4 ST626X-EMU ST626X-EMU DEVELOPMENT TOOL The interface board emulates the CPU-core. When receiving a whole development tool, the dedication board is delivered inside the mainframe, it is plugged in one of the two top position in the backplane. First of all, it is mandatory to verify the mainframe: ­ remove the 2 screws on the rear panel of the main frame ­ lift the lid on the side of the rear panel ­ pull the lid from the rear panel, it dissociates it from the front panel ­ remove the lid, pay attention to the wire for the ground connection Verify that all boards are correctly inserted in the backplane of the mainframe in the right order: ­ CLZ80 CLZ80 board must be inserted on the first (bottom) position ­ GPFM/3 board must be on second position ­ Interface N (DB014 DB014) must be inserted on third position ­ The two top positions are intended to receive one or a couple of dedication boards in order to emulate one family of component: in this case, only the ST626X-DBE ST626X-DBE board must be in one of the two top positions. JUMPERS SETTINGS: S1: ­ not used in emulation mode ­ allows the definition of the type of EPROM (27256/27128) used in stand-alone (without CLZ80 CLZ80 and GPFM/3 boards) mode S2, S3: size of emulation program ROM The position reference names depend on the version of the board. For S2 they can be identified as 0 and 1 or OLD and NEW on the board. For S3 it can be 0 and 1 or 4K and 8K. S2 S3 Size 0 or OLD 0 or 4K 4K 0 or OLD 1 or 8K 8K 1 or NEW 0 or 4K 16K 1 or NEW 1 or 8K 32K Comment normal setting not supported The purpose of this jumper is to allow the emulator to check the amount of emulation program ROM that is used. TEST/NO TEST: must be in NO TEST position CONNECTORS: J1 and J4 to link this board to GPFM/3 board. J2: receives signals from J1-EXT SIG. connector situated on the front panel of the ST6 emulator. J3: is connected to ST6-RESET, ST6-INT pushbuttons, STOP-LED and WAIT-LED situated on the front panel of the ST6 emulator. 12/38 16 ST626x-EMU2 - ST6 MAINFRAME EMULATOR (FIRST GENERATION) 3.5 INSTALLING ST626X-DBE ST626X-DBE DEDICATION BOARD When receiving only a dedication board, the user must install his dedication board as described below. Open the main frame by removing the lid: ­ remove the 2 screws on the rear panel of the main frame ­ lift the lid on the side of the rear panel ­ pull the lid from the rear panel, it dissociates it from the front panel ­ remove the lid, pay attention to the wire for the ground connection Then remove the dedication board or the two dedication board which are plugged in the two top position of the backplane, which was for emulating an other family of STMicroelectronics devices. After that, plug the new dedication board in one of the two top positions of the backplane. 3.6 INSTALLING THE PROBE Before installing the probe, the user must choose the device to be emulated, please refer to 4.2.1 chapter. Then, ­ Connect the 2 flat cables on the appropriate connectors. The connectors are J1 and J2 for ST625X/6X ST625X/6X and ST629X ST629X family (printed on board). The connectors are J3 and J4 for ST620X/1X/2X ST620X/1X/2X family (printed on board). To prevent mistakes, a bump on connectors impose to set them right. Furthermore, we can verify that the pin 1 for each connector, which is clearly printed on both boards, is on the same side as the red line on the flat cables. ­ Then, remove the 2 screws which are holding a small metal cover on the bottom of the development tool. ­ Stick the flat cables through this new opening. Then connect the chosen probe on the opposite side of the flat cables, with respect to the pin 1 of each connector. 13/38 17 ST626x-EMU2 - DEDICATION BOARD (DBE) 4 DEDICATION BOARD (DBE) This board contains the specific functions for ST620X/1X/2X ST620X/1X/2X, ST625X/6X ST625X/6X and ST629X ST629X emulation : ­ Oscillator ­ EEPROM (Byte mode and parallel mode) ­ RAM ­ Timer A ­ Timer 2 ­ Watchdog ­ Analog to Digital Converter ­ Serial Peripheral Interface ­ Analog to Digital Converter ­ Port A: 8 Bits ­ Port B: 8 Bits ­ Port C: 8 Bits (one part for ST625X/6X ST625X/6X, ST629X ST629X, the other for ST620X/1X/2X ST620X/1X/2X) ­ Low Voltage Inhibit ­ Pagination Registers A white dot indicates the position 1 for all jumpers and components on the board. Note for the VCC pin: When the input power pin VCC is connected, this input is used as a reference voltage by the emulator.(please refer to Figure 4.1 chapter) 14/38 18 No power is given or taken at this pin by the emulator. Notes on write-only registers: Several Data Space registers of the emulated ROM device are write-only, however, to offer more flexibility to the user, they are readable when commands such as "watching register" are used. 4.1 VOLTAGE FUNCTIONING RANGE This board has been designed to emulate the ROM device in the range of 3 to 6 Volts. When the input power VCC pin is connected, this input is used as a reference voltage by the emulator. This reference voltage is buffered thanks to an operational amplifier and an emitter follower for powering the output buffers, and for giving the high reference voltage to the ADC. Then all the outputs of the peripherals are fully compatible at CMOS level with an application which is powered in the range from 3 to 6 Volts. When this input is not connected, all buffers are powered with 5 volts. No power is given nor taken at this pin by the emulator. ST626x-EMU2 - DEDICATION BOARD (DBE) 4.2 JUMPER DESCRIPTION ON DEDICATION BOARD Jumpers on the board are used to select the amount of MEMORY, the emulated PERIPHERALS, and metal MASK OPTION of the ROM device. This chapter explains how to select these features. Note for ST620X/1X/2X ST620X/1X/2X: The difference between ST620X/1X ST620X/1X and ST622X ST622X is only about the size of ROM and A/D presence. As the Development Tool offers the maximum of ROM, the choice will be always a device of the ST622X ST622X family. 4.2.1 Choosing the emulated device: W7 This board has been designed to emulate 3 families of ST6 components: ST621X/2X ST621X/2X, ST626X ST626X and ST629X ST629X. The choices are different whether ADC and SIO are used, or Pin 23 or Pin 17 respectively is NMI or CKOUT, or with the amount of DATA space memory. To select this choice, only one jumper must be set on W7 in front of the name of the name of the device, clearly printed on the board. When a peripheral is not used, for example SIO for ST6292 ST6292, registers of this peripheral are at zero value, and they cannot be written. 4.2.1.1 Emulating ST621X/2X ST621X/2X family: J3 and J4 To emulate a ROM device of the ST621X/2X ST621X/2X family, a ST621X/2X ST621X/2X probe must be connected on J3 and J4 through the flat cables. There is one probe for emulating 28 pins ROM devices (DB031 DB031), and one probe for emulating 20 pins ROM devices(DB030 DB030). J3 of the dedication board must be connected on J1 of the probe. J4 of the dedication board must be connected on J2 of the probe. The number of the pins are clearly printed on both boards, and the red line on the flat cables must be on the same side of the 1 of the connectors. 4.2.1.2 Emulating ST626X ST626X or ST629X ST629X family: J1 and J2 To emulate a ROM device of the ST629X ST629X or ST626X ST626X family, the corresponding probe must be connected from J1 and J2 of the dedication board to respectively J1 and J2 of the probe, through the flat cables. The 28 pins probe emulate 28 pins ROM devices, the 20 pins probe emulate 20 pins ROM devices. The following table shows the difference between emulating ST626X ST626X or emulating ST629X ST629X. Emulated Device Jumper on W7 NMI/CKOUT ADC/SIO SPI ST6293/94 ST6293/94 ST6293/94 ST6293/94 CKOUT YES YES ST6291/92 ST6291/92 ST6291/92 ST6291/92 CKOUT NO NO ST6260/65 ST6260/65 ST6260/65 ST6260/65 NMI YES YES ST6263 ST6263* ST620/65 ST620/65 NMI YES NO ST6253 ST6253* ST6260/65 ST6260/65 NMI YES NO Data Space Memory 1 RAM Bank (0->3F) 2 EEPROM BANK (0->3F) EEPROM (0->2F) 1 RAM Bank (0->3F) 2 EEPROM BANK (0->3F) 1 RAM Bank (0->3F) 1 EEPROM BANK (0->3F) 1 RAM Bank (0->3F) 0 EEPROM BANK * Be careful not to try to emulate the SPI on ST6253/63 ST6253/63 and also the EEPROM on ST6253 ST6253 as those peripherals don't exist on these devices 15/38 19 ST626x-EMU2 - DEDICATION BOARD (DBE) 4.2.2 Mask option on Port B: W3 and W4 for ST626X ST626X and ST629X ST629X There is two option bits for the state of the bit port PB0, PB1, PB2, PB3 during RESET. This state can be input with pull-up or high impedance. The option byte 4 is for both PB0 and PB1, the other, option Byte 5, is for PB2 and PB3. OPT4: Option Byte 4 When the jumper is between 1 and 2 the option is 0: Pull-up during reset for PB0 and PB1. When the jumper is between 2 and 3 the option is 1: high impedance during reset for PB0 and PB1. OPT5: Option Byte 5 When a jumper is between 1 and 2 the option is 0: Pull-up during reset for PB2 and PB3. When a jumper is between 2 and 3 the option is 1: high impedance during reset for PB2 and PB3. The factory setting for these jumpers is: Pull-up during reset. When emulating ST621X ST621X or ST622X ST622X these jumpers are ignored. VR02091P VR02091P 16/38 20 4.2.3 Hardware WATCHDOG selection: W1 The jumper W1 permits to emulate the "hardware WATCHDOG" metal mask option of the ROM device. The watchdog can be activated in two ways in the ROM device: ­ The software Watchdog is activated by setting, by software, bit 0 of the watchdog register. ­ The other way is to be in "watchdog HARD", it means the watchdog is automatically armed after RESET (generated by watchdog or not). Jumper setting: 1-2: Watchdog is automatically activated by HARDWARE 2-3: Watchdog is only activated by SOFTWARE The jumper setting is clearly printed on board as shown in the following figure 3. Note: When activating watchdog, STOP instructions are automatically executed as WAIT instructions by the processor, see following chapter for special use of STOP mode. 4.2.4 MIXT option: Wake UP by NMI in STOP mode A special option is to effectively execute STOP mode when encountered, and to wake up from this STOP mode by using NMI pin. This feature is only available when ST6223/24 ST6223/24, or ST626X ST626X when MIXT option is selected. When this feature is selected, even if watchdog has been activated (Hard or soft), STOP instructions are effectively executed, when pin NMI is HIGH. If pin NMI goes low, or was low before executing STOP, STOP instructions are converted in WAIT instructions. Jumper setting W7: Two ways: ­ Select ST6223/24 ST6223/24 clearly printed on board ­ Put a jumper between pin 3 and 4 pin of W7 and select ST6260/65 ST6260/65 clearly printed on board. ST626x-EMU2 - DEDICATION BOARD (DBE) 4.2.5 Clock Source Selection: W2 The system CLOCK can be chosen between internal on board oscillator and pin OSCIN (or XTAL) input of the probe. This jumper setting is clearly printed on board, with INT for INTERNAL clock and EXT for EXTERNAL clock. Jumper setting: 1-2 In this case the external clock is selected: it means the Clock issued from the probe is selected. 2-3 The internal clock is selected. In this case the internal clock is made thanks to an oscillator with a quartz, this quartz XT1, can be exchanged if desired by the user. For delay of 4096, 8192 or 16384 the jumper must be in front of respectively 4, 8, or 16, clearly printed on the board. VR02091Q VR02091Q VR02091Q VR02091Q 4.2.6 Reset delay duration: W5 For as long as the reset pin is kept at the low level, the processor remains in the reset state. After the pin reset has been released, a counter provides a delay between the detection of the reset high level and the release of the MCU reset: a jumper on W5 permits to select the duration of this delay. The standard delay is 2048 oscillator cycles: the jumper must be in front of 2. Note for CLOCK "issued from the probe": If the user uses a probe made by STMicroelectronics, this probe is able to send a clock to the dedication board in two ways thanks to a jumper: ­ a clock made by the on board oscillator on the probe. ­ a clock directly issued from the application. In this case the signal on OSCIN must be at CMOS level. When oscillator is not used, it is mandatory to disable the oscillator by putting a jumper on "oscillator disable" (factory setting). WARNING on probe on board oscillator: Probe: The "open" schematic of this probe permits to the user to reconstruct on the probe, the same oscillator as on his own application. The probe is able to support a cristal or a resonator 3 pins with or without capacitor, it can be of course used also with an RC. PROBE: Installing the ferrite coil for EMC compatibility To be conform to the EMC directive, particularly in emission, the delivered ferrite coil must be placed as follow: 1) Place each part on each side of the flat cables 2) Place the metal clip to fix them together 17/38 21 ST626x-EMU2 - DEDICATION BOARD (DBE) 4.3 EMULATED PERIPHERALS 4.3.1 Oscillator For the ST621X/2X ST621X/2X it is a standard oscillator as described in the data sheet of the ROM device. For ST626X ST626X and ST629X ST629X, the four bits of the oscillator control write only register 0DCH are emulated, including RC oscillator frequency control (if Bit2=1 then Fosc is approximately divided by 100), but the pin XTAL and EXTAL are respectively input and output clock for the emulator, according to W2 selector. These two pin XTAL and EXTAL do not emulate an actual oscillator, on which it can be connected a crystal or an RC. 4.3.2 Mapping Program memory size is always valid up to 4 k Bytes (0FFFH) Data space memory size depends on the emulated device. The mapping of data space can be different in two ways: there is bank memory in the range 0 to 03FH or not. ­ No Memory Banks: case of ST6291 ST6291, ST6292 ST6292. ­ In this case, there is always EEPROM from 0 to 02FH, and nothing from 30 to 3F. ­ The Memory Bank Register (0E8H), is at 0 value, and it is not possible to write it. ­ Memory Banks exist: case of ST6293 ST6293, ST6294 ST6294, ST626X ST626X. ­ In this case the range from 0 to 03FH is fully used through the content of the Memory Bank Register located in 0E8H (write only). The meaning of each one of these bits is: Bit 0 if set selects the first EEPROM bank Bit 1 if set selects the second EEPROM bank Bit 4 if set selects the RAM bank. The others are not used and not existing. Care must be taken that only one of these three bit must be set at a time, for more details see Data Sheet of the corresponding ROM device. 4.3.3 Timer A, Timer 2, Watchdog Clock of these devices are voluntarily validated only during emulation, it provides to see the evolving values of them. Therefore pay attention that in NEXT mode the values of counters can be slightly different of a real time session because of setting ON and OFF emulation. 18/38 22 For using these peripherals, please, refer to data sheet of the corresponding ROM DEVICE. 4.3.4 Analog to Digital Converter This peripheral is available only when one component of ST620X/1X/2X ST620X/1X/2X, ST629X ST629X or ST625X/6X ST625X/6X family, which contains ADC, has been selected with W7 jumper. Except these devices, ADC registers are at zero value and are not able to be written. The ADC input can be connected at one of the 13 inputs, the 8 of port A and the 5 of port C, by properly programming the registers of these ports (one at a time). If more than one ADC input are selected, they will be short circuited each other's. The analog to Digital Converter converts the input value in about 50µS at 8 Mhz of Xtal clock. Clock conversion is always present, it means that a data conversion is always accomplished after writing a start conversion even if it is made in NEXT mode of emulation. It allows to the user to convert analog input step by step. Note on ADC voltage reference: The high voltage reference for the ADC is the applied voltage on the pin VCC internally buffered in the board. The low voltage reference is the GROUND. Then to have a conversion result of 0FFH, the voltage at the analog input must be equal to the voltage of the VCC pin. 4.3.5 Serial Peripheral Interface (SPI) This peripheral is available only when one of ST6293 ST6293, ST6294 ST6294 or ST626X ST626X has been selected with W7. For other devices, SPI registers are at zero value and are not able to be written. The Serial Peripheral Interface, when validated, is always active: it means clock and data do not depend whether on the system is in step by step mode or not. For using this peripheral, please, refer to Data Sheet of the corresponding ROM device. Note: to use this peripheral, do not forget to set bit 1 of LVI register. ST626x-EMU2 - DEDICATION BOARD (DBE) 4.3.6 Port A This port is always selected whatever is the emulated device, and if ADC is permitted (see 3.3.4 chapter), each input of this port can be an ADC input (one at a time). The functioning mode of each 8 input is selected by properly programming the three associated registers: Data Register (DRA), Data Direction Register (DDRA), and Option Register (ORA) as follow. For more details about this peripheral, please, refer to Data Sheet of the corresponding ROM Device. 4.3.7 Port B This port is always selected, the functioning mode of his 8 input is selected by properly programming the three associated registers: Data Register (DRB), Data Direction Register (DDRB), and Option Register (ORB) as follow. DDR 0 0 1 DR 1 0 Input with pullup, interrupt enabled I/O Mode 0 X 1 Input without pullup, interrupt disabled 0 1 0 Input with pullup, interrupt enabled 0 0 0 Input with pullup, interrupt disabled 1 X Push Pull Output 0 X Open Drain NMOS output I/O Mode Input without pullup, interrupt disabled DR 1 0 OPR OPR 1 DDR 0 0 0 Input with pullup, interrupt disabled 0 1 1 Analog Input 1 1 X Push Pull Output 1 0 X Open Drain NMOS output Beware of mixing input and output modes in the same port, in this case, do not use SET or RES instructions on Data Registers: When a port bit is in input mode, the data read is the state of the pin of the device (or the probe); when a port bit is in output mode the data read is the data register, so when using a read/modify/ write instruction, a bit port mode can be changed from input mode to analog input mode unintentionally! Beware of mixing input and output modes in the same port, in this case do not use SET or RES instructions on Data Registers: When a port bit is in input mode, the data read is the state of the pin of the device (or the probe); when a port bit is in output mode the data read is the data register, so when using a read/modify/ write instruction, a bit port mode can be changed from input mode to analog input mode unintentionally!. For more details about this peripheral, please, refer to Data Sheet of the corresponding ROM Device. 19/38 23 ST626x-EMU2 - DEDICATION BOARD (DBE) 4.3.8 Port C This port is always selected, and if ADC is permitted (see 3.3.4 chapter), each input of this 8 bit port can be an ADC input (one at a time). The functioning mode of each 8 input is selected by properly programming the three associated registers: Data Register (DRC), Data Direction Register (DDRC), and Option Register (ORC) as follow. Bit PC0 to PC4 are used for ST626X/9X ST626X/9X, PC4 to PC7 are used for ST621X ST621X emulation. DDR OPR DR I/O Mode 0 0 1 Input without pullup, interrupt disabled 0 1 0 Input with pullup, interrupt enabled 0 0 0 Input with pullup, interrupt disabled 0 1 1 Analog Input 1 1 X Push Pull Output 1 0 X Open Drain NMOS output Beware of mixing input and output modes in the same port, in this case, do not use SET or RES instructions on Data Registers: When a port bit is in input mode, the data read is the state of the pin of the device (or the probe); when a port bit is in output mode the data read is the data register, so when using a read/modify/ write instruction, a bit port mode can be changed 20/38 24 from input mode to analog input mode unintentionally! For more details about this peripheral, please, refer to Data Sheet of the corresponding ROM Device. 4.3.9 Low Voltage Inhibit, Pin VCC (LVI) Pin VCC on probe is an input for LVI system, and do not furnish any power to the application. A low Voltage inhibit system permanently watches Pin VCC on the probe. It generates a RESET when pin VCC goes under 2.5 Volts threshold and releases it when it goes over 3 Volts, at the same time bit 7 of LVI register (0DDH) is set to one. For more details about this peripheral, please, refer to Data Sheet of the corresponding ROM Device. 4.3.10 NMI/CKOUT The NMI/CKOUT PIN, pin 23 for 28 Pin package, pin 17 for the 20 pin package, can be either NMI entry or CKOUT output depending on the selected device (see 3.3.1 chapter). It is NMI input for ST626X ST626X family, and CKOUT for ST629X ST629X. When NMI is selected, the pin is the Non Maskable interrupt input for UC. When CKOUT is selected, the pin is an output clock whose the frequency is clock on XTAL divided by 2. CKOUT output is controlled by bit 3 of Oscillator Control Register (0DCH): If bit 3 is set: CKOUT is low If bit 3 is reset: CKOUT = Fosc/2 For more details about this peripheral, please, refer to Data Sheet of the ROM Device. ST626x-EMU2 - TROUBLESHOOTING 5 TROUBLESHOOTING 5.1 - AT POWER UP At the beginning of an emulation session, on screen of PC must appear the debugger message, with "WAIT" during software connection establishment. If a "TIMEOUT" message is encountered, there is a connection problem, which can come from one of these reasons: s when using ST6HDS2 ­ ST6 development Tool is not power ON ­ The parallel line is not well connected s or when using old main frame: ­ verify that the delivered cable is actually connected directly to the Main Frame. ­ and if necessary there is another cable which is either a "wire to wire" connection or a 25 to 9 pin adaptor. ­ The serial line is not connected to the right I/O port of the computer. 5.2 DURING EMULATION During emulation: Problem with program Counter In case of "Check Hardware Jumpering" or wrongly executing code in step mode: Most of the time, this problem occurs with HDS1 emulator or with HDS2 plastic BOX up to 4.3 version, it is coming from that the development tool is in RESET state, it can be caused by: ­ The application where probe is connected is not powered on, then the schmitt trigger on pin Reset is active and causes the RESET ­ The pin Reset of emulated device is at low level ­ A probe is connected, but is not powered either by an application or by a voltage on the VCC input. For properly emulating RESET please refer to the following chapter. During emulation: Reset emulation With ST6HDS2 new metal box, it is now possible to begin an emulation session even if application is off, it is required particularly in MONITOR or TV applications. With old ST6 HDS1 emulator, or with HDS2 plastic BOX up to 4.3 Version, if the application requires that software must be executed just after power ON, it is mandatory to proceed as follow: ­ not connect, or remove probe from application. ­ power ON emulator. ­ begin emulation session: load program. ­ then start execution of program in Real Time. ­ plug the probe in the application (which is off), at this time the ST6 emulator is in reset state, because Reset and VCC pins are at low level. ­ Power ON the application, then the execution of software will start. 5.3 DISCREPANCIES BETWEEN EMULATOR AND ROM OR EPROM DEVICE When some differences of behaviour are appearing between the emulator and the ROM device, in most cases, it comes from using read/modify/ write instructions on: ­ registers which are only writable. ­ registers in which some bits are writable, and some bits readable. For these registers, trouble are caused, because when reading, a random value is read by the CPU, after calculating the mask, this random value is written in the register, changing it unintentionally! The same problem can occur with registers, where some bits have a different function during writing or during reading. Example for Ports: When reading a bit port in input mode, the read value is the level of the pin. When reading a bit port in output, the read value is the value of the corresponding bit in the Data Register. The user has to check if each used register is correctly accessed. The principle ST6 registers, with which care must be taken, are listed below: ­ The EEPROM control registers ­ The control registers of SPIs ­ The Data registers of the 3 Ports A, B and C ­ Analog to Digital Converter Control Register ­ The Interrupt Option Register ­ The Program Rom Pagination Registers ­ The Data RAM/EEPROM Banking Register ­ The Data ROM window Register 21/38 25 ST626x-EMU2 - TROUBLESHOOTING 5.4 AVOID THE MOST FREQUENT PROBLEMS WHEN PROGRAMMING ST6 MICROS! 5.4.1 Execution of Interrupt If interrupt are not executed, in most cases, it comes from: ­ The core is not in normal mode: after RESET the core is in NMI mode, to enter the normal mode which let execute interrupt, the core must execute a RETI instruction. ­ The global enable interrupt bit has not been SET, or has been unintentionally cleared, then the IOR register must be checked. The default value to enable Interrupts is 010H. ­ The enable interrupt bit of the desired peripheral has not been SET, or has been unintentionally cleared. ­ The Interrupt Option Register is write only, and has been wrongly written by a read/modify/write instruction, only LDI is permitted. 22/38 26 5.4.2 Execution of WAIT and STOP instructions In WAIT mode, led WAIT is ON, in STOP mode the 2 led WAIT and STOP are ON (on the front panel of the emulator). If STOP or WAIT instructions are not exited, it comes from: ­ The core is not in normal mode: after RESET the core is in NMI mode, to enter the normal mode which let execute interrupt to exit from these states, the core must execute a RETI instruction. ST626x-EMU2 - ANNEX 6 ANNEX 6.1 COMPONENTS LAYOUT VR02091O VR02091O 23/38 27 ST626x-EMU2 - ANNEX 6.2 ST626X-DBE ST626X-DBE SCHEMATICS Figure 1. Main sheet VCC -12V -12V +12V TY9 A0 A2 A4 A6 TY7 TY9 INTFR INTFR WAIT +12V CYC01 CYC01 CYC03 CYC03 INT1 INT3 EXTRES WAIT CYC01 CYC01 INT1 INT3 EXTRES CYC05 CYC05 PININT0 P1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VME64 VME64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 A[0.7] TY2 A[0.7] TY2 CYC01 CYC01 1 TP1 CYC05 CYC05 CYCOI A1 A3 A5 A7 INTFLL READ INTFLL WRITE PRUN0 INT0 INT2 INT4 INTRES WEA12 WEA12 PRUN0 5 I READ R WRITE W ROMADR INT0 INT2 INT4 INTRES CLOCK CLOCK TP7 WEA12 WEA12 TP8 INTRES IR RUN WAIT WT BDIO STOP S RESSO STOP TP4 CK EXTINT RESSO TP3 TP5 ROMADRTP6 PRUN EXTINT CYC0I BDIO TP2 CLKSYST K STOP TP17 I CK/12 CK/12 VCE VCE VDDI VDDI GND TP9 TP10 TP11 TP12 TP13 CK/12 CK/12 TP14 TP15 TP16 GND VSS C7 47uF C2 47uF C1 470uF-EA C4 C3 47uF 47uF VCC VDD VCC TP18 RBB[0.3] RBB[0.3] J RBB[0.3] RBB0 RBB2 EXWR EXWR DRBB0 DRBB2 DRBB4 CLKSYST DRBB6 DRBB8 DD0 DD2 DD4 DD6 RAMPB0 RAMPB2 RAMPB4 RAMPB6 P2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VME64 VME64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 RBB1 RBB3 RESTO BIT4 ROMADR ROMADR DRBB1 DRBB[0.7] DRBB3 DRBB5 DRBB7 RAMPB1 RAMPB3 RAMPB5 RAMPB7 DRBB[0.7] 28 DD[0.7] DD[0.7] INTRES DD1 DD3 DD5 DD7 RAMPB[0.7] 24/38 RESTO BIT4 RAMPB[0.7] VR02091M VR02091M ST626x-EMU2 - ANNEX Figure 1. Main sheet (Cont'd) PORTA, Timer 1 File : PATIM1.SCH PLD1A[0.4] DD[0.7] WRITE READ TY9 CLOCK PLD1A[0.4] D[0.7] WRITE READ TY9 CLOCK NRESETI PRUN PULS TIM1IN TOUT TIMOUT NITTIM1 LATCH0 LATCH1 EXT[0.10] NRESETI PRUN PULS VDDI LATCH0 LATCH1 EXT[0.10] PRUN VCC PA[0.7] PA[0.7] PULS EXT5 VCE TIM1IN TOUT TIMOUT NITTIM1 A0 A1 A2 A3 A4 A5 A6 A7 PACAD[0.7] PACAD[0.7] PORTB, TIM2, RTC, IOR, CAD control File : PORTB1.SCH PLD1A[0.4] DD[0.7] WRITE READ TY9B CLOCK EOCADC NRESETI PRUN NITPB ITRTC NITTIM2 NADCRRR NITADC NSTARTADC PB[0.7] PBCAD[0.7] EXT[0.10] BIT4 INTFR INTFLL ADCCLOCK TEST PLD1A[0.4] D[0.7] WRITE READ TY9B CLOCK EOCADC NRESETI PRUN LATCH0 LATCH1 LATCH0 LATCH1 NITPB ITRTC NITTIM2 NADCRRR NITADC NSTARTADC PB[0.7] PBCAD[0.7] EXT[0.10] BIT4 INTFR INTFLL ADCCLOCK TEST DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 READ WRITE EXT1 PORTC, SI4, LVI PLD1A[0.4] LATCH0 LATCH1 PLD1A[0.4] DD[0.7] WRITE READ CLOCK LATCH0 LATCH1 NRESETI PRUN PLD1A[0.4] D[0.7] WRITE READ CLOCK LATCH0 LATCH1 NRESETI PRUN File : PCSI4.SCH TIMOUT TOUT ITSI4 TIM1IN J5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 MW2X30C MW2X30C EXT4 CLOCK EXT6 GND EXT2 EXT3 EXT8 EXT7 EXT10 EXT10 EXT9 EXT0 TIMOUT TOUT ITSI4 TIM1IN PC[0.7] PCCAD[0.7] PC[0.7] PCCAD[0.7] PROBE Connection EXT[0.10] RBB[0.3] EXT[0.10] RBB[0.3] PA[0.7] LVI LVI PB[0.7] PC[0.7] CONTROL, ADRESS DECODING, INTERFACE POWER File : CONTROL.SCH INT[0.4] CLOCK RESSO RESTO A[0.7] INT[0.4] CLOCK RESSO RESTO A[0.7] NITPB PRUN BDIO EXWR TY9B LVI VCKOUT ITSI4 NITTIM1 NITADC NITTIM2 ITRTC NITPB PRUN BDIO EXWR TY9B LVI VCKOUT ITSI4 NITTIM1 NITADC NITTIM2 ITRTC NRESETI RSTINT PLD1A[0.4] EXTAL XTAL NRESETAP EXTRES VCCAPP READ WRITE VCKOUT CKNMI OPTSER EXTAL XTAL CKNMI VSREF NRESETI RSTINT PLD1A[0.4] NRES CKNMI VSREF EXTRES VCCAPP READ WRITE VCKOUT CKNMI OPTSER BANK, Clock Generation, Reset, WATCHDOG, Pag. Register DD[0.7] WRITE READ NRESETI STOP WAIT TY9 PULS A[0.7] INTRES D[0.7] WRITE READ NRESETI OPTSER TY2 RSTINT INTRES OPTSER TY2 RSTINT CLOCK CLKSYST PRUN PRUN0 EXTINT CKNMI VCKOUT EXT[0.10] TY2B TY9B CLOCK CLKSYST PRUN PRUN0 EXTINT CKNMI VCKOUT EXT[0.10] TY2B TY9B RAMPB[0.7] DRBB[0.7] ROMADR OSCIN OSCOUT STOP WAIT TY9 PULS A[0.7] File : EEPRBNK.SCH RAMPB[0.7] DRBB[0.7] ROMADR XTAL EXTAL CKNMI VCKOUT EXT[0.8] Analog to Digital Converter DD[0.7] ADCCLOCK NADCRRR NSTARTADC NADCRRR NSTARTADC FILE: CAD.SCH PA[0.7] PACAD[0.7] PA[0.7] PACAD[0.7] PB[0.7] PBCAD[0.7] D[0.7] PB[0.7] PBCAD[0.7] PC[0.7] PCCAD[0.7] PC[0.7] PCCAD[0.7] ADCCLOCK NADCRRR NSTARTADC EOCADC VSREF EOCADC VSREF VR02091N VR02091N 25/38 29 26/38 30 TY9 PRUN D[0.7] VCE RP4 1 VCE 18 19 21 22 23 PAUP/CAD1 OUTPA1 VOUTPA1 INPA1 D1 PAUP/CAD2 OUTPA2 VOUTPA2 INPA2 D2 LATCH1 D0 12 13 14 15 17 PAUP/CAD0 OUTPA0 VOUTPA0 INPA0 NRESETI 10K-S10 10K-S10 4 5 6 7 8 9 10 11 10 9 8 7 6 5 4 3 2 PLD1A[0.4] LATCH1 OUTPA0 OUTPA1 OUTPA2 OUTPA3 OUTPA4 OUTPA5 OUTPA6 OUTPA7 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VOUTPA7 VOUTPA6 VOUTPA5 VOUTPA4 VOUTPA0 VOUTPA3 VOUTPA2 VOUTPA1 1 10K-S10 10K-S10 RP8 3 33 3 6 6 1 2 2 45 6 6 8 2 3 4 5 6 7 8 9 10 CK/12 CK/12 D 4 P OV I T A U ONY UT UP9 PPTA / AP4 C4 A A 4 D 4 P OV I A UON UT UP PPTA / AP3 C3 A A 3 D 3 D 3 3 3 44 4 44 4 8 9 01 2 34 5 22 2 2 2 2 3 3 45 6 7 8 9 0 1 D5 INPA5 VOUTPA5 OUTPA5 PAUP/CAD5 51 49 48 47 46 EPM5128 EPM5128 D6 INPA6 VOUTPA6 OUTPA6 PAUP/CAD6 57 56 55 53 52 D7 PLD1A4 LATCH0 INPA7 VOUTPA7 OUTPA7 PAUP/CAD7 IC10 TOUT TIMOUT 65 64 63 62 61 60 59 58 PAUP/CAD0 PAUP/CAD1 PAUP/CAD2 PAUP/CAD3 PAUP/CAD4 PAUP/CAD5 PAUP/CAD6 PAUP/CAD7 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCE I/O I/O I/O I/O I/O I/O I/O I/O TIM1IN 1 10K-S10 10K-S10 RP13 Input Input Input Input Input Input Input Input/CLK I/O I/O I/O I/O I/O I/O I/O I/O PRUN 2 3 4 5 6 7 8 9 10 PLD 1A0 PLD 1A1 PLD 1A2 PLD 1A3 D[0.7] WRITE READ NRESETI CLOCK PLD1A[0.4] PAUP/CAD0 PAUP/CAD7 PAUP/CAD1 PAUP/CAD2 PAUP/CAD6 PAUP/CAD5 PAUP/CAD3 PAUP/CAD4 LATCH0 LATCH1 LATCH0 INPA[0.7] OUTPA[0.7] VOUTPA[0.7] PUPPA[0.7] GND 1 11 3 4 7 8 13 14 17 18 1 11 3 4 7 8 13 14 17 18 OC CLK 374E IC54 D0 D1 D2 D3 D4 D5 D6 D7 OC CLK 374E IC49 D0 D1 D2 D3 D4 D5 D6 D7 RP18 10K-S10 10K-S10 GND Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 PA2 4 1 1 2 5 6 9 12 15 16 19 2 5 6 9 12 15 16 19 PACAD0 PACAD1 PACAD2 PACAD3 PACAD4 PACAD5 PACAD6 PACAD7 PUPPA0 PUPPA1 PUPPA2 PUPPA3 PUPPA4 PUPPA5 PUPPA6 PUPPA7 RS4B 3 2 2 3 RS5A EXT0 EXT1 1 2 3 4 56 7 8 90 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 W11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MW2X8C PORTA OPTION 470K R9 INPA[0.7] OUTPA[0.7] VOUTPA[0.7] PA[0.7] File : PA07.SCH PUPPA[0.7] PORT A 5 RS4C 5 RS5C 6 PACAD[0.7] 6 1K-4R8P RS4A 1 1K-4R8P RS5B 4 8 7 EXT[0.8] PA[0.7] RS4D 7 RS5D 8 LATCH0 LATCH1 PACAD[0.7] PULS NITTIM1 OUTPA0 OUTPA1 OUTPA2 OUTPA3 OUTPA4 OUTPA5 OUTPA6 OUTPA7 EXT[0.8] TOUT TIMOUT PA[0.7] ST626x-EMU2 - ANNEX Figure 2. Port A and Timer 1 VR02091J VR02091J 15 14 11 74HC4049I 74HC4049I IC25E IC25E OUTPA3 VOUTPA3 12 5 74HC4049I 74HC4049I PUPPA3 4 INPA3 INPA2 IC25B IC25B OUTPA2 VOUTPA2 74HC4049I 74HC4049I PUPPA2 INPA1 IC25F IC25F OUTPA1 VOUTPA1 PUPPA1 74HC4049I 74HC4049I OUTPA0 IC25A IC25A 3 INPA0 2 VOUTPA0 PUPPA0 5 1 3 VCE 11 6 8 IC42C IC42C 74HC126E 74HC126E 1 0 PUPPA[0.7] 2 1 11 13 6 3 8 11 74HC14E 74HC14E IC33E IC33E IC48C IC48C 74HC126E 74HC126E 1 0 74HC14E 74HC14E IC33B IC33B IC48B IC48B 74HC126E 74HC126E 4 74HC14E 74HC14E IC33F IC33F IC48D IC48D 74HC126E 74HC126E 1 3 74HC14E 74HC14E IC33A IC33A 10 9 4 12 5 3 IC48A IC48A 74HC126E 74HC126E 1 INPA[0.7] VOUTPA[0.7] OUTPA[0.7] 12 2 VCE IC42B IC42B 74HC126E 74HC126E 4 VCE IC42D IC42D 74HC126E 74HC126E 1 3 VCE IC42A IC42A 74HC126E 74HC126E 9 12 2 OUTPA[0.7] INPA[0.7] PUPPA[0.7] VOUTPA[0.7] 2 1 PA1 6 8 PA3 7 RS8D 100K-4R8P 100K-4R8P PA2 5 RS8C 100K-4R8P 100K-4R8P 4 3 RS8B 100K-4R8P 100K-4R8P PA0 RS8A 100K-4R8P 100K-4R8P 15 14 11 74HC4049I 74HC4049I IC24E IC24E OUTPA7 VOUTPA7 12 5 74HC4049I 74HC4049I PUPPA7 4 INPA7 INPA6 IC24B IC24B OUTPA6 VOUTPA6 74HC4049I 74HC4049I PUPPA6 INPA5 IC24F IC24F OUTPA5 VOUTPA5 PUPPA5 74HC4049I 74HC4049I OUTPA4 IC24A IC24A 3 INPA4 2 VOUTPA4 PUPPA4 5 9 12 2 3 11 6 8 IC41C IC41C 74HC126E 74HC126E 1 0 2 2 5 1 3 1 11 13 6 3 8 11 74HC14E 74HC14E IC32E IC32E IC53C IC53C 74HC126E 74HC126E 1 0 74HC14E 74HC14E IC32B IC32B IC53B IC53B 74HC126E 74HC126E 4 74HC14E 74HC14E IC32F IC32F IC53D IC53D 74HC126E 74HC126E 1 3 74HC14E 74HC14E IC32A IC32A IC53A IC53A 74HC126E 74HC126E 10 9 4 12 12 VCE IC41B IC41B 74HC126E 74HC126E 4 VCE IC41D IC41D 74HC126E 74HC126E 1 3 VCE IC41A IC41A 74HC126E 74HC126E 1 VCE PA[0.7] PA4 RS7A 100K-4R8P 100K-4R8P PA5 6 8 VR02091K VR02091K PA7 7 RS7D 100K-4R8P 100K-4R8P PA6 5 RS7C 100K-4R8P 100K-4R8P 4 3 RS7B 100K-4R8P 100K-4R8P 2 1 PA[0.7] ST626x-EMU2 - ANNEX Figure 3. Port A buffers 27/38 31 32 28/38 TY9B EOCADC PLD1A[0.4] PULLUP HZ W11 1 2 3 MW1X3C OPT5 W12 1 2 3 MW1X3C OPT4 PULLUP HZ CLOCK NRESETI D[0.7] PRUN READ WRITE LATCH0 LATCH1 RP13 10K-S10 10K-S10 12 13 14 15 16 17 RP14 10K-S10 10K-S10 25 26 27 28 29 30 31 32 NSTARTADC STARTRTC NITPB EOCADC PLD1A4 CLOCK2Hz D2 TS2 OUTPB2 PBUPCAD2 D3 TS3 PLD1A[0.4] 20 21 22 23 D1 TS1 OUTPB1 PBUPCAD1 INTEFLL NITADC GND 1 1 23456 7890 23456 7891 0 1 VCC D[0.7] I I I I I I I I / / / / / / / / OOOOOOOO I I I I I I / / / / / / OOOOOO 8 7777 7 0 9876 5 DT OP 7 SUB 7TU PP BC 7 A D 7 PPPP L LLL DDDD 1 111 AAAA 0 123 OP T T NE UBEYAX T US 9 DT P PT BC6 BC R 3 A R R D 3 GND 44 44 12 34 3 33333 3 45678 N B E E P OT D I I XXB US4 T TTTUT4 T354PP T354PP I CB A4 M D 2 4 444 4555 5 678 9012 3 I I I I NNNN PPPP UUUU TTTT I I I I I I / / / / / / OO OOOO I I I I NNNN PPPP UUUU TTTT / C L K I I I I I I I I / / / / / / / / OO OOOOO O W9 1 2 MW1X2C I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 88 2 143 1 1 1 09876 54 I I OOP OT D NNP P B US 0 P PT T UT 0 BB5 4 PP 1 0 CB A0 D 0 XT1 QZ 32.768 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O EXT2 IC8 12 11 INPB3 INPB2 D5 TS5 OUTPB5 PBUPCAD5 INPB7 INPB6 INPB5 INPB4 ITRTC INTEFR D6 TS6 OUTPB6 PBUPCAD6 EXT3 PRUN EPM5192 EPM5192 59 58 57 56 55 54 65 64 63 62 74 73 72 71 70 69 68 67 470K R6 PO PO 74HC4060 74HC4060 IC13 Q4 PI Q5 Q6 RST Q7 Q8 Q9 Q10 Q12 Q13 Q14 PBUPCAD[0.7] R7 100K 9 10 7 5 4 6 14 13 15 1 2 3 PBUPCAD[0.7] GND PBUPCAD0 PBUPCAD1 PBUPCAD2 PBUPCAD3 PBUPCAD4 PBUPCAD5 PBUPCAD6 PBUPCAD7 1 11 3 4 7 8 13 14 17 18 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 RP17 10K-S10 10K-S10 GND 2 5 6 9 12 15 16 19 INPB[0.7] OUTPB[0.7] VOUTPB[0.7] PUPPB[0.7] PORT B PBUPCAD[0.7] PUPPB0 PUPPB1 PUPPB2 PUPPB3 PUPPB4 PUPPB5 PUPPB6 PUPPB7 1 VCC VCE RS11A RS11A 2 3 TS6 TS7 TS4 TS5 TS0 TS1 TS2 TS3 RS11B RS11B 4 5 5 1 11 3 4 7 8 13 14 17 18 RS12A RS12A 1K-4R8P 2 RS12B RS12B 3 4 PB[0.7] File : PB07.SCH GND PBUPCAD0 PBUPCAD1 PBUPCAD2 PBUPCAD3 PBUPCAD4 PBUPCAD5 PBUPCAD6 PBUPCAD7 10K-S10 10K-S10 PORTB OPTION OPEN : OPEN DRAIN OPTION CLOSED : PUSH-PULL OPTION W10 1 2 1 3 4 5 6 7 8 9 1 10 11 12 13 14 15 16 MW2X8C 1 2 345 67890 INPB[0.7] OUTPB[0.7] TS[0.7] PUPPB[0.7] OC CLK 374E IC39 D0 D1 D2 D3 D4 D5 D6 D7 10K-S10 10K-S10 PULLUP on EPLD I/O : LOW = LOW , HIGH LEVEL = H Impedence RP2 VCE RP16 2 1 1 PBUPCAD7 2 OUTPB0 3 OUTPB7 PBUPCAD6 3 4 PBUPCAD5 4 OUTPB1 5 PBUPCAD4 5 OUTPB2 6 PBUPCAD3 6 OUTPB6 7 OUTPB5 PBUPCAD2 7 8 OUTPB3 PBUPCAD1 8 9 OUTPB4 PBUPCAD0 9 10 10 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 7 7 2 5 6 9 12 15 16 19 1 PBCAD0 PBCAD1 PBCAD2 PBCAD3 PBCAD4 PBCAD5 PBCAD6 PBCAD7 10K-S10 10K-S10 RP6 1K-4R8P RS11D RS11D 8 RS12D RS12D 8 VCE VR02091F VR02091F NADCRRR NITADC NSTARTADC NITPB BIT4 INTFR INTFLL NITTIM2 TEST EXT[0.8] OUTPB0 OUTPB1 OUTPB2 OUTPB3 OUTPB4 OUTPB5 OUTPB6 OUTPB7 ITRTC ADCCLOCK PB[0.7] PBCAD[0.7] PBCAD[0.7] EXT[0.8] RS11C RS11C 6 RS12C RS12C 6 PB[0.7] OC CLK 374E IC22 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 10 ST626x-EMU2 - ANNEX Figure 4. Port B and Timer 2 7 9 74HC4049I 74HC4049I IC24D IC24D OUTPB3 VOUTPB3 INPB3 10 7 74HC4049I 74HC4049I PUPPB3 INPB2 6 IC24C IC24C OUTPB2 VOUTPB2 9 2 5 9 12 74HC4049I 74HC4049I IC25D IC25D PUPPB2 INPB1 10 OUTPB1 VOUTPB1 74HC4049I 74HC4049I PUPPB1 INPB0 6 IC25C IC25C OUTPB0 VOUTPB0 PUPPB0 3 11 6 8 IC23C IC23C 74HC126E 74HC126E 1 0 2 5 6 9 6 8 12 VCE IC23B IC23B 74HC126E 74HC126E 4 VCE IC23D IC23D 74HC126E 74HC126E 1 3 VCE IC23A IC23A 74HC126E 74HC126E 1 VCE 3 5 11 9 6 8 5 8 9 74HC14E 74HC14E IC32D IC32D IC40C IC40C 74HC126E 74HC126E 1 0 74HC14E 74HC14E IC32C IC32C IC40B IC40B 74HC126E 74HC126E 4 74HC14E 74HC14E IC33D IC33D IC40D IC40D 74HC126E 74HC126E 1 3 74HC14E 74HC14E IC33C IC33C IC40A IC40A 74HC126E 74HC126E 1 INPB[0.7] VOUTPB[0.7] OUTPB[0.7] PUPPB[0.7] PB0 PB1 6 8 PB3 7 RS17D RS17D 100K-4R8P 100K-4R8P PB2 5 RS17C RS17C 100K-4R8P 100K-4R8P 4 3 RS17B RS17B 100K-4R8P 100K-4R8P 2 1 RS17A RS17A 100K-4R8P 100K-4R8P INPB[0.7] PUPPB[0.7] VOUTPB[0.7] OUTPB[0.7] 7 74HC4049I 74HC4049I 7 INPB7 10 74HC4049I 74HC4049I OUTPB7 IC16D IC16D VOUTPB7 9 74HC4049I 74HC4049I PUPPB7 INPB6 6 OUTPB6 IC16C IC16C VOUTPB6 PUPPB6 74HC4049I 74HC4049I OUTPB5 IC29D IC29D 9 INPB5 10 VOUTPB5 PUPPB5 INPB4 6 OUTPB4 IC29C IC29C VOUTPB4 PUPPB4 5 9 12 2 3 11 6 8 IC46C IC46C 74HC126E 74HC126E 1 0 2 6 5 9 6 8 12 VCE IC46B IC46B 74HC126E 74HC126E 4 VCE IC46D IC46D 74HC126E 74HC126E 1 3 VCE IC46A IC46A 74HC126E 74HC126E 1 VCE 3 5 11 9 6 8 5 8 9 74HC14E 74HC14E IC21D IC21D IC45C IC45C 74HC126E 74HC126E 1 0 74HC14E 74HC14E IC21C IC21C IC45B IC45B 74HC126E 74HC126E 4 74HC14E 74HC14E IC38D IC38D IC45D IC45D 74HC126E 74HC126E 1 3 74HC14E 74HC14E IC38C IC38C IC45A IC45A 74HC126E 74HC126E 1 PB[0.7] PB4 PB5 4 2 VR02091B VR02091B PB7 1 RS18A RS18A 100K-4R8P 100K-4R8P PB6 3 RS18B RS18B 100K-4R8P 100K-4R8P 6 5 RS18C RS18C 100K-4R8P 100K-4R8P 8 7 RS18D RS18D 100K-4R8P 100K-4R8P PB[0.7] ST626x-EMU2 - ANNEX Figure 5. Port B and Timer 2 buffer 29/38 33 30/38 34 GND TOUT 100K R3 R2 10K TIMOUT PRUN CLOCK D[0.7] NRESETI WRITE READ LATCH0 LATCH1 PLD1A[0.4] VCE R1 47K 4 5 6 7 8 9 10 11 PUPCAD2 OUTPC2 TSPC2 INPC2 D2 VCC 1 18 19 21 22 23 PUPCAD1 OUTPC1 TSPC1 INPC1 D1 D0 ITSI4 12 13 14 15 17 PUPCAD0 OUTPC0 TSPC0 INPC0 D[0.7] PLD1A[0.4] INPC[0.7] OUTPC[0.7] TSPC[0.7] PUPPC[0.7] I I I I I I I I N NNN N NN N PPPPPPPP U UUU U UU U TTTTTTTT / C L K I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 74HC14 74HC14 2 P OT I UUSN PT PP C P CC A C3 3 D3 3 D 4 33444444 89012345 R D P OT I B 3 UU S N B PT PP 3 CP CC AC4 4 D4 4 2 2222233 4 5678901 I/O I/O I/O I/O I I I I I I I I I I I I I I I I I/O / / / / / / / / / / / / / / / / O O O O O O O O O O OO O O OO IC12A IC12A LVI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PPP P LLL L DDD D 111 1 AAA A 321 0 PC[0.7] File : PC07.SCH 333366 12245668 INPC[0.7] TSPC[0.7] OUTPC[0.7] PUPPC[0.7] PORT C IC9 PLD1A4 EPM5128 EPM5128 51 49 48 47 46 57 56 55 53 52 65 64 63 62 61 60 59 58 D5 INPC5 TSPC5 OUTPC5 PUPCAD5 D6 INPC6 TSPC6 OUTPC6 PUPCAD6 D7 RBB2 RBB1 RBB0 INPC7 TSPC7 OUTPC7 PUPCAD7 PC[0.7] W8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MW2X8C RBB[0.3] RP15 GND 10K-S10 10K-S10 PC[0.7] 2 3 4 5 6 7 8 9 10 1 VCC 1 GND18 GND18 17 14 13 8 7 4 3 11 1 GND18 GND18 17 14 13 8 7 4 3 11 1 10K-S10 10K-S10 RP11 1 234567890 PUPCAD7 PUPCAD6 PUPCAD5 PUPCAD4 PUPCAD3 PUPCAD2 PUPCAD1 PUPCAD0 PUPCAD7 PUPCAD6 PUPCAD5 PUPCAD4 PUPCAD3 PUPCAD2 PUPCAD1 PUPCAD0 PUPPC0 PUPPC7 PUPPC1 PUPPC2 PUPPC6 PUPPC5 PUPPC3 PUPPC4 2 1 D7 D6 D5 D4 D3 D2 D1 D0 374E IC19 CLK OC D7 D6 D5 D4 D3 D2 D1 D0 374E IC27 CLK OC VCE 19 16 15 12 9 6 5 2 19 16 15 12 9 6 5 2 2 3 4 5 6 7 8 9 10 RS9A 1K-4R8P 2 RS9B 3 4 5 RS10A RS10A 1 RS10B RS10B 4 3 6 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 OUTPC7 OUTPC6 OUTPC5 OUTPC4 OUTPC0 OUTPC3 OUTPC2 OUTPC1 1 RS9D 8 VR02091H VR02091H VCE 1 10K-S10 10K-S10 RP5 LVI RBB[0.3] ITSI4 TIM1IN EXT[0.9] PCCAD[0.7] 2 3 4 5 6 7 8 9 10 OUTPC0 OUTPC1 OUTPC2 OUTPC3 OUTPC4 OUTPC5 OUTPC6 OUTPC7 EXT[0.9] 1K-4R8P RS10D RS10D 7 RS10C RS10C 5 8 RS9C 6 TSPC7 TSPC6 TSPC5 TSPC4 TSPC0 TSPC2 TSPC1 TSPC3 PCCAD[0.7] VCE 7 EXT7 EXT8 PCCAD7 PCCAD6 PCCAD5 PCCAD4 PCCAD3 PCCAD2 PCCAD1 PCCAD0 PUPPC7 PUPPC6 PUPPC5 PUPPC4 PUPPC3 PUPPC2 PUPPC1 PUPPC0 10K-S10 10K-S10 RP14 ST626x-EMU2 - ANNEX Figure 6. Port C and SIO OUTPC1 TSPC1 PUPPC1 74HC4049I 74HC4049I 74HC4049I 74HC4049I INPC3 12 9 5 74HC4049I 74HC4049I IC29E IC29E 11 OUTPC3 TSPC3 PUPPC3 INPC2 IC29B IC29B 4 5 OUTPC2 TSPC2 3 11 12 6 5 8 9 74HC14E 74HC14E 11 IC38E IC38E 8 IC51C IC51C 74HC126E 74HC126E 1 0 74HC14E 74HC14E 3 IC38B IC38B 6 IC51B IC51B 74HC126E 74HC126E 4 74HC14E 74HC14E 13 IC38F IC38F 11 IC51D IC51D 74HC126E 74HC126E 1 3 74HC14E 74HC14E 1 IC38A IC38A IC20C IC20C 74HC126E 74HC126E 10 1 0 VCE IC20B IC20B 74HC126E 74HC126E 4 4 VCE 1 3 IC51A IC51A 74HC126E 74HC126E IC20D IC20D 74HC126E 74HC126E 12 1 3 VCE IC20A IC20A 74HC126E 74HC126E 2 12 2 1 2 TSPC[0.7] VCE INPC[0.7] OUTPC[0.7] PUPPC[0.7] IC29F IC29F 15 14 INPC1 74HC4049I 74HC4049I PUPPC2 INPC0 IC29A IC29A 2 3 OUTPC0 TSPC0 PUPPC0 INPC[0.7] PUPPC[0.7] TSPC[0.7] OUTPC[0.7] 1 RS2A 100K-4R8P 100K-4R8P 2 PC3 7 RS1D 100K-4R8P 100K-4R8P 8 PC2 5 RS1C 100K-4R8P 100K-4R8P 6 PC1 3 RS1B 100K-4R8P 100K-4R8P 4 PC0 5 9 12 2 74HC4049I 74HC4049I OUTPC7 IC16E IC16E INPC7 12 11 TSPC7 PUPPC7 IC16B IC16B 4 5 INPC6 74HC4049I 74HC4049I OUTPC6 TSPC6 PUPPC6 IC16F IC16F 15 14 INPC5 74HC4049I 74HC4049I OUTPC5 TSPC5 PUPPC5 IC16A IC16A 2 3 INPC4 74HC4049I 74HC4049I OUTPC4 TSPC4 PUPPC4 2 11 12 2 5 3 6 IC43B IC43B 74HC126E 74HC126E 4 74HC14E 74HC14E IC21F IC21F 13 11 IC43D IC43D 74HC126E 74HC126E 1 3 74HC14E 74HC14E IC21A IC21A 1 8 9 1 0 74HC14E 74HC14E IC21E IC21E 11 8 IC43C IC43C 74HC126E 74HC126E IC28C IC28C 10 74HC126E 74HC126E 1 0 VCE 6 IC21B IC21B IC28B IC28B 4 3 74HC126E 74HC126E 74HC14E 74HC14E 4 VCE 1 IC43A IC43A 74HC126E 74HC126E IC28D IC28D 74HC126E 74HC126E 12 1 3 VCE 74HC126E 74HC126E 3 IC28A IC28A 1 VCE PC[0.7] PC7 100K-4R8P 100K-4R8P VR02091I VR02091I 8 7 RS2D 5 RS2C 100K-4R8P 100K-4R8P 6 PC6 3 RS2B 100K-4R8P 100K-4R8P 4 PC5 PC4 1 RS1A 100K-4R8P 100K-4R8P 2 PC[0.7] ST626x-EMU2 - ANNEX Figure 7. Port C and SIO buffers 31/38 35 32/38 36 2 9 10 11 7 6 2 A B CLR 74HC123 74HC123 8 Q 12 5 74HC04 74HC04 IC11D IC11D Q C6 22PF 9 REXT/CEXT IC35B IC35B CEXT GND WRITE READ A[0.7] 74HC04 74HC04 GND RSTINT STOP WAIT GND 1M XT2 R8 4049I 4049I IC15A IC15A D[0.7] 3 8MHZ IC11A IC11A C5 22PF 1 OPTSER WRITE READ A[0.7] D[0.7] NRESETI EXTINT PULS OSCIN TY2 TY9 PRUN0 RAMADD1 PRUN D2 RDRBB2 RAMD2 TY2B D3 RDRBB3 RAMADD0 OPTSER A5 RAMADD5 D1 RDRBB1 RAMD1 NCERAM A4 RAMADD4 25 26 27 28 29 30 31 32 20 21 22 23 12 13 14 15 16 17 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O WR RE I A TD E 11 10987654 I I I I I I I I / / / / / / / / O OO O OO O O I I I I NNNN PPPP UUUU TTTT R ST BW A T Y NA M O9 K I D PB3 T 3 I I I I I I / / / / / / OO O O OO DR R E R 7 DA X E R MT S B D9 B B7 U I 7 L D U P 877777 098765 B B B E RRD NNN X A D4 K K K T MR 0 1 2 1 DB 04B 4 44445555 67890123 I I I I I I I I / / / / / / / / O OOO O O OO W3 1 1 2 2 3 3 MW1X3C WATCHDOG AA A A 0123 333333 345678 HARD SOFT 4444 1234 I I I I I I / / / / / / O OO O OO 88 2143 I I I I N N NN P PPP U U UU TTTT / C L K RR D AD0 MR DB 0B 0 E N D B U I L D U P W7 1 EXT 2 INT 3 MW1X3C CLOCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 1 GND 10K-S10 10K-S10 RP25 2 3 4 5 6 7 8 9 10 RAMADD2 CKBUILDUP D5 RDRBB5 RAMD5 A6 RAMADD6 RAMADD3 D6 RDRBB6 RAMD6 CLKSYSTNB A7 RAMADD7 EPM5192 EPM5192 59 58 57 56 55 54 65 64 63 62 74 73 72 71 70 69 68 67 IC7 GND VCC 1 5 6 R21 1K 18 16 14 12 9 7 5 3 10K-S10 10K-S10 2 3 4 5 6 7 8 9 10 IC52B IC52B 74HC126E 74HC126E RP26 R19 1K 4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 74HC244 74HC244 1G 2G 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 IC1 VCE 1 19 2 4 6 8 11 13 15 17 3 10 11 NCERAM 20 26 RWRAM 27 22 10 9 8 7 6 5 4 3 25 24 21 23 2 2 4 6 8 CY7C185 CY7C185 CS1 CS2 WE OE 11 12 13 15 16 17 18 19 VR02091L VR02091L D0 D1 D2 D3 D4 D5 D6 D7 DRBB[0.7] RAMPB[0.7] EXT[0.10] CKNMI VCKOUT MW2X4C 1 3 5 7 W2 IC14 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 RDRBB[0.7] RDRBB[0.7] EXT[0.10] 1 15 14 12 13 4 2 3 5 6 7 9 1K R12 74HC123 74HC123 RAMADD0 RAMADD1 RAMADD2 RAMADD3 RAMADD4 RAMADD5 RAMADD6 RAMADD7 BNK0 BNK1 BNK2 BNK3 HC4040 HC4040 IC18 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 RST Q3 Q2 CLK Q1 100K IC35A IC35A OSCOUT PRUN ROMADR TY2B TY9B CLKSYST INTRES CLOCK CEXT C8 10NF 15 REXT/CEXT 1 A Q 13 2 B 3 CLR Q 4 14 IC52A IC52A 74HC126E 74HC126E 1 GND VCC R11 2 VCE PRUN RAMD0 RAMD1 RAMD2 RAMD3 RAMD4 RAMD5 RAMD6 RAMD7 ST626x-EMU2 - ANNEX Figure 8. RAM, EEPROM, Bank reg., Data ROM windowing, watchdog, Reset 3 IC26A IC26A 74HC14E 74HC14E 4 2 VCCAPP GND VCC 7 5 6 -VIN -VIN VSRC V1 +VIN +VIN 0,330 R17 12 13 1 24 4049I 4049I IC15B IC15B 4049I 4049I IC15C IC15C ITSI4 NITTIM1 NITADC NITTIM2 ITRTC A[0.7] CLOCK 74HC14E 74HC14E LVI EXTRES BDIO EXWR VCC 1 VCE R18 100K NRESETAP CKNMI RESTO RESSO NITPB NITTIM1 ITSI4 NITTIM1 NITADC NITTIM2 VCE ITRTC PRUN VCKOUT R15 100K IC26B IC26B TY9B A[0.7] CLOCK 4 5 7 8 1 D1 1N4004 1N4004 15 16 17 18 19 20 21 22 15 16 17 18 19 20 21 22 15 16 17 18 19 20 21 22 INT0 INT1 INT2 INT3 INT4 C18 PLD1A0 PLD1A1 PLD1A2 PLD1A3 PLD1A4 100nF COMP MC34063 MC34063 IPK CT SW OUT 3 2 C19 470pF BYV10-20 BYV10-20 56uH IC56 DR IN SW IN D4 GND 1 2 F0 F1 F2 F3 F4 F5 F6 F7 F0 F1 F2 F3 F4 F5 F6 F7 F0 F1 F2 F3 F4 F5 F6 F7 L1 VCC IC3 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 20V8 IC2 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 20V8 IC5 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 20V8 DC/DC CONVERTER 330 R16 15 10 14 11 1 2 3 4 5 6 7 8 9 10 11 13 14 23 1 2 3 4 5 6 7 8 9 10 11 13 14 23 C12 100nF -VOUT -VOUT +VOUT +VOUT A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 13 14 23 15K R22 R24 680 R23 1,5K C13 470uF-EA INT[0.4] PLD1A[0.4] C15 10uF READ WRITE RSTINT NRESETI INT[0.4] 2 1 PLD1A[0.4] 10K R20 C14 100NF 100NF 10uH L2 GND C16 2 10uF 1 RP27 10K-S10 10K-S10 W5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MW2X8C W6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MW2X8C C21 100NF 100NF VCC VCC 1 1 098765432 C17 1uF 2 3 GND GND RP9 10K-S10 10K-S10 R25 100K 198765432 0 1 VCC 1 1 4 GND 2 15 1 10 11 12 13 14 3 4 5 6 2 15 1 10 11 12 13 14 3 4 5 6 9 7 9 7 R14 10K LM324 LM324 1 IC57A IC57A CLK QH INH SH/LD 74HC165 74HC165 IC34 SER A B C D E F G H QH CLK QH INH SH/LD 74HC165 74HC165 IC17 SER A B C D E F G H QH VCE Q1 BD233 BD233 GND VCC VCE VDDI VR02091E VR02091E R26 1K D3 1N4148 1N4148 D2 1N4148 1N4148 OPTSER ST626x-EMU2 - ANNEX Figure 9. Control and interface power 33/38 37 34/38 38 D[0.7] GND PCCAD[0.7] PBCAD[0.7] 1K R10 PACAD[0.7] NADCRRR NSTARTADC ADCCLOCK ADCCLOCK VSREF VSREF D[0.7] PCCAD[0.7] PC[0.7] PBCAD[0.7] PB[0.7] PACAD[0.7] PA[0.7] GND 1 19 2 4 6 8 11 13 15 17 1 19 2 4 6 8 11 13 15 17 1 19 2 4 6 8 11 13 15 17 GND PCCAD0 PCCAD1 PCCAD2 PCCAD3 PCCAD4 PCCAD5 PCCAD6 PCCAD7 PC[0.7] PBCAD0 PBCAD1 PBCAD2 PBCAD3 PBCAD4 PBCAD5 PBCAD6 PBCAD7 PB[0.7] GND PACAD0 PACAD1 PACAD2 PACAD3 PACAD4 PACAD5 PACAD6 PACAD7 PA[0.7] 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 1G 2G 74HC244 74HC244 IC36 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 74HC244 74HC244 IC30 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 1G 2G 74HC244 74HC244 IC55 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 18 16 14 12 9 7 5 3 18 16 14 12 9 7 5 3 18 16 14 12 9 7 5 3 1 3 9 11 13 5 6 12 PA4 PA5 PA6 PA7 1 3 9 11 13 5 6 12 PB4 PB5 PB6 PB7 1 3 9 11 13 5 6 12 1 3 9 11 13 5 6 12 PC0 PC1 PC2 PC3 1 3 9 11 13 5 6 12 PB0 PB1 PB2 PB3 1 3 9 11 13 5 6 12 PA0 PA1 PA2 PA3 PC4 PC5 PC6 PC7 O1 O2 O3 O4 O1 O2 O3 O4 O1 O2 O3 O4 4066EC 4066EC 4066EC 4066EC IC44 I1 O1 I2 O2 I3 O3 I4 O4 C1 C2 C3 C4 IC37 I1 I2 I3 I4 C1 C2 C3 C4 4066EC 4066EC 4066EC 4066EC IC47 I1 O1 I2 O2 I3 O3 I4 O4 C1 C2 C3 C4 IC31 I1 I2 I3 I4 C1 C2 C3 C4 4066EC 4066EC 4066EC 4066EC IC58 I1 O1 I2 O2 I3 O3 I4 O4 C1 C2 C3 C4 IC59 I1 I2 I3 I4 C1 C2 C3 C4 2 4 8 10 2 4 8 10 2 4 8 10 2 4 8 10 2 4 8 10 2 4 8 10 GND C9 10uF +12V C11 10uF -12V GND D0 D1 D2 D3 D4 D5 D6 D7 +12V 3 2 -12V 8 EOCN TL072A TL072A 1 4 IC50A IC50A AINB 1 2 3 5 18 17 16 15 14 13 12 11 GND CLK CLKR VI- VI+ AIND 7 8 9 4 19 VSREF 6 VR02091C VR02091C EOCADC CS RD VREF WR INTR AGND ADC0802C ADC0802C IC6 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 C10 2.2nF R13 470 GND R5 1K R4 1K VCE ST626x-EMU2 - ANNEX Figure 10. Analog To Digital Converter GND VSREF NRES XTAL EXTAL VCCAPP PC[0.7] PB[0.7] PA[0.7] VSS VSREF NRES GND PA0 VCCAPP GND PA1 PA2 PA3 PA4 PA5 PA6 PA7 XTAL EXTAL NRES PB7 PB6 PB5 VCCAPP PC1 XTAL EXTAL CKNMI PC7 PC6 PC5 PC4 PB6 PB7 PC[0.7] PB[0.7] PA[0.7] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ST2621X ST2621X PROBE CONNECTORS J3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 HE1034DM HE1034DM J1 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 HE1034DM HE1034DM GND GND Number of component's pin ST2626X ST2626X and ST629X ST629X PROBE CONNECTORS J4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 HE1034DM HE1034DM J2 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 HE1034DM HE1034DM 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 VSREF PB5 PB4 PB3 PB2 TST PB1 PB0 PC0 PC1 PC2 PC3 PC4 CKNMI NRES VR02091D VR02091D GND CKNMI ST626x-EMU2 - ANNEX Figure 11. Application connectors 35/38 39 VDD G ND N RES PB7 PB6 DIL16 DIL16 G ND VSS PA1 PA2 PA3 XT1 10M 74HC04 74HC04 R4 2 12 11 10 9 16 15 14 13 TP3 TP4 TP5 8MHZ-XT-P 1 U4A PB0 PB1 PB3 PB5/AIN1 GN D r esonnat eur VPP/TEST R ESET PB7/AIN3 PB6/AIN2 C3 470PF 470PF 5 6 7 8 VCCAPP OSCIN OSCOUT CKNMI U 1 VDD OSCIN OSCOUT NI M VCCAPP 1 2 3 4 VSS VCC GD N C4 1NF R5 3.3 PB0 PB1 PB3 PB5 PA1 PA2 PA3 G ND 3 VCC G ND 4 C D1 100NF 100NF 74HC04 74HC04 U4B 1 40 2 36/38 NR ES PB7 PB6 PB5 VCCAPP PC 1 XTAL EXTAL CKNM I PC7 PC6 PC5 PC4 1 2 3 4 5 OSCIN 2 W1 1 1 2 2 3 3 MW3X1C G ND VPP/TEST RESET PB7 PB6 PB5 DIL20 DIL20 U2 VDD TIM OSCIN OSCOUT NM I MW 2X1C W2 NRES PB7 PB6 PB5 1 6 7 8 9 10 VCCAPP PC1 OSCIN OSCOUT CKNMI G ND 5 15 14 13 12 11 20 19 18 17 16 74HC04 74HC04 U4C PB0 PB1 PB2 PB3 PB4 VSS PA0 PA1 PA2 PA3 P R OB E EXTAL ST2 6 2 0 X/ 1 X/ 2 X J3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 HE10-34DM HE10-34DM 6 G ND 1K R1 100NF 100NF C1 PB0 PB1 PB2 PB3 PB4 PA0 PA1 PA2 PA3 GND VCC C2 100PF 100PF C 100PF 100PF R4 100K GND J4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 HE10-34DM HE10-34DM 9 74HC04 74HC04 U4D XTAL NRES PB7 PB6 PB5 VCCAPP PC1 OSCIN OSCOUT CKNMI PC7 PC6 PC5 PC4 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 VSREF 8 U 3 VDD T IM OSCIN OSCOUT NI M PC 7 PC 6 PC 5 PC 4 VPP/TEST R ESET PB7 PB6 PB5 DIL28 DIL28 OSCOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 G ND G ND VSS PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 TP1 MW1X1C 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GD N TP2 MW1X1C PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 VCC ST626x-EMU2 - ANNEX 6.3 PROBE Figure 12. Probe for ST620x, ST621x, ST622x GD N C 3 470PF 470PF XT1 10M 74H C04 R 3 U4A P2 T P1 T TP 3 2 TP 4 8MH Z-XT-P 1 TP 5 GD N reso ate nn ur GD N GD N J1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 H E10-34D E10-34D M GD N VCC C 4 1N F R 4 3.3 VSR EF P B6 P B7 PA0 VCC APP VSR EF PA1 PA2 PA3 PA4 PA5 PA6 PA7 XTAL EXTAL 3 74HC 04 U4B GD N 4 OC S IN 1 2 GD N VCC PB 6 PB 7 PA0 PB6 PB7 PA0 W 3 1 1 2 2 3 3 M 3X1C W M 2X1C W W 4 VC C P I N P ROB E U2 1 1 20 2 2 19 3 3 18 4 4 17 5 5 16 6 7 6 15 8 7 14 9 8 13 10 9 12 10 11 DIL20 DIL20 20 5 74HC04 74HC04 U 4C PB0 PB2 PB3 PB6/TIM 2I PB7/TIM 2O VCCAPP VSREF 16 PB0 PB1 PB2 PB3 PB6/TIM 2I PB7/TIM 2O PA0/ADC VCCAPP VSREF CONN E C T ORS 20 PC2/SI/ADC 19 PC3/SO/ADC 18 PC4/SK/ADC 17 16 NR S E 15 O UT SCO 14 O IN SC 13 PA3/ADC 12 PA2/ADC 11 PA1/ADC CONN E C T ORS 28 PC0/ADC 27 PC1/TIM 1/ADC 26 PC2/SI/ADC 25 PC3/SO/ADC 24 PC4/SK/ADC 23 22 NR S E 21 O UT SCO 20 O SCIN 19 PA7/ADC 18 PA6/ADC 17 PA5/ADC 16 PA4/ADC 15 PA3/ADC 6 1 2 3 4 5 6 7 8 1K R5 U3 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 DIL16 DIL16 16 15 14 13 12 11 10 9 GD N XTAL C2 100PF 100PF PC 2 PC 3 NR S E O UT SCO O IN SC PA5 PA4 P I N P ROB E C ONN E C T ORS P I N P ROB E U 1 1 1 28 2 2 27 3 3 26 4 4 25 5 5 24 6 6 23 7 7 22 8 8 21 9 10 9 20 11 10 19 12 11 18 13 12 17 14 13 16 14 15 DIL28 DIL28 28 PB0 PB1 PB2 PB3 PB4 PB5 PB6/TIM 2I PB7/TIM 2O PA0/ADC VCCAPP VSREF PA1/ADC PA2/ADC PA3 PA2 PA1 PC 2 PC 3 PC 4 PA7 PA6 PA5 PA4 PA3 P0 C P1 C P2 C P3 C P4 C W 1 2 M 2X1C W G1 EXTAL G UTTEO O UVER TE M 2X1C W G 2 G UTTECO O NTACT W 2 1 2 1 100N F C 1 PB 5 PB 4 PB 3 PB 2 PB 1 PB 0 P0 C P1 C P2 C P3 C P4 C N I/C U M KO T NE RS GD N C 100PF 100PF 9 74HC 04 U 4D J2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 HE10-34DM HE10-34DM 8 GD N O OT SC U ST626x-EMU2 - ANNEX Figure 13. Probe for ST625x, ST626x, ST629x 37/38 41 ST626x-EMU2 - ANNEX Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics ©1998 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com 38/38 42