ST52T430/E430 ST52T430K2 ST52T430K3 ST52E430K3 SSO34 PSDIP32 SDIP32 ST52X430 - Datasheet Archive

 

ST52T430/E430 ® 8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Three Timer/PWMs, ADC, SCI PRELIMINARY DATA Memories Up to 8 Kbytes

 

ST52T430/E430 ST52T430/E430 ST52T430/E430 ST52T430/E430 ® 8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Three Timer/PWMs, ADC, SCI PRELIMINARY DATA Memories Up to 8 Kbytes EPROM/OTP 256 bytes of RAM Readout Protection Core Register File Based Architecture 55 instructions Hardware multiplication and division Decision Processor for the implementation of Fuzzy Logic algorithms Clock and Power Supply Up to 20 MHz clock frequency. Power Saving features Interrupts 6 interrupt vectors Top Level External Interrupt (INT) Peripherals 3 Programmable 8-bit Timer/PWMs with internal 16-bit Prescaler featuring: ­ PWM output I/O Ports 23 I/O PINs configurable in Input and Output mode High current sink/source in all pins. ­ Input capture ­ Output Compare ­ Pulse Generator mode Watchdog timer On-chip 8-bit Sample and Hold A/D Converter with 8-channel analog multiplexer Serial Communication Interface with asynchronous protocol (UART) Development tools High level Software tools Emulator Low cost Programmer Gang Programmer ST52x430 Devices Summary Device NVM RAM Timer PWM ADC SCI Watchdog Operating Supply I/O Package ST52T430K2 ST52T430K2 4K OTP 256 3x8-bit 8-Ch Yes Yes 3.0-5.5 V 23 Sdip32 Sso34 ST52T430K3 ST52T430K3 8K OTP 256 3x8-bit 8-Ch Yes Yes 3.0-5.5 V 23 Sdip32 Sso34 ST52E430K3 ST52E430K3 8K EPROM 256 3x8-bit 8-Ch Yes Yes 3.0-5.5 V 23 Csdip32w Rev. 1.12 - May 2004 1/85 This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice. ST52T430/E430 ST52T430/E430 TABLE TENTS OF CON- TABLE OF CONTENTS 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2.1 Memory Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.2 Working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2 INTERNAL ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 ST52x430 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 Control Unit and Data Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2.1 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.3.1 RAM and STACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.2 Input Registers Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.3 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.4 Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3 EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 EPROM Programming Phase Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.1.1 EPROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1.2 EPROM Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1.3 EPROM Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1.4 EPROM Read/Verify Margin Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1.5 Stand by Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1.6 ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 Eprom Erasure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.2 Global Interrupt Request Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 4.3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 4.4 Interrupt Maskability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 4.5 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 4.6 Interrupts and Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 4.7 Interrupt RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5 CLOCK, RESET & POWER SAVING MODE. . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 5.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 5.3 Power Saving Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 5.3.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.2 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2/85 ST52T430/E430 ST52T430/E430 6 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 6.2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 6.3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.4 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.5 I/O Port Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 7 FUZZY COMPUTATION (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1 Fuzzy Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 7.2 Fuzzyfication Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 7.3 Inference Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 7.4 Defuzzyfication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 7.5 Input Membership Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 7.6 Output Singleton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 7.7 Fuzzy Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 8 A/D CONVERTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 8.2 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 8.2.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.2.2 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.3 A/D Registers Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 9 WATCHDOG TIMER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 9.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 10 PWM/TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.1 Timer Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 10.2 PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 10.3 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 11 SERIAL COMMUNICATION INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.1 SCI Receiver block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 11.2 SCI Transmitter Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 11.3 Baud Rate Generator Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.1 Parameter Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 12.3 Recommended Operating Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 12.4 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 3/85 ST52T430/E430 ST52T430/E430 12.5 Clock and Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 12.6 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 12.7 ESD Pin Protection Strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 12.7.1 Standard Pin Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.7.2 Multi-supply Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 12.8 Port Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.9 Control Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 12.9.1 RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.9.2 VPP pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.10 8-bit A/D Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.1 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 13.2 SILICON LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 13.2.1 Exit from HALT with a long duration External Interrupt signal . . . . . . . . . . . . . . . . . . . . . 84 13.2.2 Interrupt priority change after a RINT instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.2.3 Zero Flag after Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.3 HARDWARE TOOL WARNING DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 13.3.1 ST52x430 low cost Evaluation Kits resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4/85 ST52T430/E430 ST52T430/E430 1 GENERAL DESCRIPTION 1.1 Introduction ST52x430 is an 8-bit Intelligent Control Units (ICU) of the ST Five Family, which can perform both boolean and fuzzy algorithms in an efficient manner, in order to reach the best performances that the two methodologies allow. ST52x430 is produced by STMicroelectronics using the reliable high performance CMOS process, including integrated-on-chip peripherals that allow maximization of system reliability, decreasing system costs and minimizing the number of external components. The flexible I/O configuration of ST52x400/440 allows for an interface with a wide range of external devices, like D/A converters or power control devices. ST52x430 pins are configurable, allowing the user to set the input or output signals on each single pin. A hardware multiplier (8 bit by 8 bit with 16 bit result) and a divider (16 bit over 8 bit with 8 bit result and 8 bit remainder) are available to implement complex functions by using a single instruction. The program memory utilization and computational speed is optimized. Fuzzy Logic dedicated structures in ST52x430 ICU's can be exploited to model complex systems with high accuracy in a useful and easy way. F uz z y E x pe r t S y s te ms f or o v er a ll s y s te m management and fuzzy Real time Controls can be designed to increase performances at highly competitive costs. The linguistic approach characterizing Fuzzy Logic is based on a set of IF-THEN rules, which describe the control behavior, as well as on Membership Functions, which are associated to input and output variables. Up to 334 Membership Functions, with triangular and trapezoidal shapes, or singleton values are available to describe fuzzy variables. The Timer/PWM peripheral allows the management of power devices and timing signals, implementing different operating modes and high frequency PWM (Pulse With Modulation) controls. Input Capture and Output Compare functions are available on the TIMER. The programmable Timer has a 16 bit Internal Prescaler and an 8 bit Counter. It can use internal or external Start/Stop signals and clock. An internal programmable Watchdog is available to avoid loop errors and to reset the ICU. ST52x430 includes an 8-bit Analog to Digital Converter with an 8-analog channel Multiplexer. Single/Multiple channels and Single/Sequence conversion modes are supported. A Serial Communication peripheral (SCI), which uses the UART protocol allows data transfer from the ST52x430 to other external devices. In order to optimize energy consumption, two different power saving modes are available: Wait mode and Halt mode. Program Memory (EPROM/OTP) addressing capability addresses up to 8 Kbytes of memory locations to store both program instructions and permanent data. EPROM can be locked by the user to prevent external undesired operations. Operations may be performed on data stored in RAM, allowing the direct combination of new input and feedback data. All bytes of RAM are used like Register File. OTP (One Time Programmable) version devices are fully compatible with the EPROM windowed version, which may be used for prototyping and pre-production phases of development. A powerful development environment consisting of a board and software tools allows an easy configuration and use of ST52x430. T he VIS UA L F I VE T M s of twa re to ol al lo ws development of projects through a user-friendly graphical interface and optimization of generated code. 1.2 Functional Description ST52x430 ICU can work in two modes: I Memory Programming Mode I Working Mode according to RESET and Vpp signals levels (see pins description). Note: When RESET=0 it is advisable not to use the sequence "101010" to port PA (7 : 2). 1.2.1 Memory Programming Mode. The ST52x430 memory is loaded in the Memory Programming Phase. All fuzzy and standard instructions are written inside the memory. This phase starts by setting the control signals as illustrated below: RESET TEST VPP Vss Vss 12V/VDD When this phase starts, the ST52x430 core is set to RESET status; then 12V are applied to the Vpp 5/85 ST52T430/E430 ST52T430/E430 pin in order to start EPROM programming. A signal applied to PB1 is used to increment the memory address; the data is supplied to PORT A (see EPROM programming for further details). 1.2.2 Working mode. Below are the control signals of this mode: RESET TEST VPP VDD VSS VSS The processor starts the working phase following the instructions, which have been previously loaded in the memory. ST52x430's internal structure includes a computational block, CONTROL UNIT (CU) / DATA PROCESSING UNIT (DPU), which allows processing of boolean functions and fuzzy algorithms. 6/85 The CU/DPU can manage up to 334 different Members hip Functions for the fuzzy rules antecedent part. The rule consequents are "crisp" values (real numbers). The maximum number of rules that can be defined is limited by the dimensions of the implemented standard algorithm. EPROM is then shared between fuzzy and standard algorithms. The Membership Function data is stored inside the first 1024 memory locations. The Fuzzy rules are parts of the program instructions. The Control Unit (CU) reads the information and the status deriving from the peripherals. Arithmetic calculus can be performed on these values by using the internal CU and the 128/256 bytes of RAM, which supports all computations. The peripheral input can be fuzzy and/or arithmetic output, or the values contained in Data RAM and EPROM locations. ST52T430/E430 ST52T430/E430 Figure 1.1 SSO34 SSO34 Pin Configuration RESET 1 34 VDD OSCOUT 2 33 Vss OSCIN 3 32 VPP TEST 4 31 PA0/T0RES INT/PC0 5 30 PA1/T0OUT T0OUT/PC1 6 29 PA2/T1OUT T1OUT/PC2 7 28 PA3/T2OUT T2OUT/PC3 8 27 PA4/T0STRT TX/PC4 9 26 PA5/T0CLK RX/PC5 10 25 PA6 PC6 11 24 PB7/PA7/Ain7 PC7 12 23 PB6/Ain6 nc 13 22 nc PB0/Ain0 14 21 PB5/Ain5 PB1/Ain1 15 20 PB4/Ain4 PB2/Ain2 16 19 GNDA PB3/Ain3 17 18 VDDA Figure 1.2 PSDIP32 PSDIP32 Pin Configuration RESET 1 32 VDD OSCOUT 2 31 Vss OSCIN 3 30 VPP PA0/T0RES TEST 4 29 INT/PC0 5 28 PA1/T0OUT T0OUT/PC1 6 27 PA2/T1OUT T1OUT/PC2 7 26 PA3/T2OUT T2OUT/PC3 8 25 PA4/T0STRT TX/PC4 9 24 PA5/T0CLK RX/PC5 10 23 PA6 PC6 11 22 PB7/PA7/Ain7 PC7 12 21 PB6/Ain6 PB0/Ain0 13 20 PB5/Ain5 PB1/Ain1 14 19 PB4/Ain4 PB2/Ain2 15 18 GNDA PB3/Ain3 16 17 VDDA 7/85 ST52T430/E430 ST52T430/E430 Table 1.1 ST52x430 SSO34 SSO34 & PSDIP32 PSDIP32 Pin list SSO34 SSO34 Pins SDIP32 SDIP32 Pins NAME Programming Phase Working Phase 1 1 RESET General Reset General Reset 2 2 OSCOUT Oscillator Output 3 3 OSCIN Oscillator Input 4 4 TEST Must be tied to Vss Must be tied to Vss 5 5 INT/PC0 PHASE signal (PHASE) External interrupt, Digital I/O 6 6 T0OUT/PC1 Timer/PWM 0 output, Digital I/O 7 7 T1OUT/PC2 Timer/PWM 1 output, Digital I/O 8 8 T2OUT/PC3 Timer/PWM 2 output, Digital I/O 9 9 TX/PC4 SCI Output, Digital I/O 10 10 RX/PC5 SCI Input, Digital I/O 11 11 PC6 Digital I/O 12 12 PC7 Digital I/O 13 nc 14 13 Ain0/PB0 Address Reset (RST_ADD) Analog Input, Digital I/O 15 14 Ain1/PB1 Address Increment (INC_ADD) Analog Input, Digital I/O 16 15 Ain2/PB2 Configuration Reset (RST_CONF) Analog Input, Digital I/O 17 16 Ain3/PB3 Configuration Increment (INC_CONF) Analog Input, Digital I/O 18 17 VDDA Analog Power Supply Analog Power Supply 19 18 GNDA Analog Ground Analog Ground 20 19 Ain4/PB4 Analog Input, Digital I/O 21 20 Ain5/PB5 Analog Input, Digital I/O 22 nc 23 Ain6/PB6 24 22 Ain7/PB7/PA7 I/O EPROM Data Analog Input, Digital I/O 25 23 PA6 I/O EPROM Data Digital I/O 26 24 T0CLK/PA5 I/O EPROM Data Timer/PWM 0 clock, Digital I/O 27 25 T0STRT/PA4 I/O EPROM Data Timer/PWM 0 start/stop, Digital I/O 28 26 T2OUT/PA3 I/O EPROM Data Timer/PWM 2 compl. output, Digital I/O 29 27 T1OUT/PA2 I/O EPROM Data Timer/PWM 1 compl. output, Digital I/O 30 28 T0OUT/PA1 I/O EPROM Data Timer/PWM 0 compl. output, Digital I/O 31 29 T0RES/PA0 I/O EPROM Data Timer/PWM 0 Reset, Digital I/O 32 30 VPP EPROM Programming Power supply (12V ± 5%) EPROM VDD or Vss 33 31 Vss Digital Ground Digital Ground 34 8/85 21 Analog Input, Digital I/O 32 VDD Digital Power Supply Digital Power Supply ST52T430/E430 ST52T430/E430 1.3 Pin Description VDD, VSS, V DDA, GNDA, V PP . In order to avoid noise disturbances, the power supply of the digital part is kept separate from the power supply of the analog part. VDD. Main Power Supply Voltage (5V± 10%). VSS. Digital circuit ground. V DD A . Analog V D D of the Analog to Digital Converter. GNDA. Analog V SS of the Analog to Digital Converter. Must be tied to VSS. V PP . Main Power Supply for internal EPROM (12.5V±5%, in programming phase) and MODE selector. During the Programming phase (programming), V PP must be set at 12V. In the Working phase VPP must be equal to VSS. OSCin and OSCout. These pins are internally connected with the on-chip oscillator circuit. A quartz crystal or a ceramic resonator can be connected between these two pins in order to allow the correct operations of ST52x430 with various stability/cost trade-off. An external clock signal can be applied to OSCin, in this case OSCout must be floating. RESET. This signal is used to restart ST52x430 at the beginning of its program. It also allows one to select the program mode for EPROM. Ain0-Ain8. These 8 lines are connected to the input of the analog multiplexer. They allow the acquisition of 8 analog input. During the Programming phase, Ain0, Ain1, Ain2 and Ain3 are used to manage EPROM operation. PA0-PA7, PB0-PB7, PC0-PC7. These lines are organized as I/O port. Each pin can be configured as input or output. PA7/PB7 are tied to the same output. During Programming phase PA port is used for EPROM read/write data. T0RES, T0CLK, T0STRT. These pins are related with the internal Programmable Timer/PWM 0. This Timer can be reset externally by using T0RES. In Working Mode, T0RES resets the address counter of the Timer. T0RES is active at low level. The Timer 0 Clock can be the internal clock or can be supplied externally by using pin T0CLK. An external Start/Stop signal can be used to control the Timer through T0STRT pin. T0OUT, T1OUT, T2OUT. The TIMER/PWM outputs are available on these pins. T0OUT, T1OUT, T2OUT. The TIMER/PWM complementary outputs are available on these pins. Tx. Serial data output of SCI transmitter block Rx. Serial data input of the SCI receiver block. TEST. During the Programming and Working phase it must be set to Vss. 9/85 ST52T430/E430 ST52T430/E430 Figure 1.3 ST52X430 ST52X430 Block Diagram TIMER/PWM 0 PROGRAM MEMORY TIMER/PWM 1 EPROM TIMER/PWM 2 PA7:0 CORE PORT A INTERRUPTS CONTROLLER ALU & DPU PORT C PC7:0 DECISION PROCESSOR SCI CONTROL UNIT Register File 256 bytes Input registers PORT B PB7:0 VDDA ADC GNDA PC FLAGS WATCHDOG POWER SUPPLY VDD 10/85 VPP VSS OSCILLATOR RESET CIRCUIT OSCIN OSCOUT RESET ST52T430/E430 ST52T430/E430 2 INTERNAL ARCHITECTURE ST52x430 is made up of the following blocks and peripherals: I Control Unit (CU) and Data Processing Unit (DPU) I ALU / Fuzzy Core I EPROM I 256 Byte RAM I Clock Oscillator I Analog Multiplexer and A/D Converter I 3 PWM / Timers I SCI I Digital I/O port 2.1 ST52x430 Operating Modes ST52x430 works in two modes, Programming and Working Modes, depending on the control signals level RESET, TEST and VPP The Operating modes are selected by setting the control signal level as specified in the Control Signals Setting table. Table 2.1 Control Signals Setting Control Signal Programming Reset Working RESET VSS VSS VDD TEST VSS VSS 12 V The CU structure is very flexible. It was designed with the purpose of easily adapting the core of the microcontroller to market needs. New instruction sets or new peripherals can be easily included without changing the structure of the microcontroller, maintaining code compatibility. The CU reads the instructions stored on EPROM (Fetch) and decodes them. According to the instruction types, the arbiter activates one of the main blocks of the CU. Afterwards, all the control signals for the DPU are generated. A set of 46 different arithmetic, fuzzy and logic instructions is available. Each instruction requires 6 (fuzzy instructions) to 26 (DIVISION) clock pulses to be performed. The DPU receives, stores and sends instructions deriving from EPROM, RAM or peripherals in order to execute them. 2.2.1 Program Counter. The Program Counter (PC) is a 13-bit register that contains the address of the next memory location to be processed by the core. This memory location may be an opcode, operand, or an address of an operand. The 13-bit length allows direct addressing of a maximum of 8,192 bytes in the program space. After having read the current instruction address, the PC value is incremented. The result of this operation is shifted back into the PC. The PC can be changed in the following ways: VSS VPP parts of the CU so that only one part of the system is activated during working mode. I I RETIPC = Pop (stack) RETPC = Pop (stack) CALLPC = Subroutines address I 2.2 Control Unit and Data Processing Unit The Control Unit (CU) formally includes five main blocks. Each block decodes a set of instructions, generating the appropriate control signals. The main parts of the CU are illustrated in Figure 2.1. The five different parts of the CU manage Loading, Logic/Arithmetic, Jump, Control and the Fuzzy instruction set. The block called "Collector" manages the signals deriving from the different parts of the CU, defining the signals for the Data Processing Unit (DPU) and the different peripherals of the microcontroller. The block called "Arbiter" manages the different- InterruptPC = Interrupt Vector I VSS I I VSS JP (Jump)PC = Jump Address ResetPC = Reset Vector I Normal InstructionPC = PC + 1 2.2.2 Flags. The ST52x430 core includes a different set of flags that correspond to 2 different modes: normal mode and interrupt mode. Each set of flags consists of a CARRY flag (C), ZERO flag (Z) and SIGN flag (S). One set (CN, ZN, SN) is used during normal operation and one is used during interrupt mode (CI, ZI, SI). Formally, the user has to manage only one set of flags: C, Z and S. 11/85 ST52T430/E430 ST52T430/E430 Figure 2.1 Data Processing Unit (DPU) CU PROGRAM CO UNTER EPROM INPUT S PER IPH ERAL S add_EPR M U X PERIPHERALS RAM ADDRESS RAM STACK POINT FUZZY REGISTER S 256 Bytes M ULTIP LEXER AC CUMU LATOR FLAGS REG. ALU Figure 2.2 CU/DPU Block Diagram R A M D a t a 8 B it R A M A d d r. 8 B it RAM E P R O M RAM D a ta O u t 8 B it M ic r o c o d e C U C o n t r o l S ig n a ls E P R O M A d d re s s 12/85 D P U T o P e r ip h e r a ls F ro m P e r ip h e r a ls ST52T430/E430 ST52T430/E430 The ST52x430 core uses flags that correspond to the actual mode. As soon as an interrupt is generated the ST52x430 core uses the interrupt flags instead of the normal flags. Each interrupt level has its own set of flags, which is saved in the STACK together with the Program Counter. These flags are restored from the STACK automatically when a RETI instruction is executed. If the MCU was in normal mode before an interrupt, the normal flags are restored when the RETI instruction is executed. Note: A CALL subroutine is a normal mode execution. For this reason, a RET instruction, consequent to a CALL instruction does not affect the normal mode set of flags. Flags are not cleared during context switching and remain in the state they were at the end of the last interrupt routine switching. The Carry flag is set when an overflow occurs during arithmetic operations, otherwise it is cleared. The Sign flag is set when an underflow occurs during arithmetic operations, otherwise it is cleared. 2.3 Address Spaces ST52x430 has four separate address spaces: I RAM: 256 Bytes I Input Registers: 20 8-bit registers I Output Registers 10 8-bit registers I Configuration Registers: 21 8-bit registers Program memory up to 8K Bytes Program memory will be described in further details in the MEMORY section I 2.3.1 RAM and STACK. RAM memory consists of 256 general purpose 8bit RAM registers. All the registers in RAM can be specified by using a decimal address. For example, 0 identifies the first register of RAM. To read or write RAM registers LOAD instructions must be used. See Table 2.5 Each interrupt level has its own set of flags, which is saved in the STACK together with the Program Counter. These flags are restored from the STACK automatically when a RETI instruction is executed. When the instructions like Interrupt request or CALL are executed, a STACK level is used to push the PC. The STACK is located in RAM. For each level of stack, 2 bytes of RAM are used. The values of this stack are stored from the last RAM register (address 255). The maximum level of stack must be less than 128. Figure 2.3 Address Spaces Description ST52X430 ST52X430 CORE PROGRAM MEMORY ON CHIP PERIPHERALS PERIPHERAL REGISTERS INPUT REGISTERS LDPR CONTROL UNIT RAM DPU PERIPHERAL ALU CONFIGURATION REGISTERS BLOCK LDRI LDRC LDCE LDCR 13/85 ST52T430/E430 ST52T430/E430 The STACK POINTER indicates the first level available to store data. When a subroutine call or interrupt request occurs, the content of the PC and the current set of flags are stored into the level located by the STACK POINTER. When a interrupt return occurs (RETI instruction), the data stored in the highest stack level is restored back into the PC and current flags. Instead, when a subroutine return occurs (RET instruction) the data stored in the highest stack level are restored in the PC not affecting the flags. These operating modes are illustrated in Figure 2.4. Note: The user must pay close attention to avoid overwriting RAM locations where the STACK could be stored. 2.3.2 Input Registers Bench. The Input Registers (IR) bench consists of 20 8-bit registers containing data or the status of the peripherals. All the registers can be specified by using a decimal address (for example, 0 identifies the first register of the IR). The assembler instruction: LDRI RAM_Reg. IR_i loads the value of the i-th IR in the RAM location identified by the RAM_Reg address. The first input register is dedicated to store the value of the stack pointer. The next 8 registers (ADC_OUT_0:7) of the IR are dedicated to the 8 converted values deriving from the ADC. The last 9 Input Registers contain data from the I/O ports and PWM/Timers. The following table summarizes the IR address and the relative peripherals. In order to simplify the concept, a mnemonic name is assigned to the registers. The same name is used in VISUALSTUDIO® development tools Figure 2.4 Stack Operation PROGRAM COUNTER RAM REG 0 REG 1 REG 2 REG 3 REG 4 REG 5 WHEN CALL OR INTERRUPT REQ. OCCURS WHEN RETI OR RET OCCURS Stack Pointer STACK LEVEL n . REG 252 REG 253 REG 254 REG 255 14/85 STACK LEVEL 2 STACK LEVEL 1 ST52T430/E430 ST52T430/E430 Table 2.2 Input Registers IR MNEMONIC NAME PERIPHERAL REGISTER ADDRESS STACK_POINTER STACK POINTER 0 CHAN 0 A/D CHANNEL 0 1 CHAN 1 A/D CHANNEL 1 2 CHAN 2 A/D CHANNEL 2 3 CHAN 3 A/D CHANNEL 3 4 CHAN 4 A/D CHANNEL 4 5 CHAN 5 A/D CHANNEL 5 6 CHAN 6 A/D CHANNEL 6 7 CHAN 7 A/D CHANNEL 7 8 PORT_A PORT A INPUT REGISTER 9 PORT_B PORT B INPUT REGISTER 10 PORT_C PORT C INPUT REGISTER 11 PWM_ 0_COUNT PWM/TIMER 0 COUNTER 12 PWM_ 0_ STATUS PWM/TIMER 0 STATUS REGISTER 13 PWM_ 1_ COUNT PWM/TIMER 1 COUNTER 14 PWM_ 1_ STATUS PWM/TIMER 1 STATUS REGISTER 15 PWM_ 2_ COUNT PWM/TIMER 2 COUNTER 16 PWM_ 2_ STATUS PWM/TIMER 2 STATUS REGISTER 17 SCI_RX SCI DATA REGISTER 18 SCI_STATUS SCI STATUS REGISTER 19 2.3.3 Configuration Registers. The ST52x430 configuration Registers allow the configuration of all the blocks of the fuzzy microcontroller. Table 2.3 describes the functions and the related peripherals of each of the Configuration Registers. By using the load instructions, the Configuration Registers can be set by using values stored in the Program Memory (EPROM) or in RAM. Use and meaning of each register will be described in further details in the corresponding section. Table 2.3 Configuration Registers CONFIGURATION REGISTER PERIPHERAL DESCRIPTION REG_CONF 0 INTERRUPT MASK Interrupts mask setting REG_CONF 1 N.U. N.U. REG_CONF 2 WATCHDOG TIMER Watchdog Timer Configuration REG_CONF 3 A/D CONVERTER A/D configuration 15/85 ST52T430/E430 ST52T430/E430 Table 2.3 Configuration Registers (continued) CONFIGURATION REGISTER PERIPHERAL DESCRIPTION REG_CONF 4 PORT A Set the relative bit like digital input or digital output REG_CONF 5 PWM/TIMER 0 PWM/Timer 0 Working mode Configuration REG_CONF 6 PWM/TIMER 0 PWM/TIMER 0 Prescaler configuration and output waveform selection. REG_CONF 7 PWM/TIMER 0 PWM/TIMER 0 Working Mode Configuration REG_CONF 8 PWM/TIMER 1 PWM/TIMER 1 Working Mode Configuration REG_CONF 9 PWM/TIMER 1 PWM/TIMER 1 Prescaler configuration and output waveform selection. REG_CONF 10 PWM/TIMER 2 PWM/TIMER 2 Working Mode Configuration REG_CONF 11 PWM/TIMER 2 PWM/Timer 2 Prescaler configuration and output waveform selection. REG_CONF 12 PORT A Set the bit 0,1 and 2 like Digital I/O or complementary Timers Output. REG_CONF 13 PORT B Set the relative bit like digital input or digital output. REG_CONF 14 PORT B Set the relative I/O like Digital or Analog. REG_CONF 15 PORT C Set the relative I/O like digital input or digital output REG_CONF 16 PORT C Set the relative I/O like Digital I/O or Timers Output REG_CONF 17 Interrupt Priority Set the Interrupts priority REG_CONF 18 Interrupt Priority Set the Interrupts priority REG_CONF 19 SCI Set the SCI working mode REG_CONF 20 SCI Set the SCI working mode 2.3.4 Output Registers. The Output Registers (OR) consist of 10 registers containing data for the microcontroller peripherals including the I/O Ports. All registers can be specified by using a decimal address (for example, 1 identifies the second OR). By using LOAD instructions the Output Registers (OR) may be set by using values stored in the Program Memory (LDPE) or in RAM (LDPR) The assembler instruction: LDPR OR_i RAM_Reg. 16/85 loads the value of the RAM location identified by the address RAM_Reg in the OR i-th Table 2.4 describes OR. In order to simplify the concept, a mnemonic name is assigned to OR. The same names are used in FUZZYSTUDIOTM 4.0 development tools. Use and meaning of each register will be described in further details in the corresponding section. ST52T430/E430 ST52T430/E430 Table 2.4 Output Registers OR MNEMONIC NAME PERIPHERAL REGISTER ADDRESS PORT_ A PORT A OR 0 PORT_ B PORT B OR 1 PORT_C PORT C OR 2 PWM_0_COUNT TIMER/PWM 0 COUNTER 3 PWM_0_RELOAD TIMER/PWM 0 RELOAD REGISTER 4 PWM_1_COUNT TIMER/PWM 1 COUNTER 5 PWM_1_RELOAD TIMER/PWM 1 RELOAD REGISTER 6 PWM_ 2_ COUNT TIMER/PWM 2 COUNTER 7 PWM_2_RELOAD TIMER/PWM 2 RELOAD REGISTER 8 SCI_TX_DATA SCI DATA REGISTER 9 2.4 Arithmetic Logic Unit The 8-bit Arithmetic Logic Unit (ALU) allows the performance of arithmetic calculations and logic instructions, which can be divided into 5 groups: Load, Arithmetic, Jump, Interrupts and Program Control instructions (refer to the ST52x430 Assembler Set for further details). The computational time required for each instruction consists of one clock pulse for each Cycle plus 3 clock pulses for the decoding phase. The ALU of the ST52x430 can perform multiplication (MULT) and division (DIV). Multiplication is performed by using 8 bit operands storing the result in 2 registers (16 bit values), see Figure 2.5 and Figure 2.6. WARNING: If the LSB of the multiplication result is 0, the Zero flag is set although the result is not 0. Table 2.5 Load instructions Load Instructions Mnemonic Instruction Bytes Cycles Z S C LDCE LDCE conf, EPROM 3 17 - - - LDCR LDCR conf, RAM 3 14 - - - LDFR LDFR FUZZY_i_RAM RAM 3 14 - - - LDPE LDPE per, EPROM 3 17 - - - LDPE LDPE per, (RAM) 3 17 - - - LDPR LDPR reg, RAM 3 14 - - - LDRC LDRC RAM, const 3 14 - - - LDRE LDRE RAMi, EPROMi 3 16 - - - LDRE LDRE (RAMi), (RAMj) 3 18 - - - LDRI LDRI RAM, inp_reg 3 15 - - - LDRR LDRR RAMi, RAMj 3 16 - - - 17/85 ST52T430/E430 ST52T430/E430 Table 2.5 Load instructions PGSET PGSET const 2 9 - - - Table 2.6 Arithmetic & Logic instructions set Arithmetic Instructions Mnemonic Instruction Bytes Cycles Z S C ADD ADD regi, regj 3 17 I - I ADDO ADDO regi, regj 3 20 I I I AND AND regi, regj 3 17 I - - ASL ASL regi 2 15 I - I ASR ASR regi 2 15 I I - DEC DEC regi 2 15 I I - DIV DIV regi, regj 3 26 I I I INC INC regi 2 15 I - I MULT MULT regi, regj 3 19 I - - NOT NOT regi 2 15 I - - OR OR regi, regj 3 17 I - - SUB SUB regi, regj 3 17 I I - SUBO SUBO regi, regj 3 20 I I I MIRROR MIRROR regi 2 15 I - - Table 2.7 Jump Instruction Set Jump instructions mnemonic instruction bytes cycles z s c call call addr 3 18 - - - jp jp addr 3 12 - - - jpc jpc addr 3 10/12 - - - jpnc jpnc addr 3 10/12 - - - jpns jpns addr 3 10/12 - - - jpnz jpnz addr 3 10/12 - - - jps jps addr 3 10/12 - - - jpz jpz addr 3 10/12 - - - ret ret 1 13 - - - Table 2.8 Interrupt Instructions Set Interrupt Instructions Mnemonic Bytes Cycles Z S C HALT HALT 1 7/15 - - - MEGI 18/85 Instruction MEGI 1 7/15 - - - ST52T430/E430 ST52T430/E430 Table 2.8 Interrupt Instructions Set (continued) MDGI MDGI 1 6 - - - RETI RETI 1 12 - - - RINT RINT INT 2 8 - - - UDGI UDGI 1 6 - - - UEGI UEGI 1 7/15 - - - WAITI WAITI 1 7/14 - - - Table 2.9 Control Instructions Set Control Instructions Mnemonic Instruction Bytes Cycles Z S C FUZZY FUZZY 1 5 - - - NOP NOP 1 6 - - - WDTRFR WDTRFR 1 7 - - - WDTSLP WDTSLP 1 6 - - - Notes: I affected - not affected Figure 2.5 Multiplication Figure 2.6 Division RAM RAM 0 0 1 1 2 2 i-1 i i i+1 j-1 j-1 j j+1 j j+1 253 253 254 254 255 REG. j REG. j+1 255 : REG. i REG. j X REG. i 16 Bit REMAINDER QUOTIENT LSB MSB 19/85 ST52T430/E430 ST52T430/E430 3 EPROM EPROM memory provides an on-chip userprogrammable non-volatile memory, which allows fast and reliable storage of user data. EPROM memory can be locked by the user. In fact, a memory location called Lock Cell is devoted to lock EPROM and avoid external operations. A software identification code, called ID CODE, distinguishes which software version is stored in the memory. 64 kbits of memory space with an 8-bit internal parallelism (up to 8 kbytes) addressed by an 13-bit bus are available. The data bus is 8 bits. Memory has a double supply: VPP is equal to 12V±5% in Programming Phase or to VSS during Working Phase. VDD is equal to 5V±10%. ST52x430 EPROM memory is divided into three main blocks (see Figure ): I Interrupt Vectors memory block (3 through 20) contains the addresses for the interrupt routines. Each address is composed of three bytes. I Mbfs Setting memory block (21 through MemAdd) contains the coordinates of the vertexes of every Mbf defined in the program. I The maximum value of MemAdd is 1023. This area is dynamically assigned according to the size of the fuzzy routines. The unused memory area, if any, is assigned to the Program Instruction Set memory block. I The Program Instructions Set memory block (MemAdd through MemAddx) contains the instruction set of the user program. The following table summarizes the values of Mem Addx for the different devices Table 3.1 Mem Addx ST52T430K2 ST52T430K2 ST52T430K3 ST52T430K3 4095 8191 Mem Addx Locations 0, 1 and 2 contain the address of the first microcode instruction.The operations that can be performed on EPROM during the Programming Phase are: Stand By, Memory Writing, Reading and Verify/Margin Mode, Memory Lock, IDCode Writing and Verify. Figure 3.1 Program Memory Organization 8191 ST52430K3 ST52430K3 4095 ST52430K2 ST52430K2 ST52430K1 ST52430K1 2047 Fuzzy and Boolean Algorithms MemAdd+1 MemAdd Mbfs Parameters 21 20 3 2 0 20/85 INT_EXT INT_SCI INT_TIMER/PWM2 INT_TIMER/PWM1 INT_TIMER/PWM0 INT_ADC Program Instruction First Address Program Instruction Set Mbfs Setting and Program Instruction Set Interrupt Vectors ST52T430/E430 ST52T430/E430 Table 3.2 EPROM Control Register OPERATION REGISTER VALUE Stand By 0 Memory Reading/Verify 1 Memory Unlock and Lock Status Reading 2 Memory Writing 3 Memory Lock 4 ID CODE Writing 5 Memory Lock Status Reading/Verify 9 ID CODE Reading/ Verify 10 Figure 3.2 Eprom Programming Timing The operations above are managed by using the internal 4-bit EPROM Control Register. The reading phase is executed with VPP= 5V±5%, while the verify/Margin Mode phase needs VPP= 12V±5%. The Blank Check must be a reading operation with VPP= 5V±5%. Table 3.2 illustrates EPROM Control Register codes used to identify the operation running. 3.1 EPROM Programming Phase Procedure The Programming mode is selected by applying 12V±5% voltage or 5V±5% voltage to the VPP pin and setting the control signal as following: RESET =Vss TEST =Vss If the VPP voltage is 5V±5% only reading may be performed. RST_ADD, INC_ADD, RST_CONF, INC_CONF and PHASE are the control signals used during the Programming Mode. PHASE, RST_CONF and RST_ADD signals are active on level, the others are active on rising edge. VALID DATA DATA OUT PA(0:7) VALID DATA DATA IN VALID DATA DATA OUT DATA OUT RST_ADD RST_CONF INC_ADD INC_CONF PHASE 100nS MEMORY UNLOCK 10µS MEMORY WRITING LOCATION ADDRESS =1 MEMORY VERIFY MARGIN MODE 21/85 ST52T430/E430 ST52T430/E430 PHASE and RST_ADD signals are active low, RST_CONF signal is active high. Port A is used for the memory data I/O. (See Table 3.2 for pin reference on the different packages). Memory may be locked by means of the Memory Lock Status, which is a flag used to enable EPROM operations. If Memory Lock Status is 1 all EPROM operations are enabled, otherwise the user may only read (and verify) the OTP code and the Memory Lock Status. Only if EPROM is not locked by means of Lock Cell (see EPROM Locking may EPROM operations be enabled by changing the Memory Lock Status from 0 to 1. RST_ADD signal resets the memory address register and the Memory Lock Status. When the RST_ADD becomes high, the memory must be unlocked in order to read or write. INC_ADD signal increments the memory address. RST_CONF signal resets the EPROM Control Register. When RST_CONF is high, the DATA I/ O Port A is in output, otherwise it is always in input. INC_CONF signal increments the EPROM Control Register value. PHASE signal validates the operation selected by means of the EPROM Control Register value. 3.1.1 EPROM Operation. In order to execute an EPROM operation (See Table 3.2), the corresponding identification value must be loaded in the EPROM Control Register. The signal timing is the following: RST_ADD= high and PHASE= high, RST_CONF changes from low to high level, to reset the EPROM Control Register, and INC_CONF signal generates a number of positive pulses equal to the value to be loaded. After this sequence, a negative pulse of the PHASE signal will validate the operation selected. The minimum PHASE signal pulse width must be 10 µs for EPROM Writing Operation and 100 ns for the others. When RST_CONF is high, DATA I/O Port A is enabled in output and the reading/verifying operation results are available. After a writing operation, when RST_CONF is high, Port A is in output without valid data. 22/85 3.1.2 EPROM Locking. The Memory Lock operation, which is identified with the number 4 in the EPROM Control Register, writes "0" in the Memory Lock Cell. At the beginning of an External Operation, when the RST_ADD signal changes from low level to high level, the Memory Lock Status is "0", therefore it must be unlocked before proceeding. In order to unlock the Memory Lock Status the operation, which is identified by the number 2 in the EPROM Control Register must be executed (see Figure 3.2). Memory Lock Status can be changed only if Memory Lock Cell is "1". After a Memory Lock operation external operations cannot be executed except to read (or verify) the OTP Code and the Memory Lock Status. 3.1.3 EPROM Writing. When the memory is blank, all bits are at logic level "1". Data is introduced by programming only the zeros in the desired memory location. However, all input data must contain both "1" and "0". The only way to change "0" into "1" is to erase the entire memory (by exposure to Ultra Violet light) and reprogram it. The memory is in Writing mode when the EPROM Control Register value is 3. The VPP voltage must be 12V±5%, with stable data on the data bus PA(0:7). The timing signals are the following (see Figure ): 1) RST_ADD and RST_CONF change from low to high level, 2) two pulses on INC_CONF signal load the Memory Unlock operation code, 3) a negative pulse (100 ns) on the PHASE signal validates the Memory Unlock operation, 4) a negative pulse on RST_CONF signal resets the EPROM Control Register, 5) three positive pulses on INC_CONF load the Memory Writing operation code, 6) a train of positive pulses on INC_ADD signal increments the memory location address up to the requested value (generally this is a sequential operation and only one pulse is used), 7) a negative pulse (10 µs) on the PHASE signal validates the Memory Writing operation. ST52T430/E430 ST52T430/E430 3.1.4 EPROM Read/Verify Margin Mode. The read phase is executed with VPP= 5V±5%, instead of the verify phase that needs VPP= 12V±5%. The Memory Verify operation is available in order to verify the accuracy of the data written. A Memory Verify Margin Mode operation can be executed immediately after writing each byte, in this case (see Figure ): 1) a positive pulse on RST_CONF signal resets the EPROM Control Register, if it wasn't already reset; 2) one positive pulse on INC_CONF loads the Memory Read/Verify operation code; 3) a negative pulse (100 ns) on the PHASE signal validates the Memory Reading / Verify operation; 4) a negative pulse on RST_CONF signal puts in the PA(0:7) port the value stored in the actual memory address and resets the EPROM Control Register; If an error occurred writing, the user has to repeat EPROM writing. 3.1.5 Stand by Mode. EPROM has a standby mode, which reduces the active current from 10mA (Programming mode) to less than 100 µA. Memory is placed in standby mode by setting the PHASE signal at a high level or when the EPROM Control Register value is 0 and the PHASE signal is low. 3.1.6 ID code. A software identification code, called ID code may be written in order to distinguish which software version is stored in the memory. 64 Bytes are dedicated to store this code by using the address values from 0 to 63. The ID Code may be read or verified even if the Memory Lock Status is "0". The timing signals are the same as that of a normal operation. 3.2 Eprom Erasure The transparent window available in the CSDIP32W CSDIP32W package, allows the memory contents to be erased by exposure to UV light. Erasure begins when the device is exposed to light with a wavelength shorter than 4000Å. Sunlight, as well as some types of artificial light, includes wavelengths in the 3000-4000Å range which, on prolonged exposure can cause erasure of memory contents. Therefore, it is recommended that EPROM devices be fitted with an opaque label over the window area in order to prevent unintentional erasure. The erasure procedure recommended for EPROM devices consists of exposure to short wave UV light having a wavelength of 2537Å. The minimum integrated dose recommended (intensity x exposure time) for complete erasure is 15Wsec/cm 2. This is equivalent to an erasure time of 15-20 minutes using a UV source having an intensity of 12mW/cm 2 at a distance of 25mm (1 inch) from the device window. 23/85 ST52T430/E430 ST52T430/E430 4 INTERRUPTS The Control Unit (CU) responds to peripheral events and external events via its interrupt channels. When such an events occur, if the related interrupt is not masked and according to a priority order, the current program execution can be suspended to allow the CU to execute a specific response routine. Each interrupt is associated with an interrupt vector that contains the memory address of the related interrupt service routine. Each vector is located in the Program Space (EPROM Memory) at a fixed address (see Interrupt Vectors Table 4.2). 4.1 Interrupt Operation If there are pending interrupts at the end of an arithmetic or logic instruction, the one with the highest priority is passed. Passing an interrupt means storing the arithmetic flags and the current PC in the stack and executing the associated Interrupt routine, whose address is located in three bytes of the EPROM memory location between address 3 and 20. The Interrupt routine is performed as a normal code, checking if a higher priority interrupt has to be passed at the end of each instruction. An Interrupt request with the higher priority stops the lower priority Interrupt. The Program Counter and the arithmetic flags are stored in the stack. With the RETI (Return from Interrupt) instruction the arithmetic flags and Program Counter (PC) are restored from the top of the stack. This stack was already described in section RAM and STACK. An Interrupt request cannot stop processing of the fuzzy rule, but this is passed only after the end of a fuzzy rule or at the end of a logic, or arithmetic instruction. NOTE1: A fuzzy routine can only be interrupted in the Main program. However, if the fuzzy routine in the main is interrupted by an Interrupt routine containing another fuzzy routine, the internal fuzzy registers used for the first are modified with results of the latter routine. NOTE2: It is recommended not to interrupt a Fuzzy function contained in an Interrupt routine. In order to use a Fuzzy function inside an interrupt routine, the user MUST include the Fuzzy function between an UDGI (MDGI) instruction and an UEGI (MEGI) instruction (see the following paragraphs). 24/85 Figure 4.1 Interrupt Flow NO AL RM PRO RAM G FLO W INTERRUPT SERVICE RO UTINE INTERRUPT RETI INSTRUCTIO N Figure 4.2 Interrupt Vectors mapping 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 INT_ADC INT_TIMER/PWM0 INT_TIMER/PWM1 INT_TIMER/PWM2 INTERRUPT VECTORS INT_SCI INT_EXT Figure 4.3 Global Interrupt Request generation Global Interrupt Pending User Global Interrupt Mask Macro Global Global Interrupt Request ST52T430/E430 ST52T430/E430 4.2 Global Interrupt Request Enabling When an Interrupt occurs, it generates a Global Interrupt Pending (GIP), that can be masked by software. After a GIP a Global Interrupt Request (GIR) will be generated and Interrupt service routine associated to the interrupt with higher priority will start. In order to avoid possible conflicts between interrupt masking set in the main program, or inside high level language compiler macros, the GIP is hung up through the User Global Interrupt Mask or the Macro Global Interrupt Mask (see Figure 4.2). UEGI/UDGI instruction switches on/off the User Global Interrupt Mask, enabling/disabling the GIR for the main program. MEGI/MDGI instructions switch the Macro Global Interrupt Mask on/off, in order to ensure that the macro will not be broken. Table 4.1 Configuration Register 0 Description the result is CONF_REG0 =00000110 enabling the interrupts deriving from the ADC (INT_ADC) and from the PWM/TIMER 0 (INT_PWM/TIMER0). PWM/TIMER 1 Interrupt Not Masked 0 PWM/TIMER 2 Interrupt Masked PWM/TIMER 2 Interrupt Not Masked 0 SCI Interrupt Masked 1 SCI Interrupt Not Masked 0 External Interrupt Polarity Active on Rising 1 7 PWM/TIMER 1 Interrupt Masked 1 6 PWM/TIMER 0 Interrupt Not Masked 0 5 PWM/TIMER 0Interrupt Masked 1 4.4 Interrupt Maskability The interrupts can be masked by configuring the REG_CONF 0 by means of LDCR, or LDCE, instruction. The interrupt is enabled when the bit associated to the mask interrupt is "1". Viceversa, when the bit is "0", the interrupt is masked and is kept pendent. For example: LDRC 10,6 //load the constant 6 in the RAM Register 10 LDCR 0, 10 // set the CONF_REG 0 with the value stored in the RAM Register 10 A/D Converter Interrupt Not Masked 1 4 A/D Converter Interrupt Masked 1 3 External Interrupt Not Masked 0 2 External Interrupt Masked 1 1 Description 0 0 Name Value 0 4.3 Interrupt Sources ST52x430 manages interrupt signals generated by the internal peripherals (PWM/Timers, UART and Analog to Digital Converter) or coming from the INT/PC0 pin. The External Interrupt can be programmed to be active on the rising or falling edge of INT/PC0 signal by setting the PEXTINT bit of the Configuration Register to 0. WARNING: Changing the interrupt priority inside an interrupt service routine can cause unwanted interrupt requests. Each peripheral can be programmed in order to generate the associated interrupt; further details are described in the related chapter. Bit External Interrupt Polarity Active on Falling MSKE MSKAD MSKTM0 MSKTM1 MSKTM2 MSCI PEXTINT Not used Reset Configuration `000000' 25/85 ST52T430/E430 ST52T430/E430 Table 4.2 Interrupts Description Priority Peripheral Code Maskable EPROM Locations Int Programmable 000 yes 3-5 PWM/TIMER 0 Int Programmable 001 yes 6-8 INT_PWM/ TIMER1 PWM/TIMER 1 Int Programmable 010 yes 9-11 INT_PWM/ TIMER2 PWM/TIMER 2 Int Programmable 011 yes 12-14 INT_SCI SCI Int Programmable 100 yes 15-17 INT_EXT External Interrupt (INT) Ext Highest - yes 18-20 Name Description INT_ADC ADC INT_PWM/ TIMER0 Figure 4.4 Interrupt Configuration Register 0 REG_CONF0 Interrupts Mask D7 D6 D5 D4 D3 D2 D1 D0 MSKE: Ext. Int. MSKAD: A/D Int. MSKTM0: Timer0 Int. MSKTM1: Timer1 Int. MSKTM2: Timer2 Int. MSCI: SCI Int. PEXTINT: Ext. Int. Polariry Not Used 26/85 ST52T430/E430 ST52T430/E430 Figure 4.5 Interrupt Configuration Register 17 & 18 Interrupts Priority REG_CONF17 CONF17 REG_CONF18 CONF18 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 INT 1 INT 2 INT 3 INT 4 INT 5 Not Used 4.5 Interrupt Priority Seven priority levels are available: level 6 has the lowest priority, level 0 has the highest priority. Level 6 is associated to the Main Program, levels 5 to 1 are programmable by means of the priority registers called REG_CONF17 CONF17 and REG_CONF18 CONF18 (see Figure 4.5 and Table 4.3); whereas the higher level is related to the external interrupt (INT_EXT). PWM/Timers, UART and ADC are identified by a three-bit Peripheral Codes (see Table 4.2); in order to set the i-th priority level the user must write the peripheral label i in the related INTi priority level. i.e. LDRC 10, 193 //(load the value 193='11000001' in the RAM Register 10) LDRC 11, 168 //(load the value 168='10101000' in the RAM Register 11) LDCR 17, 10 // set the REG_CONF17 CONF17= `11000001' LDCR 18, 11 // set the REG_CONF18 CONF18= `10101000' The following priority levels are defined: I Level 1: INT_PWM/TIMER0 (PWM/TIMER 0 Code: 001) I Level 2: INT_ADC (ADC Code: 000) Table 4.3 Conf. Register 17 & 18 Description Bit Name Value Level 0, 1,2 INT1 Periphera l Code High 3, 4,5 INT2 Periphera l Code Medium-High 6,7,8 INT3 Periphera l Code Medium-Low 9,10,11 INT4 Periphera l Code Low 12,13,1 4 INT5 Periphera l Code Very Low I Level 3: Int_PWM/Timer2 (PWM/TIMER 2 Code: 011) I Level 4: INT_UART (UART Code: 100) I Level 5: INT_PWM/TIMER1 (PWM/TIMER 1 Code: 010) 27/85 ST52T430/E430 ST52T430/E430 Figure 4.6 Example of a sequence of Interrupt requests INT2 INT0 INT4 INT1 INT3 PRIORITY LEVEL 0 INT0 1 INT1 2 INT2 INT2 3 INT2 INT3 4 INT4 5 6 MAIN PROGRAM Note: The Interrupt priority must be fixed at the beginning of the main program, because at the RESET REG_CONF17 CONF17='00000000' & REG_CONF18 CONF18='00000000', that could generate erroneous operations. During program execution the interrupt priority can only be modified, at main program level, with the following procedure: STEP 1: Mask the interrupts by means of a UDGI (or MDGI) instruction STEP 2: Change the REG_CONF 17 and REG_CONF18 CONF18 values to modify the interrupt priority STEP 3: Reset all the pending interrupt instructions by means of RINT instructions. STEP 4: Unmask the interrupts by means of a UEGI (or MEGI) instruction When a source provides an Interrupt request and the request processing is also enabled, the CU changes the normal sequential flow of a program by transferring program control to a selected service routine. 28/85 MAIN PROGRAM When an interrupt occurs the CU executes a JUMP instruction to the address loaded in the related location of the Interrupt Vector. When the execution returns to the original program it immediately begins following the instruction that was interrupted. Table 4.4 RINT Instruction code Peripheral Name Value A/D Converter 0 PWM/TIMER 0 1 PWM/TIMER 1 2 PWM/TIMER 2 3 SCI 4 External Interrupt 5 ST52T430/E430 ST52T430/E430 4.6 Interrupts and Low power mode All interrupts allow the processor to leave the WAIT low power mode. Only the external Interrupt allows the processor to leave the HALT low power mode. 4.7 Interrupt RESET An eventually pending interrupt can be reset with the instruction RINT j, which resets the interrupt j-th where j identifies the peripherals as described in the following table (see Table 4.4). The assembler instruction: RINT 2 Resets the PWM/Timer 1 interrupt. Note: The RINT command must be preceded from a UDGI (or MDGI) command and followed by a UEGI (or MEGI) command. WARNING: If an interrupt is reset, with the RINT instruction within its own interrupt routine, the priority level of the interrupt becomes the lowest and the routine can be immediately interrupted by a lower priority interrupt request. 29/85 ST52T430/E430 ST52T430/E430 5 CLOCK, RESET & POWER SAVING MODE 5.1 System Clock The ST52x430 Clock Generator module generates the internal clock for the internal Control Unit, ALU and on-chip peripherals and it is designed to require a minimum number of external components. The ST52x430 oscillator circuit generates an internal clock signal with the same period and phase as that of the OSCin input pin. The maximum frequency allowed is 20 Mhz. Note: When the SCI peripheral is used only a 5, 10, or 20 MHz system clock must be used. The system clock may be generated by using either a quartz crystal, ceramic resonator or an external clock. The different methods of the clock generator are illustrated in Figure 5.1. When an external clock is used, it must be connected on the OSCin pin, while OSCout can be floating. The crystal oscillator start-up time is a function of many variables: crystal parameters (especially Rs), oscillator load capacitance (CL), IC parameters, environment temperature, supply voltage. Figure 5.1 Oscillator Connections CRYSTAL CLOCK Note: The crystal or ceramic leads and circuit connections must be as short as possible. Typical values for CL1, CL2 are 10pF for a 20 MHz crystal. 5.2 RESET There are two Reset sources: - RESET pin (external source.) - WATCHDOG (internal source) When a Reset event happens, the user program restarts from the beginning. The Reset pin is an input. An internal reset does not affect this pin. A Reset signal originated by external sources is recognized instantaneously. The RESET pin may be used to ensure VDD has risen to a point where the MCU can operate correctly before the user program runs. In working mode Reset must be set to `1' (see Table 2.1). 5.3 Power Saving Mode There are two Power Saving modes: WAIT and HALT mode. These conditions may be entered using the WAIT or HALT instructions. 5.3.1 Wait Mode Wait mode places the MCU in low power consumption by stopping the CPU. All peripherals EXTERNAL CLOCK ST52X430 ST52X430 OSCin Cl1 10pF 30/85 ST52X430 ST52X430 OSCout Cl2 10pF OSCin CLOCK INPUT OSCout ST52T430/E430 ST52T430/E430 and the watchdog remain active. During WAIT mode, Interrupts are enabled. The MCU will remain in Wait mode until an Interrupt or a RESET occurs, whereupon the Program Counter jumps to the interrupt service routine or, if a RESET occurs, at the beginning of the user program. REMARK: In Wait mode the CPU clock does not stop. 5.3.2 Halt Mode Halt mode is MCU's lowest power consumption mode, which is entered by executing the HALT instruction. The internal oscillator is turned off, causing all internal processing to stop, including the operations of the on-chip peripherals. Figure 5.2 Reset Block Diagram Halt mode cannot be used when the watchdog is enabled. If the HALT instruction is executed while the watchdog system is enabled, it will be skipped without modifying the normal CPU operations. The ICU can exit Halt mode after an external interrupt or reset. The oscillator is then turned on and stabilization time is provided before restarting CPU operations. Stabilization time is 4096 CPU clock cycles after the interrupt and 1.000.000 after the Reset. After the start up delay, the CPU restarts operations by serving the external interrupt routine. Reset makes the ICU exit from HALT mode and restart, after the delay, from the beginning of the user program after the delay. Warning: if the External Interrupt is disabled, the ICU exits from the Halt mode and jumps to the lower priority interrupt routine. Figure 5.4 WAIT Flow Chart RESET INTERNAL RESET WATCHDOG RESET Figure 5.3 Simple Reset Circuit Vcc 100 F 10k RESET 2.2k 2.2k 1 F 31/85 ST52T430/E430 ST52T430/E430 Figure 5.5 HALT Flow Chart HALT INSTRUCTION YES WATCHDOG ENABLED NO HALT INSTRUCTION SKIPPED OSCILLATOR PERIPHERALS CLOCK CPU CLOCK OFF OFF OFF NO NO RESET YES EXTERNAL INTERRUPT YES OSCILLATOR PERIPHERALS CLOCK CPU CLOCK ON ON ON OSCILLATOR PERIPHERALS CLOCK CPU CLOCK 4096 CPU CLOCK CYCLES DELAY 1000000 CPU CLOCK CYCLES DELAY RESET CPU AND RESTART USER PROGRAM NO RESTART PROGRAM SERVICING THE LOWER PRIORITY INTERRUPT ROUTINE 32/85 ON ON ON EXTERNAL INTERRUPT ENABLED YES RESTART PROGRAM SERVICING THE EXTERNAL INTERRUPT ROUTINE ST52T430/E430 ST52T430/E430 Each port is configured by using two configuration registers. The first is used to determine if a pin is an input or output, while the second defines the Alternate functions. 6 I/O PORTS 6.1 Introduction ST52x430 devices feature flexible individually programmable multi-functional input/output lines. Refer to the following figure for specific pin allocations. 23 I/O lines, grouped in 3 different ports are available on the ST52x430: PORT A = 7 or 8-bit ports (PA0 - PA7 pins) PORT B = 7 or 8-bit ports (PB0 - PB7 pins) PORT C = 8-bit port (PC0 - PC7 pins) PIN 24 in the SO34 or PIN 22 in the PDIP32 PDIP32 can be configured to belong to port A or to port B. These I/O lines can be programmed to provide digital input/output and analog input, or to connect input/output signals to the on-chip peripherals as alternate pin functions. Input buffers are TTL compatible with Schmitt trigger in port A and C while port B is CMOS compatible without Schmitt trigger. The output buffer can supply up to 8 mA. The port cannot be configured to be used contemporaneously as input and output. 6.2 Input Mode The input configuration is selected by setting the corresponding configuration register bit to "1" (REG_CONF 4, 13 and 15) (see paragraph I/O Port Configuration Registers). The ports are configured by using the configuration registers illustrated in the following table. . Table 6.1 I/O Port Configuration Registers. PORT A PORT B PORT C Reg_Conf 4 Reg_Conf 13 Reg_Conf 15 Digital input data is automatically stored in the Input Registers, but it cannot be read directly. In order to read a single bit of the IR its value must be copied in a RAM location. Digital data is stored in a RAM location by using the assembler instruction: LDRI RAM_Reg Input_i Figure 6.1 Ports A & C Functional Blocks TO INPUT REGISTER and PERIPHERALS TTL PORT A PIN or PORT C PIN FROM PERIPHERAL FROM OUTPUT REGISTER FROM CONFIGURATION REGISTER FROM CONFIGURATION REGISTER 33/85 ST52T430/E430 ST52T430/E430 Figure 6.2 Port B Functional Blocks FROM CONFIGURATION REGISTER CMOS TO INPUT REGISTER PORT B PIN TO A/D CONVERTER FROM OUTPUT REGISTERS FROM CONFIGURATION REGISTER Table 6.2 Input Register and I/O Ports PORT A PORT B PORT C IR 9 IR 10 IR 11 6.3 Output Mode The output configuration is selected by setting the corresponding configuration register bit to "0" (REG_CONF 4, 13 and 15) (see paragraph I/O Port Configuration Registers). Digital data is transferred to the related I/O Port by means of the Output register via the assembler instructions LDPE or LDPR. Table 6.3 Output Register and I/O Ports PORT A PORT B PORT C OR 0 OR 1 OR 2 34/85 6.4 Alternate Functions Several ST52x430 pins are configurable to be used with different functions (see Table 1.1). When an on-chip peripheral is configured to use a pin, the correct I/O mode of the related pin must be selected. For example: if pin 26 (PA5/T0CLK in the SO34) has to be used as an external PWM/Timer0 clock, the Reg_Conf 4(5) bit must be set to `1'. When the signal is an on-chip peripheral input the related I/O pin has to be configured in Input Mode. When a pin is used as an A/D Converter input the related I/O pin is automatically set in tristate. The analog multiplexer (controlled by the A/D configuration Register) switches the analog voltage present on the selected pin to the common analog rail, which is connected to the ADC input. It is recommended that the voltage level not be changed or that any port pins not be loaded while conversion is running. Furthermore, it is recommended that clocking pins not be located close to a selected analog pin. 6.5 I/O Port Configuration Registers The I/O mode for each bit of the three ports is selected by using the Configuration Registers 4, ST52T430/E430 ST52T430/E430 13 and 15 (See Table 6.1) The structure of these registers is illustrated in the following tables. Each bit of the configuration registers determines the I/O mode of the related port pin. Table 6.5 Ports B REG_CONF 13 Bit Name Bit Value Description 0 0 Name 1 0 1 D1 1 0 2 D2 1 0 3 D3 1 0 4 D4 1 0 5 D5 1 Set the pin PA0/T0RES in Input Mode 0 0 0 0 0 0 6 D6 1 Set the pin PA6 in Input Mode 0 0 1 7 Set the pin PB7/PA7/ Ain7 in Output Mode Set the pin PB7/PA7/ Ain7 in Output Mode 1 7 Set the pin PB6/Ain6 in Input Mode Set the pin PB7/PA7/ Ain7 in Input Mode D6 Set the pin PA6 in Output Mode 0 Set the pin PB6/Ain6 in Output Mode 1 6 Set the pin PB5/Ain5 in Input Mode D5 Set the pin PA5/T0CLK in Output Mode Set the pin PA5/T0CLK in Input Mode Set the pin PB5/Ain5 in Output Mode 1 5 Set the pin PB4/Ain4 in Input Mode D4 Set the pin PA4/T0STRT in Output Mode Set the pin PA4/T0STRT in Input Mode Set the pin PB4/Ain4 in Output Mode 1 4 Set the pin PB3/Ain3 in Input Mode D3 Set the pin PA3/T2OUT in Output Mode Set the pin PA3/T2OUT in Input Mode Set the pin PB3/Ain3 in Output Mode 1 3 Set the pin PB2/Ain2 in Input Mode D2 Set the pin PA2/T1OUT in Output Mode Set the pin PA2/T1OUT in Input Mode Set the pin PB2/Ain2 in Output Mode 1 2 Set the pin PB1/Ain1 in Input Mode D1 Set the pin PA1/T0OUT in Output Mode Set the pin PA1/T0OUT in Input Mode Set the pin PB1/Ain1 in Output Mode 1 1 Set the pin PB0/Ain0 in Input Mode D0 Set the pin PA0/T0RES in Output Mode D0 Set the pin PB0/Ain0 in Output Mode 1 0 Description 0 Table 6.4 Ports A REG_CONF 4 Value D7 Set the pin PB7/PA7/ Ain7 in Input Mode D7 Reset Configuration `11111111' Reset Configuration `11111111' 35/85 ST52T430/E430 ST52T430/E430 Table 6.6 Port C REG_CONF 15 Bit Value Description 0 Set the pin INT/PC0 in Output Mode 1 0 Name Set the pin INT/PC0 in Input Mode Table 6.7 Analog Inputs (REG_CONF 14) D0 0 Set the pin T0OUT/ PC1 in Output Mode 1 Set the pin T0OUT/ PC1 in Input Mode 0 1 Analog Input Option. The PB0-PB7 pins can be configured to be analog inputs according to the codes programmed in the configuration register REG_CONF 14 (See Table 6.7). These analog inputs are connected to the on-chip 8-bit Analog to Digital Converter. Bit Name Value Description 0 D0 0 pin PB0/Ain0 Digital I/O 1 pin PB0/Ain0 Analog 0 pin PB1/Ain1 Digital I/O 1 pin PB1/Ain1 Analog 0 pin PB2/Ain2 Digital I/O Set the pin T1OUT/ PC2 in Output Mode D1 1 2 2 1 Set the pin T1OUT/ PC2 in Input Mode D2 1 3 D2 D1 D3 pin PB2/Ain2 Analog 0 pin PB3/Ain3 Digital I/O 1 4 D4 pin PB3/Ain3 Analog 0 pin PB4/Ain4 Digital I/O 1 0 3 Set the pin T2OUT/ PC3 in Output Mode Set the pin T2OUT/ PC3 in Input Mode Set the pin Tx/PC4 in Input Mode 0 Set the pin Rx/PC5 in Output Mode 1 Set the pin Rx/PC5 in Input Mode 0 Set the pin PC6 in Output Mode 1 Set the pin PC6 in Input Mode 0 Set the pin PC7 in Output Mode 1 7 Set the pin Tx/PC4 in Output Mode 1 6 Set the pin PC7 in Input Mode D4 6 D6 pin PB5/Ain5 Analog 0 pin PB6/Ain6 Digital I/O 1 7 pin PB7/Ain7 Digital I/O 1 D7 pin PB6/Ain6 Analog 0 pin PB7/Ain7 Analog Reset Configuration `11111111' D5 D6 D7 Reset Configuration `11111111' 36/85 pin PB5/Ain5 Digital I/O 1 0 5 D5 D3 1 4 5 pin PB4/Ain4 Analog 0 ST52T430/E430 ST52T430/E430 PWM/Timers Alternate Functions The pins of Port A and C can be configured to be I/ O of the three PWM/Timers available on the ST52x430. The configuration of these pins is performed by using the Configuration Registers REG_CONF 12 and REG_CONF 16 if the related pin has to be output. When the related pin has to be used as an input peripheral the configuration is performed by the relative peripheral configuration registers (See PWM/Timer Session). Table 6.9 PWM/Timers REG_CONF 12 Bit Value 0 1 0 0 Pin T1OUT/PC2 is configured as PWM/ Timer 1 output T1OUT 1 Pin T2OUT/PC3 is configured as PWM/ Timer 2 output T2OUT 1 0 Pin Tx/PC4 is configured as SCI output Tx X NC PORT A bits = 7 x Not Used Not Used PC4 4-7 PORT A bits = 8 PA3 Pin Tx/PC4 is configured as Port C Digital I/O PC3 3 Pin PA3/T2OUT is configured as Port A Digital I/O 0 2 PA2 Pin T2OUT/PC3 is configured as Port C Digital I/O 0 2 Pin PA3/T2OUT is configured as PWM/Timer 2 complementary output 1 PinT1OUT/PC2 is configured as Port C Digital I/O 1 PC2 Pin PA2/T1OUT is configured as Port A Digital I/O 1 Pin T0OUT/PC1 is configured as PWM/ Timer 0 output T0OUT 1 1 Pin PA2/T1OUT is configured as PWM/Timer 1 complementary output 0 Pin T0OUT/PC1 is configured as Port C Digital I/O PC1 Pin PA1/T0OUT is configured as Port A Digital I/O Description 1 0 Pin PA1/T0OUT is configured as PWM/Timer 0 complementary output 0 Name Description PA1 Table 6.8 PWM/Timers REG_CONF 16 Bit Value 1 0 Name 3 4-7 PASZ NC Reset Configuration `0000' Reset Configuration `1111' 37/85 ST52T430/E430 ST52T430/E430 Figure 6.3 Configuration Register 12 REG_CONF 12 DIGITAL PORT D7 D6 D5 D4 D3 D2 D1 D0 PA1T: Pin PA1/T0OUT setting PA2T: Pin PA2/T1OUT setting PA3T: Pin PA3/T2OUT setting PA78: PORT A size not used Figure 6.4 Configuration Register 16 REG_CONF 16 DIGITAL PORT D7 D6 D5 D4 D3 D2 D1 D0 P6SL: Pin T0OUT/PC1setting P7SL: Pin T1OUT/PC2 setting P8SL: Pin T2OUT/PC3 setting P9SL: Pin Tx/PC4 setting not used 38/85 ST52T430/E430 ST52T430/E430 Figure 7.2 Alpha Weight Calculation 7 FUZZY COMPUTATION (DP) The ST52T430/E430 ST52T430/E430 Decision Processor (DP) main features are: I Up to 8 Inputs with 8-bit resolution; I 1 Kbyte of Program/Data Memory available to store more than 300 to Membership Functions (Mbfs) for each Input; I Up to 128 Outputs with 8-bit resolution; I Possibility of processing fuzzy rules with an UNLIMITED number of antecedents; I j-th Mbf 1 UNLIMITED number of Rules and Fuzzy Blocks. The limits on the number of Fuzzy Rules and Fuzzy program blocks are only related to the Program/Data Memory size. 7.1 Fuzzy Inference The block diagram shown in Figure 7.1 describes the different steps performed during a Fuzzy algorithm. The ST52T430/E430 ST52T430/E430 Core allows for the implementation of a Mamdani type fuzzy inference with crisp consequents. Inputs for fuzzy inference are stored in 8 dedicated Fuzzy input registers. The LDFR instruction is used to set the Input Fuzzy registers with values stored in the Register File. The result of a Fuzzy inference is stored directly in a location of the Register File. 7.2 Fuzzyfication Phase In this phase the intersection (alpha weight) between the input values and the related Mbfs (Figure 7.2) is performed. Eight Fuzzy Input registers are available for Fuzzy inferences. ij i-th INPUT VARIABLE After loading the input values by using the LDFR assembler instruction, the user can start the fuzzy inference by using the FUZZY assembler instruction. During fuzzyfication: input data is transformed in the activation level (alpha weight) of the Mbf's. 7.3 Inference Phase The Inference Phase manages the alpha weights obtained during the fuzzyfication phase to compute the truth value () for each rule. This is a calculation of the maximum (for the OR operator) and/or minimum (for the AND operator) performed on alpha values according to the logical connectives of Fuzzy Rules. Several conditions may be linked together by linguistic connectives AND/OR, NOT operators and brackets. The truth value and the related output singleton are used by the Defuzzyfication phase, in order to complete the inference calculation. Figure 7.1 Fuzzy Inference 1 11 2 1m INFERENCE PHASE FUZZYFICATION DEFUZZYFICATION n1 nm Input Values N rules -1 N rules Output Values 39/85 ST52T430/E430 ST52T430/E430 Figure 7.3 Fuzzyfication IF INPUT 1 IS X1 OR INPUT 2 IS X2 THEN . 1 2 X1 I X2 Input 1 Input 2 OR = Max IF INPUT 1 IS X1 AND INPUT 2 IS X2 THEN . 1 2 X1 7.5 Input Membership Function The Decision Processor allows the management of triangular Mbfs. In order to define an Mbf, three different parameters must be stored on the Program/Data Memory (see Figure 7.4): I the vertex of the Mbf: V; X2 Input 1 the length of the left semi-base: LVD; I the length of the right semi-base: RVD; In order to reduce the size of the memory area and the computational effort the vertical range of the vertex is fixed between 0 and 15 (4 bits) By using the previous memorization method different kinds of triangular Membership Functions may be stored. Figure 7.5 shows some examples of valid Mbfs that can be defined in ST52T430/ ST52T430/ E430. Each Mbf is then defined storing 3 bytes in the first Kbyte of the Program/Data Memory. The Mbf is stored by using the following instruction: Input 2 MBF n_mbf lvd v rvd 7.4 Defuzzyfication In this phase the output crisp values are determined by implementing the consequent part of the rules. Each consequent Singleton Xi is multiplied by its weight values i, calculated by the Decision processor, in order to compute the upper part of the Defuzzyfication formula. Each output value is obtained from the consequent crisp values (Xi) by carrying out the following Defuzzyfication formula: where: n_mbf is a tag number that identifies the Mbf lvd, v, and rvd are the parameters that describe the Mbf's shape as described above. Figure 7.4 Mbfs Parameters 15 Input Mbf N Xij ij j Y i = -N 0 V ij LVD Input Variable RVD j where: i = identifies the current output variable N = number of the active rules on the current output ij = weight of the j-th singleton Xij = abscissa of the j-th singleton The Decision Processor outputs are stored in the RAM location i-th specified in the assembler instruction OUT i. 40/85 Output Singleton 15 w 0 X Output Variable ST52T430/E430 ST52T430/E430 Figure 7.5 Example of valid Mbfs Figure 7.6 Output Membership Functions j-th Singleton 1 ij i0 in 0 X i0 7.6 Output Singleton The Decision Processor uses a particular kind of membership function called Singleton for its output variables. A Singleton doesn't have a shape, like a traditional Mbf, and is characterized by a single point identified by the couple (X, w), where w is calculated by the Inference Unit as described earlier. Often, a Singleton is simply identified with its Crisp Value X. X ij X in i-th OUTPUT 7.7 Fuzzy Rules Rules can have the following structures: if A op B op C.then Z if (A op B) op (C op D op E.) .then Z where op is one of the possible linguistic operators (AND/OR) In the first case the rule operators are managed sequentially; in the second one, the priority of the operator is fixed by the brackets. Each rule is codified by using an instruction set, the inference time for a rule with 4 antecedents and 1 consequent is about 3 microseconds at 20 MHz. The Assembler Instruction Set used to manage the Fuzzy operations is reported in the table below. Table 7.1 Fuzzy Instructions Set Instruction Description MBF n_mbf Ivd v rvd Stores the Mbf n_mbf with the shape identified by the parameters Ivd, v and rvd LDP n m Fixes the alpha value of the input n with the Mbf m and stores it in internal registers LDN n m Calculates the complementary alpha value of the input n with the Mbf m. and stores the result in internal registers FZAND Implements the Fuzzy operation AND between the last two values stored in internal registers FZOR Implements the Fuzzy operation OR between the last two values stored in internal registers LDK Stores the result of the last Fuzzy operation executed in internal registers SKM Loads the result of the last performed Fuzzy operation (stored in the temporary register K) in the temporary buffer M. LDM Copies the value of register M in the data stack CON crisp Multiplies the crisp value with the last weight OUT n_out Performs Defuzzyfication and stores the currently Fuzzy output in the RAM n_out location FUZZY Starts the Fuzzy algorithm 41/85 ST52T430/E430 ST52T430/E430 Example 1: IF Input1 IS NOT Mbf1 AND Input4 is Mbf12 OR Input3 IS Mbf8 THEN Crisp1 is codified by the following instructions: LDN 1 1 calculates the NOT value of Input1 with Mbf1 and stores the result in internal registers LDP 4 12 fixes the value of Input4 with Mbf12 and stores the result in internal registers FZAND implements the operation AND between the results obtained with the previous instructions LDK stores the result of the previous operation in internal DPU registers LDP 3 8 fixes the value of Input3 with Mbf8 and stores the result in internal registers FZOR implements the operation OR between the results obtained with the previous instructions CON crisp1 multiplies the result of the last operation with the crisp value crisp1 Example 2, the priority of the operator is fixed by the brackets: IF (Input3 IS Mbf1 AND Input4 IS NOT Mbf15) OR (Input1 IS Mbf6 OR Input6 IS NOT Mbf14) THEN Crisp2 LDP 3 1 fixes the value of Input3 with Mbf1 and stores the result in internal registers LDN 4 15 calculates the NOT value of Input4 with Mbf15 and stores the result in internal registers FZAND implements the operation AND between the results obtained with the previous instructions SKM stores the result of the previous operation in register M LDP 1 6 fixes the value of Input1 with Mbf6 and stores the result in internal registers LDN 2 14 calculates the NOT value of Input6 with Mbf14 and stores the result in internal registers FZOR implements the operation OR between the results obtained with the previous instructions LDK stores the result of the previous operation in internal DPU registers LDM copies the value of the register M in internal DPU registers FZOR implements the operation OR between the last two values stored in DPU registers CON crisp2 multiplies the result of the last operation with the crisp value crisp2 At the end of the fuzzy rule, by using the instruction OUT RAM_reg, a byte is written. Afterwards, the control of the algorithm returns to the CU. 42/85 ST52T430/E430 ST52T430/E430 8 A/D CONVERTER 8.1 Introduction The A/D Converter of ST52x430 is an 8-bit analog to digital converter with up to 8 analog inputs offering 8 bit resolution with a total accuracy of 1 LSB and a typical conversion time of 8.2 µs with a 20 MHz clock. This period also includes the 5.1 µs of the integral Sample and Hold circuitry, which minimizes the need for external components and allows quick sampling of the signal for a minimum warping effect and Integral conversion error. Conversion is performed in 82 A/D clock pulses. The A/D clock is derived from the clock master. The maximum A/D clock frequency has to be 10 MHz. When the master clock is higher than 10 MHz it has to be divided by 2 using the SCK bit of the A/D configuration register REG_CONF 3 (See Table 8.1). The A/D peripheral converts the input voltage with a process of successive approximations using a fixed clock frequency derived from the oscillator. The conversion range is between the analog VSS and VDD references. The converter uses a fully differential analog input configuration for the best noise immunity and Figure 8.1 A/D Converter Structure precision performance, along with one separate supply (VDDA), allowing the best supply noise rejection. Up to 8 multiplexed Analog Inputs are available. A group of signals can be converted sequentially by simply programming the starting address of the last analog channel to be converted. Single or continuous conversion mode are available. The result of the conversion is stored in an 8-bit Input Register (from IR 1 to IR 8). The A/D converter is controlled via the Configuration Register REG_CONF 3. A Power-Down programmable bit allows the A/D converter to be set to a minimum consumption idle status. The ST52x430 Interrupt Unit provides one maskable channel for the End of Conversion (EOC). 8.2 Operational Description The conversion is monotonic, meaning that the result never decreases if the analog input doesn't and never increases if the analog input doesn't. If input voltage is greater than or equal to Vdda (Voltage Reference high) then the result is equal to FFh (full scale) without an overflow indication. CONFIGURATION REGISTER 3 INPUT REGISTER STR LP POW SEQ SCK CH0 CH1 CH2 1÷8 A/D CHANNEL 0 A/D CHANNEL 1 A/D CHANNEL 2 A/D CHANNEL 3 A/D CHANNEL 4 A/D CHANNEL 5 A/D CHANNEL 6 A/D CHANNEL 7 PB0/AIN0 CONTROL LOGIC PB1/AIN1 PB2/AIN2 SAMPLE & HOLD ANALOG PB3/AIN3 MUX PB4/AIN4 PB5/AIN5 SUCCESSIVE APPROXMATION A/D CONVERTER PB6/AIN6 PB7/PA7/AIN7 43/85 ST52T430/E430 ST52T430/E430 If input voltage is less than VSS (voltage reference low) then the result is equal to 00h. The A/D converter is linear and the digital result of the conversion is provided by the following formula: 255inputVoltage Digitalresult = -referenceVoltage Where Reference Voltage is Vdda - Vss. The accuracy of the conversion is described in the Electrical Characteristics Section. The A/D converter is not affected by the WAIT mode. When the MCU enters HALT mode with A/D converter enabled, the converter is disabled until HALT mode is terminated and the start-up delay has elapsed. A stabilization period is also required before accurate conversions can be performed. 8.2.1 Operating Modes. Four main operating modes can be selected by setting the values of the LP and SEQ bit in the A/D configuration Register. One Channel Single Mode In this mode (SEQ = `0'', LP = `0') the A/D provides an EOC signal after the end of channel i-th conversion; then the A/D waits for a new start event. Channel i-th is identified by the bit CH0, CH1, CH2. i.e CH(2:0) = `011' means conversion of channel 3 then stop. Multiple Channels Single Mode In this mode (SEQ = `1', LP = `0') the A/D provides an EOC signal after the end of the channels sequence conversion identified by the bit CH0, CH1, CH2; then the A/D waits for a new start event. i.e. CH(2:0) = `011' means conversion of channels 0,1,2 and 3 then stop. Figure 8.2 Conf. Register (REG_CONF 3) REG_CONF 3 D7 D0 CH2 CH1 CH0 SCK SEQ POW LP STR START/STOP CONVERSION MODE SEL. ON/OFF A/D CONVERSION MODE SEL. CLOCK SELECTOR CHANNELS SEL. 44/85 ST52T430/E430 ST52T430/E430 One Channel Continuous Mode In this mode (SEQ = `0'', LP = `1') a continuous conversion flow is entered by a starting event on the channel selected by the CH0, CH1, CH2 bits For example: CH(2:0) = `011' means continuous conversion of channel 3. At the end of each conversion the relative IR is updated with the last conversion result, while the former value is lost. To stop the conversion STR has to be set to `0'. Multiple Channels Continuous Mode In this mode (SEQ = `1'', LP = `1') a continuous conversion flow is entered by a starting event on the channels selected by the CH0, CH1, CH2 bits. i.e CH(2:0) = `011' means continuous conversion of channel 0,1,2 and 3. At the end of each conversion the relative IRs are updated with the last conversion results, while the former values are lost. To stop the conversion STR has to be set to `0'. 8.2.2 Power Down Mode. Before enabling any A/D operation mode, set the POW bit of the A/D configuration register to `1' at least 60 µs before the first conversion starts to enable the biasing circuit inside the analog section of the converter. Clearing the POW bit (POW = `0') is useful when the A/D is not used, reducing the total chip power consumption. This state is also the reset configuration and it is forced by hardware when the core is in HALT state (after a HALT instruction execution). setting CH2=0 CH1=0 CH0=0 only channel 0 is converted. b4 = SCK: Master clock divider. ST52x430 can work with a clock frequency up to 20 MHz. The SCK must be set to `1' when the ST52x430 clock is higher then 10 MHz. It is useful to set SCK = `1' even when the clock master is lower than 10 MHz and a high accuracy is required. b3 = SEQ: Multiple/Single channel. When SEQ is set to `0' the channel identified by CH(2:0) is converted. If SEQ is set to `1' the group of channels identified by CH(2:0) are converted. b2= POW: Power Up/ Power Down. A logical `1' enables the A/D logic and analog circuitry. Logical level `0' disables all power consuming logic, allowing a low power idle status. b1 = LP: Continuous/Single. When this bit is set to `1' (continuous mode), the first conversion sequences are started by the STR bit then a continuous conversion flow is processed. When LP='0' (single mode) only one sequence of conversions is started when STR is set. b0 = STR: Start/Stop. A logical level `1' enables starting a conversion sequence; a logical level `0' stops the conversion. When the A/D is running in the Single Modes (LP='0'), this bit is hardware reset at the end of a conversion sequence. Table 8.1 A/D Conf. Register (Reg_Conf 3) Name 0 8.3 A/D Registers Description The result of the conversions of the 8 available channels are loaded in the 8 Input Register from decimal address 1 to decimal address 8. (IR (1:8) see Table 2.2). Every IR(1:8) is reloaded with a new value at the end of the conversion of the correspondent analog input. By using the assembler instruction: LDRI RAM_Reg. IR_i the value stored in the i-th IR is transferred on the RAM location RAM_Reg. The A/D configuration register is the REG_CONF 3. Figure 6.2 illustrates the structure of this register, which manages the A/D logic operation. The A/D configuration register (REG_CONF 3) is programmable as following: b7-b5 = CH2, CH1, CH0: Last Conversion Address. These 3 bits define the last analog input. The first analog input is converted, then the address is incremented for the successive conversion until the channel identified by CH0CH2 is converted. The (CH2, CH1, CH0) bits define the group of channels to be scanned. When Bit STR A/D ON 0 Single Channel Conv. Multiple Channels Conv 0 Clock not Divided Clock Divided Channel 0 Channel 1 Channel 2 011 Channel 3 Channel 4 101 7 A/D OFF 100 CH(2:0) 0 010 6 Continuous 001 5 Single Conversion 000 SCK 0 1 4 SEQ Start Conversion 1 3 POW Stop Conversion 1 2 0 1 LP Description 1 1 Value Channel 5 110 Channel 6 111 Channel 7 45/85 ST52T430/E430 ST52T430/E430 9 WATCHDOG TIMER 9.1 Operational Description The Watchdog Timer (WDT) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which cause the application program to abandon its normal sequence. The WDT circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the WDT before the end of the programmed time delay. 16 different delays can be selected by using the WDT configuration register. After the end of the delay programmed by the configuration register if the WDT is activated (by using the assembler instruction WDTSFR), it starts a reset cycle pulling the reset pin low. Once the WDT has been activated the application program has to refresh this peripheral (by the WDTSFR instruction) at regular intervals during normal operation in order to prevent an MCU reset. In order to stop the WDT during user program execution the instruction WDTSLP has to be used. The working frequency of the WDT (PRES CLK in the Figure 9.1) is equal to the clock master. The clock master is divided by 500, obtaining the WDT CLK signal, which is used to fix the timeout of the WDT. Table 9.1 Watchdog Timing range (CLK=5 MHz) WDT timeout period (ms) min 0.1 max 937.5 According to the WDT configuration register values, a WDT delay may be defined between 0.1 ms and 937.5 mS when the clock master is 5 MHz. By changing the clock master frequency the timeout delay can be calculated according to the configuration register values REG_CONF 2, as described in the following section. Warning: changing the REG_CONF2 value when the WDT is active, a WDT reset is generated and the CPU is restarted. To avoid this side effect, use the WDTSLP instruction before changing the REG_CONF2. Figure 9.1 Watchdog Block Diagram REG_CONF 2 D3 D2 D1 D0 WDT WDTRFR RESET PRESCALER PRES CLK = CLK MASTER WDTSLP 46/85 WTD CLK RESET GENERATOR RESET ST52T430/E430 ST52T430/E430 9.2 Register Description The WDT timeout is defined by setting the value of the REG_CONF 2. The first 4 bits of this register are used, obtaining 16 different delays as illustrated in Table 9.2. In Table 9.2 timeout is expressed by using the number of WDT CLK. The WDT CLK is derived from the clock master by a division factor of 500. Timeout is obtained by multiplying the WDT CLK pulse length for the number of pulses defined by the configuration register REG_CONF 2. Table 9.4 illustrates the pulse lengths for typical values of the clock master. Table 9.3 illustrates the timeout WDT values when the Master Clock is 5 MHz. Table 9.3 Timeout Values with CLK = 5 MHz Bit Name Value Timeout Values (ms) 0000 62.5 0010 0 0.1 0001 125 0011 312.5 0110 D (3:0) 250 0101 1 187.5 0100 375 Table 9.2