ST16C654/654D 64-BYTE ST16C654 ST16C554 ST68C554 ST16C654CQ64 ST16C654DCQ64 - Datasheet Archive
QUAD UART WITH 64-BYTE FIFO AND INFRARED (IrDA) ENCODER/DECODER DESCRIPTION The ST16C654 *1 is a universal asynchronous receiver
ST16C654/654D ST16C654/654D QUAD UART WITH 64-BYTE 64-BYTE FIFO AND INFRARED (IrDA) ENCODER/DECODER DESCRIPTION The ST16C654 ST16C654 *1 is a universal asynchronous receiver and transmitter (UART) with a dual foot print interface compatible with the ST16C554 ST16C554 and ST68C554 ST68C554. The 654 is an enhanced UART with 64 byte FIFOs, automatic hardware/software flow control, and data rates up to 1.5Mbps. Onboard status registers provide the user with error indications and operational status, modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows onboard diagnostics. The 654 is available in 64 pin TQFP, 68 pin PLCC, and 100 pin QFP packages. The 64 pin package offers the 16 interface mode which is compatible with the industry standard ST16C554 ST16C554. The 68 and 100 pin packages offer an additional 68 mode which allows easy integration with Motorola, and other popular microprocessors. The ST16C654CQ64 ST16C654CQ64 (64 pin) offers three state interrupt control while the ST16C654DCQ64 ST16C654DCQ64 provides constant active interrupt outputs. The 64 pin devices do not offer TXRDY/RXRDY outputs or the default clock select option (CLKSEL). The 100 pin packages offer faster channel status access by providing separate outputs for TXRDY and RXRDY, offer separate Infrared TX outputs and a musical instrument clock input (MIDICLK). The 654 combines the package interface modes of the 16C454/ 16C454/ 554 and 68/C454/554 68/C454/554 series on a single integrated chip. FEATURES -CDA -RIA RXA GND D7 D6 D5 D4 D3 D2 D1 D0 INTSEL VCC RXD -RID -CDD 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 63 PLCC Package -DSRA 10 60 -DSRD -CTSA 11 59 -CTSD -DTRA 12 58 -DTRD VCC 13 57 GND -RTSA 14 56 -RTSD INTA 15 55 INTD -CSA 16 54 -CSD TXA 17 53 TXD -IOW 18 52 -IOR TXB 19 51 TXC -CSB 20 50 -CSC INTB 21 49 INTC -RTSB 22 48 -RTSC GND 23 47 VCC -DTRB 24 46 -DTRC -CTSB 25 45 -CTSC -DSRB 26 44 -DSRC Part number ST16C654CJ68 ST16C654CJ68 ST16C654CQ64 ST16C654CQ64 ST16C654DCQ64 ST16C654DCQ64 ST16C654CQ100 ST16C654CQ100 Pins 68 64 64 100 Package Operating temperature PLCC TQFP TQFP QFP 0° C to + 70° C 0° C to + 70° C 0° C to + 70° C 0° C to + 70° C 40 41 42 43 RXC -RIC -CDC 39 -TXRDY GND 38 34 A0 -RXRDY 33 A1 37 32 A2 RESET 31 16/-68 36 30 CLKSEL Pins 68 64 64 100 XTAL2 29 RXB ST16C654IJ68 ST16C654IJ68 ST16C654IQ64 ST16C654IQ64 ST16C654DIQ64 ST16C654DIQ64 ST16C654IQ100 ST16C654IQ100 35 28 Part number XTAL1 27 ORDERING INFORMATION -RIB ST16C654CJ68 ST16C654CJ68 16 MODE -CDB · Compatibility with the Industry Standard ST16C454/554 ST16C454/554, ST68C454/554 ST68C454/554, TL16C554 TL16C554 · 1.5 Mbps transmit/receive operation (24MHz) · 64 byte transmit FIFO · 64 byte receive FIFO with error flags · Automatic software/hardware flow control · Programmable Xon/Xoff characters · Independent transmit and receive control · Software selectable Baud Rate Generator prescaleable clock rates of 1X, 4X. · Four selectable Transmit/Receive FIFO interrupt trigger levels · Standard modem interface or infrared IrDA encoder/decoder interface · Software flow control turned off optionally by any (Xon) RX character · Independent MIDI interface on 100 pin packages · 100 pin packages offer internal register FIFO monitoring and separate IrDA TX outputs · Sleep mode ( 200mA stand-by) Package Operating temperature PLCC TQFP TQFP QFP -40° C to + 85° C -40° C to + 85° C -40° C to + 85° C -40° C to + 85° C Note *1: Patent Pending Rev. 4.30 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 · (510) 668-7000 · FAX (510) 668-7017 ST16C654/654D ST16C654/654D Figure 1, Package Descriptions 23 24 25 26 27 28 29 30 31 A1 A0 XTAL1 XTAL2 RESET GND RXC -RIC -CDC D5 D4 D3 D2 D1 D0 N.C. VCC RXD -RID -CDD 2 1 68 67 66 65 64 63 62 61 27 22 A2 -CDB 21 VCC 32 20 RXB -DSRC 19 -RIB N.C. 18 D6 -DSRC N.C. 17 3 44 -DSRA -CDB D7 26 -CTSA -DSRB 4 -CTSC -DSRB -CTSC 43 33 45 -CDC 16 25 42 -CTSB -DTRC -CTSB -DTRC -RIC 34 46 41 15 24 RXC -DTRB VCC -DTRB VCC 40 35 47 GND 14 23 39 GND -RTSC GND -RTSC -TXRDY 36 48 38 13 22 -RXRDY -RTSB N.C. -RTSB INTC 49 37 37 A4 21 -RESET 12 50 36 INTB 20 N.C. -CSC TXC A3 XTAL2 38 51 35 11 19 XTAL1 -CSB N.C. TXB TXC ST16C654DCQ64 ST16C654DCQ64 34 39 52 ST16C654CJ68 ST16C654CJ68 68 MODE A0 10 TXD 18 33 -TXB 53 R/-W -IOR N.C. 17 A1 40 54 32 9 N.C. 16 A2 -IOW ST16C654CQ64 ST16C654CQ64 GND -CDD TXA TXD 55 TXA -CSD 41 5 -RID 49 42 8 -RTSD 15 31 RXD 50 7 56 16/-68 VCC 51 -CSA GND 14 -CS INTD 57 -IRQ -RTSD 43 RXA D0 52 44 6 6 D1 53 5 INTA -DTRD 13 30 D2 54 -RTSA 58 -RTSA GND -CTSD 12 VCC -DTRD 45 -DSRD 59 CLKSEL D3 55 46 4 -RIA D4 56 3 VCC 7 D5 57 -DTRA 60 11 -DTRA -CTSD 10 -CTSA 29 D6 58 47 -DSRA -DSRD RXB D7 59 -CDA GND 60 2 8 RXA 61 9 -RIA 62 48 28 -CTSA 1 -RIB -CDA -DSRA 63 68 Pin PLCC Package 64 64 Pin TQFP Package 100 Pin QFP Package N.C. N.C. N.C. N.C. N.C. -TXRDYB IRTXB -DSRB -CTSB -DTRB GND -RTSB INTB -CSB TXB -IOW TXA -CSA INTA -RTSA VCC -DTRA IRTXA -TXRDYA N.C. N.C. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 -RXRDYB 31 100 -RXRDYA -CDB 32 99 -CDA -RIB 33 98 -RIA RXB 34 97 RXA CLKSEL 35 96 GND 16/-68 36 95 D7 A2 37 94 D6 A1 38 93 D5 A0 39 92 D4 XTAL1 40 91 D3 XTAL2 41 90 D2 MIDICLK 42 89 D1 RESET 43 88 D0 -RXRDY 44 87 INTSEL -TXRDY 45 86 VCC GND 46 85 RXD RXC 47 84 -RID -RIC 48 83 -CDD -CDC 49 82 -RXRDYD -RXRDYC 50 81 -TXRDYD ST16C654CQ100 ST16C654CQ100 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 N.C. N.C. N.C. N.C. N.C. -TXRDYC IRTXC -DSRC -CTSC -DTRC VCC -RTSC INTC -CSC TXC -IOR TXD -CSD INTD -RTSD GND -DTRD -CTSD -DSRD IRTXD -CSRDY N.C. N.C. N.C. N.C. Rev. 4.30 2 ST16C654/654D ST16C654/654D Figure 2, Block Diagram 16 Mode XTAL1 MIDI XTAL2 Data bus & Control Logic Register Select Logic Receive FIFO Registers Inter Connect Bus Lines & Control signals INT A-D -RXRDY -TXRDY -RXRDY A-D -TXRDY A-D INTSEL Interrupt Control Logic A0-A2 -CS A-D Flow Control Logic Flow Control Logic Transmit Shift Register TX A-D Ir Encoder Receive Shift Register RX A-D RXIR A-D Ir Decoder -DTR A-D -RTS A-D Modem Control Logic Clock & Baud Rate Generator D0-D7 -IOR -IOW RESET Transmit FIFO Registers Rev. 4.30 3 -CTS A-D -RI A-D -CD A-D -DSR A-D ST16C654/654D ST16C654/654D Figure 3, Block Diagram 68 Mode XTAL1 MIDI XTAL2 Data bus & Control Logic Register Select Logic Receive FIFO Registers Inter Connect Bus Lines & Control signals IRQ -RXRDY -TXRDY -RXRDY A-D -TXRDY A-D Interrupt Control Logic A0-A4 -CS Flow Control Logic Flow Control Logic Transmit Shift Register TX A-D Ir Encoder Receive Shift Register RX A-D IRRX A-D Ir Decoder -DTR A-D -RTS A-D Modem Control Logic Clock & Baud Rate Generator D0-D7 R/-W -RESET Transmit FIFO Registers Rev. 4.30 4 -CTS A-D -RI A-D -CD A-D -DSR A-D ST16C654/654D ST16C654/654D SYMBOL DESCRIPTION Symbol 68 Pin 100 64 Signal type 16/-68 31 36 - I 16/68 Interface Type Select (input with internal pull-up). This input provides the 16 (Intel) or 68 (Motorola) bus interface type select. The functions of -IOR, -IOW, INT AD, and -CS A-D are re-assigned with the logical state of this pin. When this pin is a logic 1, the 16 mode interface 16C554 16C554 is selected. When this pin is a logic 0, the 68 mode interface (68C554 68C554) is selected. When this pin is a logic 0, -IOW is reassigned to R/-W, RESET is re-assigned to -RESET, -IOR is not used, and INT A-D(s) are connected in a WIRE-OR configuration. The WIRE-OR outputs are connected internally to the open source IRQ signal output. This pin is not available on 64 pin packages which operate in the 16 mode only. A0 34 39 24 I Address-0 Select Bit. Internal registers address selection in 16 and 68 modes. A1 33 38 23 I Address-1 Select Bit. Internal registers address selection in 16 and 68 modes. A2 32 37 22 I Address-2 Select Bit. - Internal registers address selection in 16 and 68 modes. 20,50 17,64 - I Address 3-4 Select Bits. - When the 68 mode is selected, these pins are used to address or select individual UARTs (providing -CS is a logic 0). In the 16 mode, these pins are reassigned as chip selects, see -CSB and -CSC. These pins are not available on 64 pin packages which operate in the 16 mode only. CLKSEL 30 35 - I Clock Select. - The 1X or 4X pre-scaleable clock is selected by this pin. The 1X clock is selected when CLKSEL is a logic 1 (connected to VCC) or the 4X is selected when CLKSEL is a logic 0 (connected to GND). MCR bit-7 can override the state of this pin following reset or initialization (see MCR bit7). This pin is not available on 64 pin packages which provide MCR bit-7 selection only. -CS 16 13 - I Chip Select. (active low) - In the 68 mode, this pin functions as a multiple channel chip enable. In this case, all four A3-A4 Pin Description Rev. 4.30 5 ST16C654/654D ST16C654/654D SYMBOL DESCRIPTION Symbol 68 Pin 100 64 Signal type Pin Description UARTs (A-D) are enabled when the -CS pin is a logic 0. An individual UART channel is selected by the data contents of address bits A3-A4. When the 16 mode is selected (68/100 pin devices), this pin functions as -CSA, see definition under -CS A-B. This pin is not available on 64 pin packages which operate in the 16 mode only. -CS A-B -CS C-D 16,20 50,54 13,17 64,68 7,11 38,42 I Chip Select A, B, C, D (active low) - This function is associated with the 16 mode only, and for individual channels, A through D. When in 16 Mode, these pins enable data transfers between the user CPU and the ST16C654 ST16C654 for the channel(s) addressed. Individual UART sections (A, B, C, D) are addressed by providing a logic 0 on the respective -CS A-D pin. When the 68 mode is selected, the functions of these pins are reassigned. 68 mode functions are described under the their respective name/pin headings. -CSRDY - 76 - I Control Status Ready (active low) - This feature is available on 100 pin QFP packages only. On 100 pin packages, the Contents of the FIFORDY Register is read when this pin is a logic 0. However it should be noted, D0-D3 will contain the inverted logic states of TXRDY, status bits A-D, and D4-D7 the inverted logic states of RXRDY, status bits D4-D7. D0-D2 D3-D7 66-68 1-5 88-90 91-95 53-55 56-60 I/O GND GND 6,23 40,57 96,20 46,71 14,28 45,61 Pwr INT A-B INT C-D 15,21 49,55 12,18 63,69 6,12 37,43 O Data Bus (Bi-directional) - These pins are the eight bit, three state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. Signal and power ground. Interrupt A, B, C, D (active high) - This function is associated with the 16 mode only. These pins provide individual channel interrupts, INT A-D. INT A-D are enabled when MCR bit-3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and when an interrupt con- Rev. 4.30 6 ST16C654/654D ST16C654/654D SYMBOL DESCRIPTION Symbol 68 Pin 100 64 Signal type Pin Description dition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. When the 68 mode is selected, the functions of these pins are reassigned. 68 mode functions are described under the their respective name/pin headings. INTSEL 65 87 - I Interrupt Select. (active high, with internal pull-down) - This function is associated with the 16 mode only. When the 16 mode is selected, this pin can be used in conjunction with MCR bit-3 to enable or disable the three state interrupts, INT A-D or override MCR bit-3 and force continuous interrupts. Interrupt outputs are enabled continuously by making this pin a logic 1. Making this pin a logic 0 allows MCR bit-3 to control the three state interrupt output. In this mode, MCR bit-3 is set to a logic 1 to enable the three state outputs. This pin is disabled in the 68 mode. Due to pin limitations on 64 pin packages, this pin is not available. To cover this limitation, two 64 pin QFP package versions are offered. The ST16C654DCQ64 ST16C654DCQ64 operates in the continuos interrupt enable mode by bonded this pin to VCC internally. The ST16C654CQ64 ST16C654CQ64 operates with MCR bit-3 control by bonding this pin to GND. -IOR 52 66 40 I Input/Output Read. (active low Strobe) - This function is associated with the 16 mode only. A logic 0 transition on this pin will load the contents of an Internal register defined by address bits A0-A2 onto the ST16C654 ST16C654 data bus (D0-D7) for access by an external CPU. This pin is disabled in the 68 mode. -IOW 18 15 9 I Input/Output Write. (active low strobe) - This function is associated with the 16 mode only. A logic 0 transition on this pin will transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is defined by address bits A0/A2. When the 16 mode is selected (68/100 pin devices), this pin functions as R/-W, see definition under R/W. Rev. 4.30 7 ST16C654/654D ST16C654/654D SYMBOL DESCRIPTION Symbol 68 Pin 100 64 Signal type 15 12 - O Interrupt Request or Interrupt A - This function is associated with the 68 mode only. In the 68 mode, interrupts from UART channels A-D are WIRE-ORed internally to function as a single IRQ interrupt. This pin transitions to a logic 0 (if enabled by the interrupt enable register) whenever a UART channel(s) requires service. Individual channel interrupt status can be determined by addressing each channel through its associated internal register, using -CS and A3A4. In the 68 mode an external pull-up resistor must be connected between this pin and Vcc. The function of this pin changes to INTA when operating in the 16 mode, see definition under INTA. IRTX A-B IRTX C-D - 6,24 57,75 - O Infrared Transmit Data Output (IrDA) - This function is associated with 100 pin packages only. These pins provide separate infrared IrDA TX outputs for UART channels (AD). The serial infrared IRTX data is transmitted via these pins with added start, stop and parity bits. The IRTX signal will be a logic 0 during reset, idle (no data), or when the transmitter is disabled. MCR bit-6 selects the standard modem or infrared interface. MIDICLK - 42 - I MIDI (Musical Instrument Digital Interface) Clock Input This function is associated with 100 pin packages only. RXC and TXC can function as MIDI input/output ports when an external MIDI Clock is provided at this pin. External Clock or a crystal is connected to the XTAL2 pins for normal operation (see XTAL 1 & 2). -RESET RESET 37 43 27 I Reset. - In the 16 mode a logic 1 on this pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. (See ST16C654 ST16C654 External Reset Conditions for initialization details.) When 16/-68 is a logic 0 (68 mode), this pin functions similarly but, as an inverted reset interface signal, -RESET. R/-W 18 15 - I Read/Write Strobe (active low) - This function is associated -IRQ Pin Description Rev. 4.30 8 ST16C654/654D ST16C654/654D SYMBOL DESCRIPTION Symbol 68 Pin 100 64 Signal type Pin Description with the 68 mode only. This pin provides the combined functions for Read or Write strobes. A logic 1 to 0 transition transfers the contents of the CPU data bus (D0-D7) to the register selected by -CS and A0-A4. Similarly a logic 0 to 1 transition places the contents of a 654 register selected by -CS and A0-A4 on the data bus, D0-D7, for transfer to an external CPU. -RXRDY -RXRDY A-B -RXRDY C-D -TXRDY 38 44 - O Receive Ready (active low) - This function is associated with 68 and 100 pin packages only. -RXRDY contains the wire OR-ed status of all four receive channel FIFOs, RXRDY A-D. A logic 0 indicates receive data ready status, i.e. the RHR is full or the FIFO has one or more RX characters available for unloading. This pin goes to a logic 1 when the FIFO/RHR is full or when there are no more characters available in either the FIFO or RHR. The 100 pin chip-sets provide both the combined wire ored output and individual channel RXRDY-A-D outputs. RXRDY A-D is discussed in a following paragraph. For 64/68 pin packages, individual channel RX status is read by examining individual internal registers via -CS and A0-A4 pin functions. - 100,31 50,82 - O Receive Ready A-D (active low) - This function is associated with 100 pin packages only. This function provides the RX FIFO/RHR status for individual receive channels (A-D). A logic 0 indicates there is receive data to read/unload, i.e., receive ready status with one or more RX characters available in the FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the programmed trigger level has not been reached. 39 45 - O (active low) - This function is associated with 68 and 100 pin packages only. -TXRDY contains the wire OR-ed status of all four transmit channel FIFOs, TXRDY A-D. A logic 0 indicates a buffer ready status, i.e., at least one location is empty and available in one of the TX channels (A-D). This pin goes to a logic 1 when all four channels have no more empty locations in the TX FIFO or THR. The 100 pin chipsets provide both the combined wire ored output and Rev. 4.30 9 ST16C654/654D ST16C654/654D SYMBOL DESCRIPTION Symbol 68 Pin 100 64 Signal type Pin Description individual channel TXRDY-A-D outputs. TXRDY A-D is discussed in a following paragraph For 64/68 pin packages, individual channel TX status can be read by examining individual internal registers via -CS and A0-A4 pin functions. -TXRDY A-B -TXRDY C-D - 5,25 56,81 - O 13 47,64 10 61,86 4,21 35,52 I Power supply inputs. XTAL1 35 40 25 I Crystal or External Clock Input - Functions as a crystal input or as an external clock input. A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit (see figure 8). Alternatively, an external clock can be connected to this pin to provide custom data rates (see Baud Rate Generator Programming and optional MIDCLK). XTAL2 36 41 26 O Output of the Crystal Oscillator or Buffered Clock - (See also XTAL1). Crystal oscillator output or buffered clock output. -CD A-B -CD C-D 9,27 43,61 99,32 49,83 64,18 31,49 I Carrier Detect (active low) - These inputs are associated with individual UART channels A through D. A logic 0 on this pin indicates that a carrier has been detected by the modem for that channel. -CTS A-B -CTS C-D 11,25 45,59 8,22 59,73 2,16 33,47 I Clear to Send (active low) - These inputs are associated with individual UART channels, A through D. A logic 0 on the CTS pin indicates the modem or data set is ready to accept transmit data from the 654. Status can be tested by reading MSR bit-4. This pin only affects the transmit and receive VCC VCC This function is associated with 100 pin packages only. These outputs provide the TX FIFO/THR status for individual transmit channels (A-D). As such, an individual channels -TXRDY A-D buffer ready status is indicated by logic 0, i.e., at least one location is empty and available in the FIFO or THR. This pin goes to a logic 1 when there are no more empty locations in the FIFO or THR. Rev. 4.30 10 ST16C654/654D ST16C654/654D SYMBOL DESCRIPTION Symbol 68 Pin 100 64 Signal type Pin Description operations when Auto CTS function is enabled via the Enhanced Feature Register (EFR) bit-7, for hardware flow control operation. -DSR A-B -DSR C-D 10,26 44,60 7,23 58,74 1,17 32,48 I Data Set Ready (active low) - These inputs are associated with individual UART channels, A through D. A logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the UART. This pin has no effect on the UARTs transmit or receive operation. -DTR A-B -DTR C-D 12,24 46,58 9,21 60,72 3,15 34,46 O Data Terminal Ready (active low) - These inputs are associated with individual UART channels, A through D. A logic 0 on this pin indicates that the 654 is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR bit-0 will set the -DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR bit-0, or after a reset. This pin has no effect on the UARTs transmit or receive operation. -RI A-B -RI C-D 8,28 42,62 98,33 48,84 63,19 30,50 I Ring Indicator (active low) - These inputs are associated with individual UART channels, A through D. A logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt. -RTS A-B -RTS C-D 14,22 48,56 11,19 62,70 5,13 36,44 O Request to Send (active low) - These outputs are associated with individual UART channels, A through D. A logic 0 on the -RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register (MCR bit-1) will set this pin to a logic 0 indicating data is available. After a reset this pin will be set to a logic 1. This pin only affects the transmit and receive operations when Auto RTS function is enabled via the Enhanced Feature Register (EFR) bit-6, for hardware flow control operation. Rev. 4.30 11 ST16C654/654D ST16C654/654D SYMBOL DESCRIPTION Symbol 68 Pin 100 64 Signal type Pin Description RX/IRRX A-B RX/IRRX C-D 7,29 41,63 97,34 47,85 62,20 29,51 I Receive Data Input RX/IRRX A-D. - These inputs are associated with individual serial channel data to the ST16C654 ST16C654. Two user selectable interface options are available. The first option supports the standard modem interface. The second option provides an Infrared decoder interface, see figures 2/3. When using the standard modem interface, the RX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. The inactive state (no data) for the Infrared decoder interface is a logic 0. MCR bit-6 selects the standard modem or infrared interface. During the local loop-back mode, the RX input pin is disabled and TX data is internally connected to the UART RX Input, internally. TX/IRTX A-B TX/IRTX C-D 17,19 51,53 14,16 65,67 8,10 39,41 O Transmit Data - These outputs are associated with individual serial transmit channel data from the 654. Two user selectable interface options are available. The first user option supports a standard modem interface. The second option provides an Infrared encoder interface, see figures 2/ 3. When using the standard modem interface, the TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. The inactive state (no data) for the Infrared encoder/ decoder interface is a Logic 0. MCR bit6 selects the standard modem or infrared interface. During the local loop-back mode, the TX input pin is disabled and TX data is internally connected to the UART RX Input. Rev. 4.30 12 ST16C654/654D ST16C654/654D GENERAL DESCRIPTION The 654 combines the package interface modes of the 16C454/554 16C454/554 and 68/C454/554 68/C454/554 series on a single integrated chip. The 16 mode interface is designed to operate with the Intel type of microprocessor bus while the 68 mode is intended to operate with Motorola, and other popular microprocessors. Following a reset, the 654 is down-ward compatible with the ST16C454/ ST16C454/ ST68C454 ST68C454 or the ST68C454/ST68C554 ST68C454/ST68C554 dependent on the state of the interface mode selection pin, 16/68. The 654 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. The ST16C654 ST16C654 represents such an integration with greatly enhanced features. The 654 is fabricated with an advanced CMOS process to achieve low drain power and high speed requirements. The 654 is capable of operation to 1.5Mbps with a 24 MHz crystal or external clock input. With a crystal of 14.7464 MHz and through a software option, the user can select data rates up to 460.8Kbps or 921.6Kbps, 8 times faster than the 16C554 16C554. The rich feature set of the 654 is available through internal registers. Automatic hardware/software flow control, selectable transmit and receive FIFO trigger levels, selectable TX and RX baud rates, infrared encoder/decoder interface, modem interface controls, and a sleep mode are all standard features. MCR bit-5 provides a facility for turning off (Xon) software flow control with any incoming (RX) character. In the 16 mode INTSEL and MCR bit-3 can be configured to provide a software controlled or continuous interrupt capability. Due of pin limitations for the 64 pin 654 this feature is offered by two different QFP packages. The ST16C654DCQ64 ST16C654DCQ64 operates in the continuos interrupt enable mode by bonded INTSEL to VCC internally. The ST16C654CQ64 ST16C654CQ64 operates in conjunction with MCR bit-3 by bonding INTSEL to GND internally. The 654 is an upward solution that provides 64 bytes of transmit and receive FIFO memory, instead of 16 bytes provided in the 16/68C554 16/68C554, or none in the 16/ 68C454 68C454. The 654 is designed to work with high speed modems and shared network environments, that require fast data processing time. Increased performance is realized in the 654 by the larger transmit and receive FIFOs. This allows the external processor to handle more networking tasks within a given time. For example, the ST16C554 ST16C554 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses a character length of 11 bits, including start/stop bits at 115.2Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. However with the 64 byte FIFO in the 654, the data buffer will not require unloading/loading for 6.1 ms. This increases the service interval giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. In addition, the 4 selectable levels of FIFO trigger interrupt and automatic hardware/software flow control is uniquely provided for maximum data throughput performance especially when operating in a multi-channel environment. The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The 68 and 100 pin ST16C654 ST16C654 packages offer a clock select pin to allow system/board designers to preset the default baud rate table. The CLKSEL pin selects the 1X or 4X pre-scaleable baud rate generator table during initialization, but can be overridden following initialization by MCR bit-7. The 100 pin packages offer several enhances features. These features include an MIDI clock input, an internal FIFO monitor register, and separate IrDA TX outputs. The MIDI (Musical Instrument Digital Interface) can be connected to the XTAL2 pin for normal Rev. 4.30 13 ST16C654/654D ST16C654/654D The 68 Mode Interface The 68 mode configures the package interface pins for connection with Motorola, and other popular microprocessor bus types. The interface operates similar to the 68C454/554 68C454/554. In this mode the 654 decodes two additional addresses, A3-A4 to select one of the four UART ports. The A3-A4 address decode function is used only when in the 68 mode (16/-68 logic 0), and is shown in Table 3 below. operation or to external MIDI oscillator for MIDI applications. A separate register is provided for monitoring the real-time status of the FIFO signals -TXRDY and -RXRDY for each of the four UART channels (A-D). This reduces polling time involved in accessing individual channels. The 100 pin QFP package also offers, four separate IrDA (Infrared Data Association Standard) outputs for Infrared applications. These outputs are provided in addition to the standard asynchronous modem data outputs. Table 3, SERIAL PORT CHANNEL SELECTION GUIDE, 68 MODE INTERFACE FUNCTIONAL DESCRIPTIONS -CS A4 A3 UART CHANNEL 1 0 0 0 0 N/A 0 0 1 1 N/A 0 1 0 1 None A B C D Interface Options Two user interface modes are selectable for the 654 package. These interface modes are designated as the 16 mode and the 68 mode. This nomenclature corresponds to the early 16C454/554 16C454/554 and 68C454/ 68C454/ 554 package interfaces respectively. The 16 Mode Interface The 16 mode configures the package interface pins for connection as a standard 16 series (Intel) device and operates similar to the standard CPU interface available on the 16C454/554 16C454/554. In the 16 mode (pin 16/-68 logic 1) each UART is selected with individual chip select (CSx) pins as shown in Table 2 below. Internal Registers The 654 provides 15 (64/68 pin packages) or 16 (100 pin packages) internal registers for monitoring and control. These resisters are shown in Table 4 below. Twelve registers are similar to those already available in the standard 16C554 16C554. These registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/ DLM), and a user assessable scratchpad register (SPR). Beyond the general 16C554 16C554 features and capabilities, the 654 offers an enhanced feature register set (EFR, Xon/Xoff 1-2) that provides on board hardware/software flow control. Register functions are more fully described in the following paragraphs. Table 2, SERIAL PORT CHANNEL SELECTION GUIDE, 16 MODE INTERFACE -CSA -CSB -CSC -CSD UART CHANNEL 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 None A B C D Rev. 4.30 14 ST16C654/654D ST16C654/654D Table 4, INTERNAL REGISTER DECODE A2 A1 A0 READ MODE WRITE MODE General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Receive Holding Register Interrupt Status Register Line Status Register Modem Status Register Scratchpad Register Transmit Holding Register Interrupt Enable Register FIFO Control Register Line Control Register Modem Control Register Scratchpad Register Baud Rate Register Set (DLL/DLM): Note *2 0 0 0 0 0 1 LSB of Divisor Latch MSB of Divisor Latch LSB of Divisor Latch MSB of Divisor Latch Enhanced Register Set (EFR, Xon/off 1-2): Note *3 0 1 1 1 1 1 0 0 1 1 0 0 1 0 1 Enhanced Feature Register Xon-1 Word Xon-2 Word Xoff-1 Word Xoff-2 Word Enhanced Feature Register Xon-1 Word Xon-2 Word Xoff-1 Word Xoff-2 Word FIFO Ready Register: Note *4 X X X RXRDY (A-D), TXRDY (A-D) Note *2: These registers are accessible only when LCR bit-7 is set to a logic 1. Note *3: Enhanced Feature Register, Xon 1,2 and Xoff 1,2 are accessible only when the LCR is set to BF(HEX). Note *4: FIFO Ready Register is available through the CSRDY interface pin only. Rev. 4.30 15 ST16C654/654D ST16C654/654D FIFO Operation Hardware Flow Control The 64 byte transmit and receive data FIFOs are enabled by the FIFO Control Register (FCR) bit-0. With 16C554 16C554 devices, the user can set the receive trigger level but not the transmit trigger level. The 654 provides independent trigger levels for both receiver and transmitter. To remain compatible with ST16C554 ST16C554, the transmit interrupt trigger level is set to 8 following a reset. It should be noted that the user can set the transmit trigger levels by writing to the FCR register, but activation will not take place until EFR bit4 is set to a logic 1. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU. An interrupt is generated whenever the Receive Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached. (see hardware flow control for a description of this timing). When automatic hardware flow control is enabled, the 654 monitors the -CTS pin for a remote buffer overflow indication and controls the -RTS pin for local buffer overflows. Automatic hardware flow control is selected by setting bits 6 (RTS) and 7 (CTS) of the EFR register to a logic 1. If -CTS transitions from a logic 0 to a logic 1 indicating a flow control request, ISR bit5 will be set to a logic 1 (if enabled via IER bit 6-7), and the 654 will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the -CTS input returns to a logic 0, indicating more data may be sent. With the Auto RTS function enabled, an interrupt is generated when the receive FIFO reaches the programmed trigger level. The -RTS pin will not be forced to a logic 1 (RTS Off), until the receive FIFO reaches the next trigger level. However, the -RTS pin will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the programmed trigger. However, under the above described conditions the 654 will continue to accept data until the receive FIFO is full. Selected Trigger Level (characters) INT Pin Activation -RTS Logic 1 (characters) -RTS Logic 0 (characters) 8 16 56 60 8 16 56 60 16 56 60 60 0 8 16 56 Rev. 4.30 16 ST16C654/654D ST16C654/654D Software Flow Control Special Feature Software Flow Control When software flow control is enabled, the 654 compares one or two sequential receive data characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the 654 will halt transmission (TX) as soon as the current character(s) has completed transmission. When a match occurs, the receive ready (if enabled via Xoff IER bit-5) flags will be set and the interrupt output pin (if receive interrupt is enabled) will be activated. Following a suspension due to a match of the Xoff characters values, the 654 will monitor the receive data stream for a match to the Xon-1,2 character value(s). If a match is found, the 654 will resume operation and clear the flags (ISR bit4). The 654 offers a special Xon mode via MCR bit-5. The initialized default setting of MCR bit-5 is a logic 0. In this state Xoff and Xon will operate as defined above. Setting MCR bit-5 to a logic 1 sets a special operational mode for the Xon function. In this case Xoff operates normally however, transmission (Xon) will resume with the next character received, i.e., a match is declared simply by the receipt of an incoming (RX) character. A special feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced Feature Register (EFR). When 8 bit character is detected, it will be placed on the user accessible data stack along with normal incoming RX data. This condition is selected in conjunction with EFR bits 0-3. Note that software flow control should be turned off when using this special mode by setting EFR bit 0-3 to a logic 0. Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff characters and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected, the 654 compares two consecutive receive characters with two software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO. Xon Any Feature The 654 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character (see Figure 9). Although the Internal Register Table shows each XRegister with eight bits of character information, the actual number of bits is dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also determines the number of bits that will be used for the special character comparison. Bit-0 in the X-registers corresponds with the LSB bit for the receive character. A special feature is provided to return the Xoff flow control to the inactive state following its activation. In this mode any RX character received will return the Xoff flow control to the inactive state so that transmissions may be resumed with a remote buffer. This feature is more fully defined in the Software Flow Control section. Hardware/Software and Timeout Interrupts Three special interrupts have been added to monitor the hardware and software flow control. The interrupts are enabled by IER bits 5-7. Care must be taken when handling these interrupts. Following a reset the transmitter interrupt is enabled, the 654 will issue an interrupt to indicate that transmit holding register is empty. This interrupt must be serviced prior to continuing operations. The LSR register provides the current singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have lowest interrupt priority. A condition can exist where a higher In the event that the receive buffer is overfilling and flow control needs to be executed, the 654 automatically sends an Xoff message (when enabled) via the serial TX output to the remote modem. The 654 sends the Xoff-1,2 characters as soon as received data passes the programmed trigger level. To clear this condition, the 654 will transmit the programmed Xon1,2 characters as soon as receive data drops below the programmed trigger level. Rev. 4.30 17 ST16C654/654D ST16C654/654D interface pin is left open or made a logic 0, MCR bit3 controls the three state interrupt outputs, INT A-D. When INTSEL is a logic 1, MCR bit-3 has no effect on the INT A-D outputs and the package operates with interrupt outputs enabled continuously. priority interrupt may mask the lower priority CTS/ RTS interrupt(s). Only after servicing the higher pending interrupt will the lower priority CTS/ RTS interrupt(s) be reflected in the status register. Servicing the interrupt without investigating further interrupt conditions can result in data errors. Programmable Baud Rate Generator When two interrupt conditions have the same priority, it is important to service these interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt priority (when enabled by IER bit-3). The receiver issues an interrupt after the number of characters have reached the programmed trigger level. In this case the 654 FIFO may hold more characters than the programmed trigger level. Following the removal of a data byte, the user should recheck LSR bit-0 for additional characters. A Receive Time Out will not occur if the receive FIFO is empty. The time out counter is reset at the center of each stop bit received or each time the receive holding register (RHR) is read. The actual time out value is T (Time out length in bits) = 4 X P (Programmed word length) + 12. To convert the time out value to a character value, the user has to consider the complete word length, including data information length, start bit, parity bit, and the size of stop bit, i.e., 1X, 1.5X, or 2X bit times. The 654 supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example a 33.6Kbps modem that employs data compression may require a 115.2Kbps input data rate. A 128.0Kbps ISDN modem that supports data compression may need an input data rate of 460.8Kbps. The 654 can support a standard data rate of 921.6Kbps. Single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel control. The programmable Baud Rate Generator is capable of accepting an input clock up to 24 MHz, as required for supporting a 1.5Mbps data rate. The 654 can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal (parallel resonant/ 22-33 pF load) is connected externally between the XTAL1 and XTAL2 pins (see figure ). Alternatively, an external clock can be connected to Example -A: If the user programs a word length of 7, with no parity and one stop bit, the time out will be: T = 4 X 7( programmed word length) +12 = 40 bit times. The character time will be equal to 40 / 9 = 4.4 characters, or as shown in the fully worked out example: T = [(programmed word length = 7) + (stop bit = 1) + (start bit = 1) = 9]. 40 (bit times divided by 9) = 4.4 characters. XTAL1 Example -B: If the user programs the word length = 7, with parity and one stop bit, the time out will be: T = 4 X 7(programmed word length) + 12 = 40 bit times. Character time = 40 / 10 [ (programmed word length = 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4 characters. XTAL2 Figure 8, Crystal oscillator connection X1 1.8432 MHz In the 16 mode for 68/100 pin packages, the system/ board designer can optionally provide software controlled three state interrupt operation. This is accomplished by INTSEL and MCR bit-3. When INTSEL C1 22pF Rev. 4.30 18 C2 33pF ST16C654/654D ST16C654/654D the XTAL1 pin to clock the internal baud rate generator for standard or custom rates. (see Baud Rate Generator Programming). rate selection during initialization, the rate tables can be changed by the internal register, MCR bit-7. Setting MCR bit-7 to a logic 1 when CLKSEL is a logic 1 provides an additional divide by 4 whereas, setting MCR bit-7 to a logic 0 only divides by 1. (See Table 5 and Figure 11). Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator. The generator divides the input 16X clock by any divisor from 1 to 216 -1. The 654 divides the basic crystal or external clock by 16. Further division of this 16X clock provides two table rates to support low and high data rate applications using the same system design. After a hardware reset and during initialization, the 654 sets the default baud rate table according to the state of the CLKSEL. pin. A logic 1 on CLKSEL will set the 1X clock default whereas, logic 0 will set the 4X clock default table. Following the default clock Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in Table 5 below, shows the two selectable baud rate tables available when using a 7.3728 MHz crystal. Table 5, BAUD RATE GENERATOR PROGRAMMING TABLE (7.3728 MHz CLOCK): Output Baud Rate MCR BIT-7=1 Output Baud Rate MCR Bit-7=0 User 16 x Clock Divisor (Decimal) User 16 x Clock Divisor (HEX) DLM Program Value (HEX) DLL Program Value (HEX) 50 300 600 1200 2400 4800 9600 19.2k 38.4k 57.6k 115.2k 200 1200 2400 4800 9600 19.2K 38.4k 76.8k 153.6k 230.4k 460.8k 2304 384 192 96 48 24 12 6 3 2 1 900 180 C0 60 30 18 0C 06 03 02 01 09 01 00 00 00 00 00 00 00 00 00 00 80 C0 60 30 18 0C 06 03 02 01 Rev. 4.30 19 ST16C654/654D ST16C654/654D Figure 11, Baud Rate Generator Circuitry XTAL1 XTAL2 Clock Oscillator Logic MCR Bit-7=0 Divide by 1 logic Baudrate Generator Logic Divide by 4 logic MCR Bit-7=1 Rev. 4.30 20 -BAUDOUT ST16C654/654D ST16C654/654D DMA Operation (bits 3/2) control the modem -RI and -CD inputs respectively. MCR signals -DTR and -RTS (bits 0-1) are used to control the modem -CTS and -DSR inputs respectively. The transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally (See Figure 12). The -CTS, -DSR, CD, and -RI are disconnected from their normal modem control inputs pins, and instead are connected internally to -DTR, -RTS, -OP1 and -OP2. Loop-back test data is entered into the transmit holding register via the user data bus interface, D0-D7. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loop-back connection. The receive UART converts the serial data back into parallel data that is then made available at the user data interface, D0-D7. The user optionally compares the received data to the initial transmitted data for verifying error free operation of the UART TX/RX circuits. The 654 FIFO trigger level provides additional flexibility to the user for block mode operation. LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s). The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR bit-3). When the transmit and receive FIFOs are enabled and the DMA mode is deactivated (DMA Mode 0), the 654 activates the interrupt output pin for each data transmit or receive operation. When DMA mode is activated (DMA Mode 1), the user takes the advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the preset trigger level. In this mode, the 654 sets the interrupt output pin when characters in the transmit FIFOs are below the transmit trigger level, or the characters in the receive FIFOs are above the receive trigger level. Sleep Mode In this mode, the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational. However, the interrupts can only be read using lower four bits of the Modem Control Register (MCR bits 0-3) instead of the four Modem Status Register bits 4-7. The interrupts are still controlled by the IER. The 654 is designed to operate with low power consumption. A special sleep mode is included to further reduce power consumption when the chip is not being used. With EFR bit-4 and IER bit-4 enabled (set to a logic 1), the 654 enters the sleep mode but resumes normal operation when a start bit is detected, a change of state on any of the modem input pins RX, -RI, -CTS, -DSR, -CD, or transmit data is provided by the user. If the sleep mode is enabled and the 654 is awakened by one of the conditions described above, it will return to the sleep mode automatically after the last character is transmitted or read by the user. In any case, the sleep mode will not be entered while an interrupt(s) is pending. The 654 will stay in the sleep mode of operation until it is disabled by setting IER bit-4 to a logic 0. Loop-back Mode The internal loop-back capability allows onboard diagnostics. In the loop-back mode the normal modem interface pins are disconnected and reconfigured for loop-back internally. MCR register bits 0-3 are used for controlling loop-back diagnostic testing. In the loop-back mode OP1 and OP2 in the MCR register Rev. 4.30 21 ST16C654/654D ST16C654/654D Figure 12, INTERNAL LOOP-BACK MODE DIAGRAM Flow Control Logic I n te r C o n n e c t B u s L in e s & C o n tr o l s ig n a ls Receive Shift Register RX A-D Ir Decoder -CD A-D -DTR A-D Modem Control Logic XTAL1 XTAL2 Ir Encoder -RTS A-D Interrupt Control Logic INT A-D -RXRDY -TXRDY Flow Control Logic Clock & Baud Rate Generator A0-A2 -CS A-D Register Select Logic Receive FIFO Registers TX A-D Transmit Shift Register MCR Bit-4=1 Data bus & Control Logic D0-D7 -IOR,-IOW RESET Transmit FIFO Registers -RI A-D -OP1 A-D -DSR A-D -OP2 A-D -CTS A-D Rev. 4.30 22 ST16C654/654D ST16C654/654D REGISTER FUNCTIONAL DESCRIPTIONS assigned bit functions are more fully defined in the following paragraphs. The following table delineates the assigned bit functions for the fifteen 654 internal registers. The Table 6, ST16C654 ST16C654 INTERNAL REGISTERS A2 A1 A0 Register [Default] Note *5 BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 General Register Set 0 0 0 RHR[XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 THR[XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 IER CTS interrupt RTS interrupt Xoff interrupt Sleep mode modem status interrupt receive line status interrupt transmit holding register receive holding register 0 1 0 FCR RCVR trigger (MSB) RCVR trigger (LSB) TX trigger (MSB) TX trigger (LSB) DMA mode select XMIT FIFO reset RCVR FIFO r eset FIFO enable 0 1 0 ISR FIFOs enabled FIFOs enabled INT priority bit-4 INT priority bit-3 INT priority bit-2 INT priority bit-1 INT priority bit-0 INT status 0 1 1 LCR divisor latch enable set break set parity even parity parity enable stop bits word length bit-1 word length bit-0 1 0 0 MCR Clock select IR enable Xon Any loop back -OP2/ INTx enable -OP1 -RTS -DTR 1 0 1 LSR FIFO data error trans. empty trans. holding empty break interrupt framing error parity error overrun error receive data ready 1 1 0 MSR[X0] CD RI DSR CTS delta -CD delta -RI delta -DSR delta -CTS 1 1 1 SPR[FF] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 Special Register set: Note *2 0 0 0 DLL[XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 DLM[XX] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 Rev. 4.30 23 ST16C654/654D ST16C654/654D A2 A1 A0 Register [Note *5] BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 Enhanced Register Set: Note *3 0 1 0 EFR Auto CTS Auto RTS Special Char. select Enable IER Bits 4-7, ISR, FCR Bits 4-5, MCR Bits 5-7 Cont-3 Tx,Rx Control Cont-2 Tx,Rx Control Cont-1 Tx,Rx Control Cont-0 Tx,Rx Control 1 1 1 1 0 0 1 1 0 1 0 1 Xon-1 Xon-2 Xoff-1 Xoff-2 bit-7 bit-15 bit-7 bit-15 bit-6 bit-14 bit-6 bit-14 bit-5 bit-13 bit-5 bit-13 bit-4 bit-12 bit-4 bit-12 bit-3 bit-11 bit-3 bit-11 bit-2 bit-10 bit-2 bit-10 bit-1 bit-9 bit-1 bit-9 bit-0 bit-8 bit-0 bit-8 RXRDY C RXRDY B RXRDY A TXRDY D TXRDY C TXRDY B TXRDY A FIFO Ready Register: Note *4 X Note *2: Note *3: Note *4: Note *5: X X FIFORdy RXRDY D The Special register set is accessible only when LCR bit-7 is set to 1. Enhanced Feature Register, Xon 1,2 and Xoff 1,2 are accessible only when LCR is set to BFHex FIFORdy register is available only in 100 pin QFP packages and is selected by -CSRDY vice A0-A2. The value between the square brackets represents the registers initialized HEX value. Rev. 4.30 24 ST16C654/654D ST16C654/654D Transmit (THR) and Receive (RHR) Holding Registers FIFO drops below the programmed trigger level. B) FIFO status will also be reflected in the user accessible ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to the THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR. Note that a write operation can be performed when the transmit holding register empty flag is set (logic 0 = FIFO full, logic 1= at least one FIFO location available). C) The data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty. IER Vs Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1; resetting IER bits 0-3 enables the 654 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). The serial receive section also contains an 8-bit Receive Holding Register, RHR. Receive data is removed from the 654 and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at 16x clock rate. After 7 1/2 clocks the start bit time should be shifted to the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. Receiver status codes will be posted in the LSR. A) LSR BIT-0 will be a logic 1 as long as there is one byte in the receive FIFO. B) LSR BIT 1-4 will provide the type of errors encountered, if any. C) LSR BIT-5 will indicate when the transmit FIFO is empty. Interrupt Enable Register (IER) D) LSR BIT-6 will indicate when both the transmit FIFO and transmit shift register are empty. The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. These interrupts would normally be seen on the INT A-D output pins in the 16 mode, or on WIRE-OR IRQ output pin, in the 68 mode. E) LSR BIT-7 will indicate any FIFO data errors. When the receive FIFO (FCR BIT-0 = a logic 1) and receive interrupts (IER BIT-0 = logic 1) are enabled, the receive interrupts and register status will reflect the following: IER BIT-0: This interrupt will be issued when the FIFO has reached the programmed trigger level or is cleared when the FIFO drops below the trigger level in the FIFO mode of operation. Logic 0 = Disable the receiver ready interrupt. (normal default condition) Logic 1 = Enable the receiver ready interrupt. A) The receive data available interrupts are issued to the external CPU when the FIFO has reached the programmed trigger level. It will be cleared when the IER BIT-1: This interrupt will be issued whenever the THR is empty and is associated with bit-1 in the LSR register. IER Vs Receive FIFO Interrupt Mode Operation Rev. 4.30 25 ST16C654/654D ST16C654/654D FIFO Control Register (FCR) Logic 0 = Disable the transmitter empty interrupt. (normal default condition) Logic 1 = Enable the transmitter empty interrupt. IER BIT-2: This interrupt will be issued whenever a fully assembled receive character is transferred from the RSR to the RHR/FIFO, i.e., data ready, LSR bit-0. Logic 0 = Disable the receiver line status interrupt. (normal default condition) Logic 1 = Enable the receiver line status interrupt. This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode. The DMA, and FIFO modes are defined as follows: DMA MODE Mode 0 Set and enable the interrupt for each single transmit or receive operation, and is similar to the ST16C454 ST16C454 mode. Transmit Ready (-TXRDY) will go to a logic 0 when ever an empty transmit space is available in the Transmit Holding Register (THR). Receive Ready (-RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with a character. Mode 1 Set and enable the interrupt in a block mode operation. The transmit interrupt is set when the transmit FIFO is below the programmed trigger level. -TXRDY remains a logic 0 as long as one empty FIFO location is available. The receive interrupt is set when the receive FIFO fills to the programmed trigger level. However the FIFO continues to fill regardless of the programmed level until the FIFO is full. -RXRDY remains a logic 0 as long as the FIFO fill level is above the programmed trigger level. IER BIT-3: Logic 0 = Disable the modem status register interrupt. (normal default condition) Logic 1 = Enable the modem status register interrupt. IER BIT -4: Logic 0 = Disable sleep mode. (normal default condition) Logic 1 = Enable sleep mode. See Sleep Mode section for details. IER BIT-5: Logic 0 = Disable the software flow control, receive Xoff interrupt. (normal default condition) Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for details. FCR BIT-0: Logic 0 = Disable the transmit and receive FIFO. (normal default condition) Logic 1 = Enable the transmit and receive FIFO. This bit must be a 1 when other FCR bits are written to or they will not be programmed. IER BIT-6: Logic 0 = Disable the RTS interrupt. (normal default condition) Logic 1 = Enable the RTS interrupt. The 654 issues an interrupt when the RTS pin transitions from a logic 0 to a logic 1. FCR BIT-1: Logic 0 = No FIFO receive reset. (normal default condition) Logic 1 = Clears the contents of the receive FIFO and resets the FIFO counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. IER BIT-7: Logic 0 = Disable the CTS interrupt. (normal default condition) Logic 1 = Enable the CTS interrupt. The 654 issues an interrupt when CTS pin transitions from a logic 0 to a logic 1. FCR BIT-2: Logic 0 = No FIFO transmit reset. (normal default condition) Logic 1 = Clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. Rev. 4.30 26 ST16C654/654D ST16C654/654D FCR BIT-3: Logic 0 = Set DMA mode 0. (normal default condition) Logic 1 = Set DMA mode 1. BIT-5 TX FIFO trigger level 0 0 1 1 Transmit operation in mode 0: When the 654 is in the ST16C450 ST16C450 mode (FIFOs disabled, FCR bit-0 = logic 0) or in the FIFO mode (FIFOs enabled, FCR bit-0 = logic 1, FCR bit-3 = logic 0) and when there are no characters in the transmit FIFO or transmit holding register, the -TXRDY pin will be a logic 0. Once active the -TXRDY pin will go to a logic 1 after the first character is loaded into the transmit holding register. BIT-4 0 1 0 1 8 16 32 56 FCR BIT 6-7: (logic 0 or cleared is the default condition, Rx trigger level = 8) These bits are used to set the trigger level for the receive FIFO interrupt. Receive operation in mode 0: When the 654 is in mode 0 (FCR bit-0 = logic 0) or in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = logic 0) and there is at least one character in the receive FIFO, the -RXRDY pin will be a logic 0. Once active the -RXRDY pin will go to a logic 1 when there are no more characters in the receiver. An interrupt is generated when the number of characters in the FIFO equals the programmed trigger level. However the FIFO will continue to be loaded until it is full. BIT-7 Receive operation in mode 1: When the 654 is in FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = logic 1) and the trigger level has been reached, or a Receive Time Out has occurred, the RXRDY pin will go to a logic 0. Once activated, it will go to a logic 1 after there are no more characters in the FIFO. RX FIFO trigger level 0 0 1 1 Transmit operation in mode 1: When the 654 is in FIFO mode ( FCR bit-0 = logic 1, FCR bit-3 = logic 1 ), the -TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty. BIT-6 0 1 0 1 8 16 56 60 Interrupt Status Register (ISR) The 654 provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is cleared. However it should be noted that only the current pending interrupt is cleared by the read. A lower level interrupt may be seen after rereading the interrupt status bits. The Interrupt Source Table 7 (below) shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels: FCR BIT 4-5: (logic 0 or cleared is the default condition, TX trigger level = 8) These bits are used to set the trigger level for the transmit FIFO interrupt. The ST16C654 ST16C654 will issue a transmit empty interrupt when the number of characters in FIFO drops below the selected trigger level. Rev. 4.30 27 ST16C654/654D ST16C654/654D Table 7, INTERRUPT SOURCE TABLE Priority Level 1 2 2 3 4 5 6 [ ISR BITS ] Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 Source of the interrupt 0 0 0 0 0 0 0 LSR (Receiver Line Status Register) RXRDY (Received Data Ready) RXRDY (Receive Data time out) TXRDY ( Transmitter Holding Register Empty) MSR (Modem Status Register) RXRDY (Received Xoff signal)/ Special character CTS, RTS change of state ISR BIT-0: Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. Logic 1 = No interrupt pending. (normal default condition) LCR BIT 0-1: (logic 0 or cleared is the default condition) These two bits specify the word length to be transmitted or received. BIT-1 ISR BIT 4-5: (logic 0 or cleared is the default condition) These bits are enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that matching Xoff character(s) have been detected. ISR bit-5 indicates that CTS, RTS have been generated. Note that once set to a logic 1, the ISR bit-4 will stay a logic 1 until Xon character(s) are received. BIT-0 Word length 0 0 1 1 ISR BIT 1-3: (logic 0 or cleared is the default condition) These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (See Interrupt Source Table). 0 1 0 1 5 6 7 8 LCR BIT-2: (logic 0 or cleared is the default condition) The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT-2 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Rev. 4.30 28 Word length Stop bit length (Bit time(s) 0 1 1 ISR BIT 6-7: (logic 0 or cleared is the default condition) These bits are set to a logic 0 when the FIFO is not being used. They are set to a logic 1 when the FIFOs are enabled. 5,6,7,8 5 6,7,8 1 1-1/2 2 ST16C654/654D ST16C654/654D LCR BIT-3: Parity or no parity can be selected via this bit. Logic 0 = No parity. (normal default condition) Logic 1 = A parity bit is generated during the transmission, receiver checks the data and parity for transmission errors. Logic 1 = Forces the transmitter output (TX) to a logic 0 for alerting the remote receiver to a line break condition. LCR BIT-7: The internal baud rate counter latch and Enhance Feature mode enable. Logic 0 = Divisor latch disabled. (normal default condition) Logic 1 = Divisor latch and enhanced feature register enabled. LCR BIT-4: If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format. Logic 0 = ODD Parity is generated by forcing an odd number of logic 1s in the transmitted data. The receiver must be programmed to check the same format. (normal default condition) Logic 1 = EVEN Parity is generated by forcing an even the number of logic 1s in the transmitted. The receiver must be programmed to check the same format. Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. MCR BIT-0: Logic 0 = Force -DTR output to a logic 1. (normal default condition) Logic 1 = Force -DTR output to a logic 0. LCR BIT-5: If the parity bit is enabled, LCR BIT-5 selects the forced parity format. LCR BIT-5 = logic 0, parity is not forced. (normal default condition) LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. LCR Bit-5 LCR Bit-4 LCR Bit-3 X 0 1 0 1 0 1 1 1 1 MCR BIT-2: This bit is used in the Loop-back mode only. In the loop-back mode this bit is use to write the state of the modem -RI interface signal via -OP1. Parity selection X 0 0 1 1 MCR BIT-1: Logic 0 = Force -RTS output to a logic 1. (normal default condition) Logic 1 = Force -RTS output to a logic 0. Automatic RTS may be used for hardware flow control by enabling EFR bit-6 (See EFR bit-6). No parity Odd parity Even parity Force parity 1 Forced parity 0 MCR BIT-3: (Used to control the modem -CD signal in the loop-back mode.) Logic 0 = Forces INT (A-D) outputs to the three state mode during the 16 mode. (normal default condition) In the Loop-back mode, sets -OP2 (-CD) internally to a logic 1. Logic 1 = Forces the INT (A-D) outputs to the active mode during the 16 mode. In the Loop-back mode, sets -OP2 (-CD) internally to a logic 0. LCR BIT-6: When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state). This condition exists until disabled by setting LCR bit-6 to a logic 0. Logic 0 = No TX break condition. (normal default condition) MCR BIT-4: Logic 0 = Disable loop-back mode. (normal default condition) Logic 1 = Enable local loop-back mode (diagnostics). Rev. 4.30 29 ST16C654/654D ST16C654/654D MCR BIT-5: Logic 0 = Disable Xon any function (for 16C550 16C550 compatibility). (normal default condition) Logic 1 = Enable Xon any function. In this mode any RX character received will enable Xon. therefore the data in the FIFO is not corrupted by the error. LSR BIT-2: Logic 0 = No parity error. (normal default condition) Logic 1 = Parity error. The receive character does not have correct parity information and is suspect. In the FIFO mode, this error is associated with the character at the top of the FIFO. MCR BIT-6: Logic 0 = Enable the standard modem receive and transmit input/output interface. (normal default condition) Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the TX/RX output/ Inputs are routed to the infrared encoder/decoder. The data input and output levels will conform to the IrDA infrared interface requirement. As such, while in this mode the infrared TX output will be a logic 0 during idle data conditions. LSR BIT-3: Logic 0 = No framing error. (normal default condition) Logic 1 = Framing error. The receive character did not have a valid stop bit(s). In the FIFO mode this error is associated with the character at the top of the FIFO. LSR BIT-4: Logic 0 = No break condition. (normal default condition) Logic 1 = The receiver received a break signal (RX was a logic 0 for one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. MCR BIT-7: Logic 0 = Divide by one. The input clock (crystal or external) is divided by sixteen and then presented to the Programmable Baud Rate Generator (BGR) without further modification, i.e., divide by one. (normal, default condition) Logic 1 = Divide by four. The divide by one clock described in MCR bit-7 equals a logic 0, is further divided by four (also see Programmable Baud Rate Generator section). LSR BIT-5: This bit is the Transmit Holding Register Empty indicator. This bit indicates that the UART is ready to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to CPU when the THR interrupt enable is set. The THR bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. The bit is reset to logic 0 concurrently with the loading of the transmitter holding register by the CPU. In the FIFO mode this bit is set when the transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO. Line Status Register (LSR) This register provides the status of data transfers between. the 654 and the CPU. LSR BIT-0: Logic 0 = No data in receive holding register or FIFO. (normal default condition) Logic 1 = Data has been received and is saved in the receive holding register or FIFO. LSR BIT-6: This bit is the Transmit Empty indicator. This bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. It is reset to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to one whenever the transmit FIFO and transmit shift register are both empty. LSR BIT-1: Logic 0 = No overrun error. (normal default condition) Logic 1 = Overrun error. A data overrun error occurred in the receive shift register. This happens when additional data arrives while the FIFO is full. In this case the previous data in the shift register is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the FIFO, Rev. 4.30 30 ST16C654/654D ST16C654/654D LSR BIT-7: Logic 0 = No Error. (normal default condition) Logic 1 = At least one parity error, framing error or break indication is in the current FIFO data. This bit is cleared when LSR register is read. Flow control (when enabled) allows the starting and stopping the transmissions based on the external modem -CTS signal. A logic 1 at the -CTS pin will stop 654 transmissions as soon as current character has finished transmission. Modem Status Register (MSR) Normally MSR bit-4 bit is the compliment of the -CTS input. However in the loop-back mode, this bit is equivalent to the RTS bit in the MCR register. This register provides the current state of the control interface signals from the modem, or other peripheral device that the 654 is connected to. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register. MSR BIT-5: DSR (active high, logical 1). Normally this bit is the compliment of the -DSR input. In the loop-back mode, this bit is equivalent to the DTR bit in the MCR register. MSR BIT-6: RI (active high, logical 1). Normally this bit is the compliment of the -RI input. In the loop-back mode this bit is equivalent to the OP1 bit in the MCR register. MSR BIT-0: Logic 0 = No -CTS Change (normal default condition) Logic 1 = The -CTS input to the 654 has changed state since the last time it was read. A modem Status Interrupt will be generated. MSR BIT-7: CD (active high, logical 1). Normally this bit is the compliment of the -CD input. In the loop-back mode this bit is equivalent to the OP2 bit in the MCR register. MSR BIT-1: Logic 0 = No -DSR Change. (normal default condition) Logic 1 = The -DSR input to the 654 has changed state since the last time it was read. A modem Status Interrupt will be generated. Scratchpad Register (SPR) The ST16C654 ST16C654 provides a temporary data register to store 8 bits of user information. MSR BIT-2: Logic 0 = No -RI Change. (normal default condition) Logic 1 = The -RI input to the 654 has changed from a logic 0 to a logic 1. A modem Status Interrupt will be generated. Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits-0 through 4 provide single or dual character software flow control selection. When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential characters. MSR BIT-3: Logic 0 = No -CD Change. (normal default condition) Logic 1 = Indicates that the -CD input to the has changed state since the last time it was read. A modem Status Interrupt will be generated. EFR BIT 0-3: (logic 0 or cleared is the default condition) Combinations of software flow control can be selected by programming these bits. MSR BIT-4: -CTS functions as hardware flow control signal input if it is enabled via EFR bit-7. The transmit holding register flow control is enabled/disabled by MSR bit-4. Rev. 4.30 31 ST16C654/654D ST16C654/654D Table 8, SOFTWARE FLOW CONTROL FUNCTIONS Cont-3 Cont-2 Cont-1 Cont-0 0 1 0 1 X X X 1 0 0 1 1 X X X 0 X X X X 0 1 0 1 X X X X 0 0 1 1 0 1 1 1 1 1 1 1 0 0 1 1 TX, RX software flow controls No transmit flow control Transmit Xon1/Xoff1 Transmit Xon2/Xoff2 Transmit Xon1 and Xon2/Xoff1 and Xoff2 No receive flow control Receiver compares Xon1/Xoff1 Receiver compares Xon2/Xoff2 Transmit Xon1/ Xoff1. Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 Transmit Xon2/Xoff2 Receiver compares Xon1 and Xon2/Xoff1 and Xoff2 Transmit Xon1 and Xon2/Xoff1 and Xoff2 Receiver compares Xon1 and Xon2/Xoff1 and Xoff2 No transmit flow control Receiver compares Xon1 and Xon2/Xoff1 and Xoff2 EFR BIT-4: Enhanced function control bit. The content of the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 can be modified and latched. After modifying any bits in the enhanced registers, EFR bit-4 can be set to a logic 0 to latch the new values. This feature prevents existing software from altering or overwriting the 654 enhanced functions. EFR BIT-5: Logic 0 = Special Character Detect Disabled. (normal default condition) Logic 1 = Special Character Detect Enabled. The 654 compares each incoming receive character with Xoff2 data. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Bit-0 in the X-registers corresponds with the LSB bit for the receive character. When this feature is enabled, the normal software flow control must be disabled (EFR bits 0-3 must be set to a logic 0). Logic 0 = disable/latch enhanced features. IER bits 47, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are saved to retain the user settings, then IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are initialized to the default values shown in the Internal Resister Table. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are set to a logic 0 to be compatible with ST16C554 ST16C554 mode. (normal default condition). Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1 all enhanced features of the 654 are enabled and user settings stored during a reset will be restored. EFR BIT-6: Automatic RTS may be used for hardware flow control by enabling EFR bit-6. When AUTO RTS is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and -RTS will go to a logic 1 at the next trigger level. -RTS will return to a logic 0 when data is unloaded below the next lower trigger level (Programmed trigger level -1). The state of this register bit changes with the status of the hardware flow control. -RTS functions normally when hardware flow control is disabled. Rev. 4.30 32 ST16C654/654D ST16C654/654D ST16C654 ST16C654 EXTERNAL RESET CONDITIONS 0 = Automatic RTS flow control is disabled. (normal default condition) 1 = Enable Automatic RTS flow control. REGISTERS IER ISR LCR MCR LSR FCR EFR IER BITS 0-7=0 ISR BIT-0=1, ISR BITS 1-7=0 LCR BITS 0-7=0 MCR BITS 0-7=0 LSR BITS 0-4=0, LSR BITS 5-6=1 LSR, BIT 7=0 MSR BITS 0-3=0, MSR BITS 4-7= input signals FCR BITS 0-7=0 EFR BITS 0-7=0 SIGNALS RESET STATE TX A-D -RTS A-D -DTR A-D -RXRDY A-D -TXRDY A-D EFR bit-7: Automatic CTS Flow Control. Logic 0 = Automatic CTS flow control is disabled. (normal default condition) Logic 1 = Enable Automatic CTS flow control. Transmission will stop when -CTS goes to a logical 1. Transmission will resume when the -CTS pin returns to a logical 0. RESET STATE High High High High Low MSR FIFO READY REGISTER This register is applicable to 100 pin ST16C654s only. The FIFO resister provides the real-time status of the transmit and receive FIFOs. Each TX and RX cannel (A-D) has its own 64 byte FIFO. When any of the eight TX/RX FIFOs become full, a bit associated with its TX/RX function and channel A-D is set in the FIFO status register. FIFO channel A-D RDY Bit 0-3: 0 = The transmit FIFO A-D associated with this bit is full. This channel will not accept any more transmit data. 1 = One or more empty locations exist in the FIFO. FIFORdy Bit 4-7: 0 = The receive FIFO is above the programmed trigger level or time-out is occurred. 1 = Receiver is ready and is below the programmed trigger level. Rev. 4.30 33 ST16C654/654D ST16C654/654D AC ELECTRICAL CHARACTERISTICS TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. Symbol T1w,T2w T3w T 6s T7d T7w T7h T9d T12d T12h T13d T13w T13h T15d T16s T16h T17d T18d T19d T20d T21d T22d T23d T24d T25d T26d T27d T28d T30s T30w T30h T30d T31d T31h T32s T32h T32d T33s Parameter Clock pulse duration Oscillator/Clock frequency Address setup time -IOR delay from chip select -IOR strobe width Chip select hold time from -IOR Read cycle delay Delay from -IOR to data Data disable time -IOW delay from chip select -IOW strobe width Chip select hold time from -IOW Write cycle delay Data setup time Data hold time Delay from -IOW to output Delay to set interrupt from MODEM input Delay to reset interrupt from -IOR Delay from stop to set interrupt Delay from -IOR to reset interrupt Delay from stop to interrupt Delay from initial INT reset to transmit start Delay from -IOW to reset interrupt Delay from stop to set -RxRdy Delay from -IOR to reset -RxRdy Delay from -IOW to set -TxRdy Delay from start to reset -TxRdy Address setup time Chip select strobe width Address hold time Read cycle delay Delay from -CS to data Data disable time Write strobe setup time Write strobe hold time Write cycle delay Data setup time Limits 3.3 Min Max 17 Limits 5.0 Min Max 17 5 10 35 0 40 0 10 25 0 30 10 35 0 40 20 5 8 10 40 15 70 15 10 10 70 20 Rev. 4.30 34 8 35 25 50 40 40 1 45 45 24 45 1 45 45 8 35 10 25 0 30 15 5 8 10 40 15 70 15 15 10 10 70 15 Units 40 35 ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 35 1 40 40 24 ns Rclk ns ns Rclk 40 1 40 40 8 ns Rclk ns ns Rclk ns ns ns ns ns ns ns ns ns ns 24 25 15 Conditions 100 pF load 100 pF load 100 pF load 100 pF load ST16C654/654D ST16C654/654D AC ELECTRICAL CHARACTERISTICS TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. Symbol T33h TR N Parameter Data hold time Reset pulse width Baud rate devisor Limits 3.3 Min Max 10 40 1 Rev. 4.30 35 2 16-1 Limits 5.0 Min Max Units 10 40 1 ns ns Rclk 216-1 Conditions ST16C654/654D ST16C654/654D ABSOLUTE MAXIMUM RATINGS Supply range Voltage at any pin Operating temperature Storage temperature Package dissipation 7 Volts GND - 0.3 V to VCC +0.3 V -40° C to +85° C -65° C to 150° C 500 mW DC ELECTRICAL CHARACTERISTICS TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. Symbol VILCK VIHCK VIL VIH VOL VOL VOH VOH IIL ICL I CC CP RIN Parameter Clock input low level Clock input high level Input low level Input high level Output low level on all outputs Output low level on all outputs Output high level Output high level Input leakage Clock leakage Avg power supply current Input capacitance Internal pull-up resistance Limits 3.3 Min Max Limits 5.0 Min Max -0.3 2.4 -0.3 2.0 -0.5 3.0 -0.5 2.2 0.6 VCC 0.8 0.4 2.0 3 ±10 ±10 3 5 0.6 VCC 0.8 VCC 0.4 2.4 ±10 ±10 6 5 15 Units V V V V V V V V µA µA mA pF k Note: See the Symbol Description Table, for a listing of pins having internal pull-up resistors. Rev. 4.30 36 Conditions IOL = 5 mA IOL = 4 mA I OH= -5 mA I OH= -1 mA ST16C654/654D ST16C654/654D A0-A4 T30s T30h T30w T30d -CS T31h R/-W T31d D0-D7 8654-RD-1 8654-RD-1 General read timing in 68 mode A0-A4 T30s T30h -CS T32s T32h T30w T32d R/-W T33h T33s D0-D7 8654-WD-1 8654-WD-1 General write timing in 68 mode Rev. 4.30 37 ST16C654/654D ST16C654/654D Valid Address A0-A2 T6s Active -CS T7d T7w -IOR T7h T9d Active T12d T12h D0-D7 Data X654-RD-2 X654-RD-2 General write timing in 16 mode Valid Address A0-A2 T6s Active -CS T13d -IOW T13h T13w Active T16s D0-D7 T15d T16h Data X654-WD-2 X654-WD-2 General read timing in 16 mode Rev. 4.30 38 ST16C654/654D ST16C654/654D -IOW Active T17d -RTS -DTR Change of state Change of state -CD -CTS -DSR Change of state Change of state T18d T18d INT Active Active Active T19d Active -IOR Active Active T18d Change of state -RI X654-MD-1 X654-MD-1 Modem input/output timing T1w T2w EXTERNAL CLOCK X654-CK-1 X654-CK-1 T3w External clock timing Rev. 4.30 39 ST16C654/654D ST16C654/654D START BIT RX STOP BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 5 DATA BITS 6 DATA BITS 7 DATA BITS D6 D7 PARITY BIT NEXT DATA START BIT T20d Active INT T21d Active -IOR 16 BAUD RATE CLOCK Receive timing Rev. 4.30 40 X654-RX-1 X654-RX-1 ST16C654/654D ST16C654/654D START BIT RX STOP BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7 PARITY BIT NEXT DATA START BIT T25d Active Data Ready -RXRDY T26d -IOR Active X654-RX-2 X654-RX-2 Receive ready timing in none FIFO mode START BIT RX STOP BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7 PARITY BIT First byte that reaches the trigger level T25d Active Data Ready -RXRDY T26d -IOR Active X654-RX-3 X654-RX-3 Receive timing in FIFO mode Rev. 4.30 41 ST16C654/654D ST16C654/654D START BIT TX STOP BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 5 DATA BITS 6 DATA BITS 7 DATA BITS D6 D7 PARITY BIT NEXT DATA START BIT T22d Active Tx Ready INT T24d T23d -IOW Active Active 16 BAUD RATE CLOCK Transmit timing Rev. 4.30 42 X654-TX-1 X654-TX-1 ST16C654/654D ST16C654/654D START BIT TX STOP BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7 PARITY BIT -IOW D0-D7 NEXT DATA START BIT Active T28d BYTE #1 T27d -TXRDY Active Transmitter ready Transmitter not ready X654-TX-2 X654-TX-2 Transmit ready timing in none FIFO mode Rev. 4.30 43 ST16C654/654D ST16C654/654D START BIT DATA BITS (5-8) D0 TX D1 D2 D3 D4 STOP BIT D5 D6 5 DATA BITS D7 PARITY BIT 6 DATA BITS 7 DATA BITS -IOW Active T28d D0-D7 -TXRDY BYTE #64 T27d FIFO Full X654-TX-3 X654-TX-3 Transmit ready timing in FIFO mode Rev. 4.30 44 ST16C654/654D ST16C654/654D TX DATA 0 Stop Start UART Frame Data Bits 1 1 0 0 1 0 1 1 0 IRTX (A-D) TX 1/2 Bit Time Bit Time 3/16 Bit Time Infrared transmit timing IRRX (A-D) RX Bit Time 1 0 1 0 0 Data Bits 1 1 0 1 Stop 0 Start RX DATA 0-1 16x clock delay UART Frame X654-IR-1 X654-IR-1 Infrared receive timing Rev. 4.30 45 Package Dimensions Package Dimensions 64 LEAD THIN QUAD FLAT PACK (10 x 10 x 1.4 mm, TQFP) Rev. 2.00 D D1 48 33 49 32 D1 64 D 17 1 A2 16 B e C A Seating Plane A1 L INCHES SYMBOL A A1 A2 B C D D1 e L MIN MILLIMETERS MAX MIN 0.055 0.063 0.002 0.006 0.053 0.057 0.005 0.009 0.004 0.008 0.465 0.480 0.390 0.398 0.020 BSC 0.018 0.030 1.40 0.05 1.35 0.13 0.09 11.80 9.90 0° 7° MAX 1.60 0.15 1.45 0.23 0.20 12.20 10.10 0.50 BSC 0.45 0.75 0° Note: The control dimension is the millimeter column 7° Package Dimensions 68 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) Rev. 1.00 D C Seating Plane D1 45° x H1 A2 45° x H2 2 1 68 B1 B D D2 D3 D1 e R D3 A1 A INCHES SYMBOL MILLIMETERS MIN MAX MIN MAX A 0.165 0.200 4.19 5.08 A1 0.090 0.130 2.29 3.30 A2 0.020 . 0.51 B 0.013 0.021 0.33 0.53 B1 0.026 0.032 0.66 0.81 C 0.008 0.013 0.19 0.32 D 0.985 0.995 25.02 25.27 D1 0.950 0.958 24.13 24.33 D2 0.890 0.930 22.61 23.62 D3 e 0.800 typ. 0.050 BSC 20.32 typ. 1.27 BSC H1 0.042 0.056 1.07 1.42 H2 0.042 0.048 1.07 1.22 R 0.025 0.045 0.64 1.14 Note: The control dimension is the inch column NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1994 EXAR Corporation Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.