500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

SSTL-3

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: Integrated Circuit Systems, Inc. DATA SHEET ICS1524 ICS1524 Dual Output Phase Controlled SSTL_3/PECL Clock Generator Dual Output Phase Controlled SSTL_3/PECL Clock Generator General Description The , DPACLK. These two output channels have both 250 MHz PECL differential and 150 MHz SSTL_3 single-ended , range · 8 kHz to 100 MHz 250 MHz balanced PECL differential outputs 150 MHz single-ended SSTL_3 clock , upon by the customer is current and accurate. 2 IDTTM / ICSTM Dual Output Phase Controlled SSTL_3 Integrated Device Technology
Original
1523AN4 PSD01 ICS9148-53 SD0060CN02270T 199707558G
Abstract: ® White Paper MAX 7000B I/O MAX 7000B SDRAM GTL+SSTL-2 SSTL-3 I/O GTL+SSTL-2 SSTL-3 I/O LVCMOS LVTTL GTL+ PLD LVTTL I/O MAX 7000B I/O White Paper I/O I/O , http://www.altera.com Literature GTL+ SSTL-2 SSTL-3 Class I Class II M-WP-MAX7000B-01/J , Drivers 2 SSTL-2SSTL-3 Fairchild 1 2 3 4 5 6 7 20-bit SSTL-3 universal bus driver class I outputs 20-bit SSTL-3 universal bus driver class II outputs 20-bit SSTL-3 Altera
Original
GTLP16612 SN74GTLP1394 SN74GTLPH1612 SN74GTLPH1616 SN74GTLPH1645 SN74GTLPH16612 10EPM7256B 100-P 144-P 169-P 208-P 256-P
Abstract: ® 7000B device is the only product-term device capable of supporting the GTL+, SSTL-2, and SSTL-3 , , discrete I/O translators, buffers, drivers, and transceivers are used to convert GTL+, SSTL-2, or SSTL-3 , -2 and SSTL-3 drivers supporting outputs in the Class I and Class II standards. M-WP-MAX7000B , Corporation Using MAX 7000B Devices to Replace I/O Drivers Table 2. Part Numbers for SSTL-2 & SSTL-3 Drivers Number Description Part Numbers Fairchild 1 2 3 4 5 6 7 20-bit SSTL-3 Altera
Original
sstl lvttl Translator
Abstract: outputs · Up to 250 MHz · SSTL_3 Single-ended clock outputs · Up to 150 MHz · Dynamic Phase Adjust , differential (PECL) and single-ended (SSTL_3) high-speed clock outputs and the FUNC output. The ICS1523 has , FUNC The ICS1523 also has SSTL_3 (EIA/JESD8-8) and low-voltage PECL (Positive ECL) outputs , transition time. REF can be output on pin 14. The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs can be Integrated Device Technology
Original
ICS1523MLF 1523MLFT 734 coaxial cable data 132 kv gis MAN09 POWER TECH INC 1523MLF
Abstract: LVTTL 44 TSOP 1 1(400MIL) SSTL-3 NOW 50 TSOP I I (400MIL) 66/83/100 MHz SSTL-3 LVTTL SSTL-3 LVTTL SSTL-3 LVTTL SSTL-3 4K LVTTL SSTL-3 LVTTL SSTL-3 LVTTL SSTL-3 MHz 54 TSOP 1 1 (400MIL) NOW *NOTE LVTTL : Low Voltage Transistor Transistor Logic CTT : Center Tapped Termination SSTL-3 -
OCR Scan
gm72v16821 gm72v16821ct GMM2645233CTG GM72V16421CT 400M1L GM72V16821CT GM72V16421DT GM72V16821DT GM72V161621CT
Abstract: the GTL+, SSTL-2, and SSTL-3 standards used in processor interfaces, backplane drivers, and SDRAM , to convert GTL+, SSTL-2, or SSTL-3 signals to LVCMOS or to LVTTL before transferring these signals , www.altera.com. Table 1 lists the available GTL+ drivers and Table 2 lists the SSTL-2 and SSTL-3 drivers , GTLP8T306 transceiver GTLP8T306 SN74GTLPH306 GTLP6C816 Table 2. Part Numbers for SSTL-2 & SSTL-3 , 20-bit SSTL-3 universal bus driver class I outputs SN74SSTL16837A (2) 2 20-bit SSTL-3 Altera
Original
GTLP16T1655 AN-293-1
Abstract: the GTL+, SSTL-2, and SSTL-3 standards used in processor interfaces, backplane drivers, and SDRAM , to convert GTL+, SSTL-2, or SSTL-3 signals to LVCMOS or to LVTTL before transferring these signals , www.altera.com. Table 1 lists the available GTL+ drivers and Table 2 lists the SSTL-2 and SSTL-3 drivers , GTLP8T306 transceiver GTLP8T306 SN74GTLPH306 GTLP6C816 Table 2. Part Numbers for SSTL-2 & SSTL-3 , 20-bit SSTL-3 universal bus driver class I outputs SN74SSTL16837A (2) 2 20-bit SSTL-3 Altera
Original
altera EPM7032B
Abstract: -V VCCIO ) and SSTL-3 class II (3.3-V VCCIO ), use two separate I/O banks. Different I/O standards need , resistor (RS) for single-ended voltage-referenced I/O standard such as SSTL-2 and SSTL-3. The series , Supported I/O Standards SSTL-3 class I VCCIO (V) 3.3 SSTL-3 class II 3.3 SSTL-2 class I 2.5 , resistors. Parallel termination is supported for SSTL-2, SSTL-3, HSTL (class I and II), GTL, GTL+, and CTT , ) SSTL-3 class I N/A 50 3.3 SSTL-3 class II (1) 50 50 3.3 SSTL-2 class I N Altera
Original
800-EPLD
Abstract: frequency range · 15.734 kHz to 100 MHz · PECL differential outputs · Up to 250 MHz · SSTL_3 Single-ended , single-ended (SSTL_3) high-speed clock outputs and the FUNC output. The ICS1523 has the ability to operate in , . See 0x0:5. 1.14 Output Drivers The ICS1523 also has SSTL_3 (EIA/JESD8-8) and low-voltage PECL (Positive ECL) outputs, operating off the 3.3 V supply voltage. The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs Integrated Circuit Systems
Original
Abstract: voltage (VREF). · Voltage-referenced ­ GTL+, SSTL2 Classes I/II, SSTL3 Classes I/II, HSTL Class I , . SSTL3 SSTL3 is a 2.5V memory bus interface standard sponsored by IBM and Hitachi. There are two , 3.6 LVTTL, 3.3V PCI, LVPECL, GTL+, SSTL3 2.5 2.7 LVCMOS 2.5V, GTL+, SSTL2 1.7 1.8 , I SSTL2 Class I & II SSTL3 Class I & II LVDS (VREF=1.0V) LVDS (VREF , ), when VREF = 1.0V (GTL+ requirement). b) LVTTL can be used with 3.3V PCI/PCI-X, and SSTL3 Class I & II Actel
Original
AC182 IDTQS32X2384 JESD8-8 LVCMOS15 LVCMOS25
Abstract: outputs · Up to 250 MHz · SSTL_3 Single-ended clock outputs · Up to 150 MHz · Dynamic Phase Adjust , differential (PECL) and single-ended (SSTL_3) high-speed clock outputs and the FUNC output. The ICS1523 has , . 1.14 Output Drivers 1.8 Feedback Divider (FD) and FUNC The ICS1523 also has SSTL_3 (EIA/JESD8 , the FUNC output aligned. The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs can be operated Integrated Device Technology
Original
Abstract: SSTL_3 Single-ended clock outputs · Up to 150 MHz · Dynamic Phase Adjust (DPA) for all outputs · I2C , (SSTL_3) high-speed clock outputs and the FUNC output. The ICS1523 has the ability to operate in , then output on the FUNC pin. See Reg 0:5. The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs can be operated , VSYNC signals. 1.12 Output Drivers The ICS1523 also has SSTL_3 (EIA/JESD8-8) and low-voltage PECL Integrated Circuit Systems
Original
ICS1523M ICS1523MT
Abstract: outputs · Up to 250 MHz · SSTL_3 Single-ended clock outputs · Up to 150 MHz · Dynamic Phase Adjust , differential (PECL) and single-ended (SSTL_3) high-speed clock outputs and the FUNC output. The ICS1523 has , can be output on pin 14. The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs can be operated , such as most VESA compliant HSYNC and VSYNC signals. 1.12 Output Drivers The ICS1523 also has SSTL_3 Integrated Circuit Systems
Original
ICS1523MLFT
Abstract: outputs · Up to 250 MHz · SSTL_3 Single-ended clock outputs · Up to 150 MHz · Dynamic Phase Adjust , single-ended (SSTL_3) high-speed clock outputs and the FUNC output. The ICS1523 has the ability to operate in , most VESA compliant HSYNC and VSYNC signals. The ICS1523 also has SSTL_3 (EIA/JESD8-8) and , MDS 1523 X 1.11 OSC Input The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs can be operated Integrated Circuit Systems
Original
0000x0
Abstract: SSTL_3 Single-ended clock outputs · Up to 150 MHz · Dynamic Phase Adjust (DPA) for all outputs · I2C , occurs on all PLL outputs including the differential (PECL) and single-ended (SSTL_3) high-speed clock , output on the FUNC pin. See 0x0:5. 1.14 Output Drivers The ICS1523 also has SSTL_3 (EIA/JESD8-8) and low-voltage PECL (Positive ECL) outputs, operating off the 3.3 V supply voltage. The SSTL_3 and differential , SSTL_3 outputs can be operated unterminated. See Section 9, "Output Termination" 1.15 Power-On Reset Integrated Device Technology
Original
1523m ICP02 SSTL_3, 3.3 V 1523M 1523MT
Abstract: outputs · Up to 250 MHz · SSTL_3 Single-ended clock outputs · Up to 150 MHz · Dynamic Phase Adjust , occurs on all PLL outputs including the differential (PECL) and single-ended (SSTL_3) high-speed clock , (FD) and FUNC The ICS1523 also has SSTL_3 (EIA/JESD8-8) and low-voltage PECL (Positive ECL , with a short transition time. REF can be output on pin 14. The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 Integrated Device Technology
Original
Hex schmitt trigger ecl
Abstract: outputs · Up to 250 MHz · SSTL_3 Single-ended clock outputs · Up to 150 MHz · Dynamic Phase Adjust , differential (PECL) and single-ended (SSTL_3) high-speed clock outputs and the FUNC output. The ICS1523 has , . 1.14 Output Drivers 1.8 Feedback Divider (FD) and FUNC The ICS1523 also has SSTL_3 (EIA/JESD8 , . The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs can be operated unterminated. See Section 9, "Output Integrated Device Technology
Original
U-09-01
Abstract: SN74SSTL16833 * 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVE WITH 3-STATE OUTPUTS SCBS675E - SEPTEMBER 1996 - REVISED DECEMBER 199 Member of the Texas Instruments Widebug* Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB Layout Meets SSTL_3 Class I and Class , -V to 3.6-V V cc operation and SSTL_3 or LVTTL I/O levels. Data flow from A to Y is controlled by the , 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS675E - SEPTEMBER 1996- REVISED -
OCR Scan
JESD17
Abstract: SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A ­ OCTOBER 1997 ­ REVISED MAY 1998 D Member of the Texas Instruments D D D D D D Widebus Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB Layout Meets SSTL_3 Class I and Class II , -V VCC operation and SSTL_3 input levels. Data flow from A to Y is controlled by the output-enable (OE). , Incorporated POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 6­9 SN74SSTL16847 20-BIT SSTL_3 Texas Instruments
Original
MIL-STD-883
Abstract: outputs · Up to 250 MHz · SSTL_3 Single-ended clock outputs · Up to 150 MHz · Dynamic Phase Adjust , single-ended (SSTL_3) high-speed clock outputs and the FUNC output. The ICS1523 has the ability to operate in , most VESA compliant HSYNC and VSYNC signals. The ICS1523 also has SSTL_3 (EIA/JESD8-8) and , MDS 1523 Y 1.11 OSC Input The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs can be operated Integrated Circuit Systems
Original
GIS 110 kV TTL Schmitt-Trigger
Abstract: Integrated Circuit Systems, Inc. ICS1524A Dual Output Phase Controlled SSTL_3/PECL Clock , 250 MHz PECL differential and 150 MHz SSTL_3 single-ended output pins. The CLK output channel has a , single-ended SSTL_3 clock outputs Dynamic Phase Adjust (DPA) for DPACLK outputs · Software controlled phase , Function output SSTL_3 selectable HSYNC output 16 CLK SSTL P i xe l c l o c k t Non-Delayed SSTL_3 Clock 17 D PAC L K SSTL DPA Delayed Clock DPA Delayed SSTL_3 Clock 18 Integrated Circuit Systems
Original
1524AM 1524AMLF d1223 ICS1524AM 1524M S1524M ICS1524AMTT ICS1524AMLF
Abstract: to 133 MHz AGP 1× and 2× Graphics processors 66 to 133 MHz SSTL-3 class I and II SDRAM , VREF = 1.5 V SSTL-3 Class I & II - EIA/JEDEC Standard JESD8-8 The SSTL-3 I/O standard is a 3.3 , the input and output specifications for devices that operate in the SSTL-3 logic switching range of 0.0 to 3.3 V. The SSTL-3 standard specifies an input voltage range of ­ 0.3 V VI VCCIO + 0.3 V. SSTL-3 requires a 1.5-V VREF and a 1.5-V VTT to which the series and termination resistors are Altera
Original
JC42 SSTL-18 AN-201-2
Abstract: to 100 MHz · PECL differential outputs · Up to 250 MHz · SSTL_3 Single-ended clock outputs · Up to , (PECL) and single-ended (SSTL_3) high-speed clock outputs and the FUNC output. The 1523 has the ability , Drivers and Logic Inputs The ICS1523 uses low-voltage TTL (LVTTL) inputs as well as SSTL_3 (EIA/JESD8 , are 5 V-tolerant. The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs can be operated unterminated. See Chapter 11 Integrated Circuit Systems
Original
1523 IC circuit diagram REG670 SOIC-24
Showing first 20 results.