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DLF 3500L Coilcraft Inc Common mode filter, data line, 3 line, RoHS ri Buy
DLF 3000L Coilcraft Inc Common mode filter, data line, 3 line, RoHS ri Buy
DLF 3500 Coilcraft Inc NOT RoHS. Common mode filter, data line, 3 line (add 'L' for compliant version) ri Buy

SSTL-3

Catalog Datasheet Results Type PDF Document Tags
Abstract: Integrated Circuit Systems, Inc. ICS1523 ICS1523 1523 Document Type: Application Note Document Stage: Release Using SSTL-3 Outputs with CMOS or LVTTL Inputs The ICS1523 ICS1523 has the following SSTL-3 outputs , , SSTL-3 outputs are intended to provide a moderate voltage swing across a low-impedance load at the end of a transmission line. However, if an SSTL-3 output is connected directly to a destination , SSTL-3 outputs can be used. For those applications, the designer can use the corresponding PECL outputs. ... Original
datasheet

1 pages,
9.7 Kb

SSTL-3 ICS1523 JESD88 ICS1523 abstract
datasheet frame
Abstract: LVTTL 44 TSOP 1 1(400MIL 400MIL) SSTL-3 NOW 50 TSOP I I (400MIL 400MIL) 66/83/100 MHz SSTL-3 LVTTL SSTL-3 LVTTL SSTL-3 LVTTL SSTL-3 4K LVTTL SSTL-3 LVTTL SSTL-3 LVTTL SSTL-3 MHz 54 TSOP 1 1 (400MIL 400MIL) NOW *NOTE LVTTL : Low Voltage Transistor Transistor Logic CTT : Center Tapped Termination SSTL-3 ... OCR Scan
datasheet

7 pages,
245.16 Kb

GMM2645233CTG gm72v16821 datasheet abstract
datasheet frame
Abstract: ® White Paper MAX 7000B 7000B I/O MAX 7000B 7000B SDRAM GTL+SSTL-2 SSTL-3 I/O GTL+SSTL-2 SSTL-3 I/O LVCMOS LVTTL GTL+ PLD LVTTL I/O MAX 7000B 7000B I/O White Paper I/O I/O , http://www.altera.com Literature GTL+ SSTL-2 SSTL-3 Class I Class II M-WP-MAX7000B-01/J M-WP-MAX7000B-01/J , Drivers 2 SSTL-2SSTL-3 Fairchild 1 2 3 4 5 6 7 20-bit SSTL-3 universal bus driver class I outputs 20-bit SSTL-3 universal bus driver class II outputs 20-bit SSTL-3 ... Original
datasheet

9 pages,
63.15 Kb

sstl lvttl Translator SN74GTLPH16612 SN74GTLPH1645 SN74GTLPH1616 SN74GTLPH1612 SN74GTLP1394 GTLP16612 7000B 7000B abstract
datasheet frame
Abstract: Contents Page SN74SSTL16837A SN74SSTL16837A SN74SSTL16847 SN74SSTL16847 SN74SSTL16857 SN74SSTL16857 SN74SSTL32867 SN74SSTL32867 SN74SSTL32877 SN74SSTL32877 20-Bit SSTL_3 Interface Universal Bus Driver With 3-State Outputs . . . . . . . . . . . . . . 20-Bit SSTL_3 Interface Buffer With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-Bit SSTL_2 Registered Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-Bit Registered Buffer With SSTL_2 Inputs and LVCMOS Outputs . . . . . . . . . . . . . . 26-Bit ... Original
datasheet

1 pages,
207.41 Kb

SN74SSTL16837A SN74SSTL16847 SN74SSTL16857 SN74SSTL32867 SN74SSTL32877 SN74SSTL16837A abstract
datasheet frame
Abstract: 1.0 N/A 1.5 SSTL-2 Class I and II 1.125 2.5 1.125 SSTL-3 Class I and II , I/O s LVTTL s LVCMOS s 2.5V s 1.8V s 3.3V PCI s GTL+ s SSTL_3 Class I and II s SSTL_2 Class , LVTTL() LVCMOS 3.3V PCI LVDS 2.5V 1.8V GTL+ SSTL-2 Class I SSTL-2 Class II SSTL-3 Class I SSTL-3 Class II AGP CTT 2 Altera Corporation Using I/O Standards in the Quartus , VCCIO I/O I/O ( )() VCCIO I/O VREF VREF I/O GTL+ SSTL-3 Class I 7 Using I/O ... Original
datasheet

15 pages,
419.83 Kb

SSTL_3, 3.3 V EP20K400EBC652-1X EP20K100E 10-LVDS APEXTM20KE APEXTM20KE abstract
datasheet frame
Abstract: 284 LVTTL,LVCMOS2,LVCMOS18 LVCMOS18, PCI33 PCI33, PCI66 PCI66, GTL, GTL+, HSTL I,HSTL III,HSTL IV ,SSTL3 I, SSTL3 II , III, HSTL IV, -5 -6 -5 0.8M SSTL3 I, SSTL3 II, SSTL2 I, -5 -6 -5 1.1M SSTL2 II, AGP-2X, CTT -5 -6 -5 ... Original
datasheet

1 pages,
151.06 Kb

XC2S15 202 ball bga datasheet abstract
datasheet frame
Abstract: SO-8PSOP-8LLP-16 SO-8PSOP-8LLP-16 DDR SSTL-2 SSTL-3 20020514 © National Semiconductor , VREF VTT 1.25V SSTL-3 0.5 VDDQ - 0.45 VDDQ , TTVREF VDDQ -0.45 V 2 50k VTT VDDQ - 0.5 SSTL-3 0.5 FIGURE 6. SSTL-3 Implementation VTT VDDQ - 0.5 VTTGND VSENSE VREF VTT ... Original
datasheet

12 pages,
342.66 Kb

SO-8PSOP-8LLP-16 M08A LP2995 LLP-16 LP2955 LP2995 abstract
datasheet frame
Abstract: SO-8PSOP-8LLP-16 SO-8PSOP-8LLP-16 DDR SSTL-2 SSTL-3 20020514 © National Semiconductor , VREF VTT 1.25V SSTL-3 0.5 VDDQ - 0.45 VDDQ , TTVREF VDDQ -0.45 V 2 50k VTT VDDQ - 0.5 SSTL-3 0.5 FIGURE 6. SSTL-3 Implementation VTT VDDQ - 0.5 VTTGND VSENSE VREF VTT ... Original
datasheet

12 pages,
329.04 Kb

M08A LP2995 LP2955 LP2995 abstract
datasheet frame
Abstract: VCCIO ) and SSTL-3 class II (3.3-V VCCIO ), use two separate I/O banks. Different I/O standards need , termination resistor (RS) for single-ended voltage-referenced I/O standard such as SSTL-2 and SSTL-3. The , Supported I/O Standards SSTL-3 class I VCCIO (V) 3.3 SSTL-3 class II 3.3 SSTL-2 class I 2.5 , termination is supported for SSTL-2, SSTL-3, HSTL (class I and II), GTL, GTL+, and CTT I/O standards. All the , Termination (RT1) Parallel Termination (RT2) VCCIO (V) SSTL-3 class I N/A 50 3.3 ... Original
datasheet

14 pages,
94.92 Kb

SSTL-3 datasheet abstract
datasheet frame
Abstract: the GTL+, SSTL-2, and SSTL-3 standards used in processor interfaces, backplane drivers, and SDRAM , to convert GTL+, SSTL-2, or SSTL-3 signals to LVCMOS or to LVTTL before transferring these signals , www.altera.com. Table 1 lists the available GTL+ drivers and Table 2 lists the SSTL-2 and SSTL-3 drivers , SN74GTLPH306 SN74GTLPH306 GTLP6C816 GTLP6C816 Table 2. Part Numbers for SSTL-2 & SSTL-3 Drivers (Part 1 of 2) Number Description Part Numbers Fairchild National Philips Tl 1 20-bit SSTL-3 universal bus ... Original
datasheet

12 pages,
91.33 Kb

SN74GTLPH16612 SN74GTLPH1616 SN74GTLPH1612 SN74GTLP1394 GTLP16T1655 GTLP16612 altera EPM7032B 7000B 7000B abstract
datasheet frame
Abstract: SSTL_3/PECL Clock Generator Dual Output Phase Controlled SSTL_3/PECL Clock Generator General Description , DPACLK. These two output channels have both 250 MHz PECL differential and 150 MHz SSTL_3 single-ended , range · 8 kHz to 100 MHz 250 MHz balanced PECL differential outputs 150 MHz single-ended SSTL_3 clock , upon by the customer is current and accurate. 2 IDTTM / ICSTM Dual Output Phase Controlled SSTL_3 , Output Phase Controlled SSTL_3/PECL Clock Generator ICS1524 ICS1524 TSD Document Revision History Rev A ... Original
datasheet

24 pages,
567.21 Kb

PSD01 ICS1524 ICS1524 abstract
datasheet frame
Abstract: the GTL+, SSTL-2, and SSTL-3 standards used in processor interfaces, backplane drivers, and SDRAM , to convert GTL+, SSTL-2, or SSTL-3 signals to LVCMOS or to LVTTL before transferring these signals , www.altera.com. Table 1 lists the available GTL+ drivers and Table 2 lists the SSTL-2 and SSTL-3 drivers , SN74GTLPH306 SN74GTLPH306 GTLP6C816 GTLP6C816 Table 2. Part Numbers for SSTL-2 & SSTL-3 Drivers (Part 1 of 2) Number Description Part Numbers Fairchild National Philips Tl 1 20-bit SSTL-3 universal bus ... Original
datasheet

12 pages,
74.62 Kb

SN74GTLPH16612 SN74GTLPH1616 SN74GTLPH1612 SN74GTLP1394 GTLP16T1655 GTLP16612 7000B 7000B abstract
datasheet frame
Abstract: 7000B 7000B device is the only product-term device capable of supporting the GTL+, SSTL-2, and SSTL-3 , , discrete I/O translators, buffers, drivers, and transceivers are used to convert GTL+, SSTL-2, or SSTL-3 , SSTL-2 and SSTL-3 drivers supporting outputs in the Class I and Class II standards. M-WP-MAX7000B-01 M-WP-MAX7000B-01 , Corporation Using MAX 7000B 7000B Devices to Replace I/O Drivers Table 2. Part Numbers for SSTL-2 & SSTL-3 Drivers Number Description Part Numbers Fairchild 1 2 3 4 5 6 7 20-bit SSTL-3 ... Original
datasheet

9 pages,
51.38 Kb

SSTL-3 sstl lvttl Translator SN74GTLPH16612 SN74GTLPH1645 SN74GTLPH1616 SN74GTLPH1612 SN74GTLP1394 GTLP16612 7000B 7000B abstract
datasheet frame

Datasheet Content (non pdf)

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Over 1.1 million files (1986-2014): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer.
 
SN74SSTL16847 SN74SSTL16847 SN74SSTL16847 SN74SSTL16847 20-BIT 20-BIT 20-BIT 20-BIT SSTL_3 the Texas Instruments Widebus TM Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB Layout Meets SSTL_3 Class I and Class II Specifications ESD Protection Exceeds 2000 3.6-V V CC operation and SSTL_3 input levels. Data flow from A to Y is controlled by the output-enable is characterized for operation from 0°C to 70°C. Title: 20-BIT 20-BIT 20-BIT 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE
www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/datasht/scbs709a.htm
Texas Instruments 01/06/1998 5.45 Kb HTM scbs709a.htm
SN74SSTL16837 SN74SSTL16837 SN74SSTL16837 SN74SSTL16837 20-BIT 20-BIT 20-BIT 20-BIT SSTL_3 sheet. features Member of the Texas Instruments Widebus TM Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB Layout Meets SSTL_3 Class I and Class II Specifications designed for 3-V to 3.6-V V CC operation and SSTL_3 or LVTTL I/O levels. Data flow from A to Y is for operation from 0°C to 70°C Title: 20-BIT 20-BIT 20-BIT 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE
www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/datasht/scbs675e.htm
Texas Instruments 01/06/1998 5.94 Kb HTM scbs675e.htm
The LP2994 LP2994 LP2994 LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 package SO-8 Low cost and easy to use Shutdown pin Applications SSTL-2 SSTL-3
www.datasheetarchive.com/files/national/htm/nsc03718.htm
National 16/08/2002 11.87 Kb HTM nsc03718.htm
Synchronous DRAM, High-Speed Microprocessors, and SSTL_3 Applications LVTTL- or SSTL_3-Compatible Inputs and Outputs Distributed V CC and GND Pin Configuration Minimize High-Speed Switching Noise Meets SSTL_3 Class 1 and 2 Specifications Packaged in 56-Pin Plastic LVTTL- or SSTL_3-compatible inputs and outputs. The CDC2587 CDC2587 CDC2587 CDC2587 operates at frequencies from 16.67 MHz to SSTL_3 input levels by connecting V REF to a nominal reference voltage of 1.5 V. If V REF is strapped
www.datasheetarchive.com/files/texas-instruments/data/html/scas560b-v2.htm
Texas Instruments 18/08/1997 4.48 Kb HTM scas560b-v2.htm
Synchronous DRAM, High-Speed Microprocessors, and SSTL_3 Applications LVTTL- or SSTL_3-Compatible Inputs and Outputs Distributed V CC and GND Pin Configuration Minimize High-Speed Switching Noise Meets SSTL_3 Class 1 and 2 Specifications Packaged in 56-Pin Plastic LVTTL- or SSTL_3-compatible inputs and outputs. The CDC2587 CDC2587 CDC2587 CDC2587 operates at frequencies from 16.67 MHz to SSTL_3 input levels by connecting V REF to a nominal reference voltage of 1.5 V. If V REF is strapped
www.datasheetarchive.com/files/texas-instruments/data/html/scas560b.htm
Texas Instruments 17/11/1997 4.48 Kb HTM scas560b.htm
Synchronous DRAM, High-Speed Microprocessors, and SSTL_3 Applications LVTTL- or SSTL_3-Compatible Inputs and Outputs Distributed V CC and GND Pin Configuration Minimize High-Speed Switching Noise Meets SSTL_3 Class 1 and 2 Specifications Packaged in 56-Pin Plastic LVTTL- or SSTL_3-compatible inputs and outputs. The CDC2587 CDC2587 CDC2587 CDC2587 operates at frequencies from 16.67 MHz to SSTL_3 input levels by connecting V REF to a nominal reference voltage of 1.5 V. If V REF is strapped
www.datasheetarchive.com/files/texas-instruments/data/html/scas560b-v1.htm
Texas Instruments 18/08/1997 4.48 Kb HTM scas560b-v1.htm
Answers Database Does Virtex support LVPECL voltage standard? Record #5179 Product Family: Hardware Product Line: Virtex Problem Title: Does Virtex support LVPECL voltage standard? Problem Description: Keywords: Virtex, LVPECL, Voltage, Standard Urgency: Standard as LVTTL, LVCMOS, PCI, GTL, HSTL Class I III and IV, SSTL3 class I and II, SSTL2
www.datasheetarchive.com/files/xilinx/docs/wcd0000e/wcd00e42.htm
Xilinx 16/02/1999 3.37 Kb HTM wcd00e42.htm
DDR SDRAM Termination SSTL_2 Interface SSTL_3 Interface
www.datasheetarchive.com/files/linear/c1003/c1042/c1093/p2170/p2170-applications-v1.html
Linear 21/11/2005 7.37 Kb HTML p2170-applications-v1.html
DDR SDRAM Termination SSTL_2, SSTL_3 Interface HSTL Interface
www.datasheetarchive.com/files/linear/c1003/c1042/c1093/p2466/p2466-applications.html
Linear 09/02/2007 7.9 Kb HTML p2466-applications.html
DDR SDRAM Termination SSTL_2, SSTL_3 Interface HSTL Interface
www.datasheetarchive.com/files/linear/c1003/c1042/c1093/p2466/p2466-applications-v1.html
Linear 21/11/2005 7.38 Kb HTML p2466-applications-v1.html