NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Integrated Circuit Systems, Inc. ICS1523 ICS1523 1523 Document Type: Application Note Document Stage: Release Using SSTL-3 Outputs with CMOS or LVTTL Inputs The ICS1523 ICS1523 has the following SSTL-3 outputs , , SSTL-3 outputs are intended to provide a moderate voltage swing across a low-impedance load at the end of a transmission line. However, if an SSTL-3 output is connected directly to a destination , SSTL-3 outputs can be used. For those applications, the designer can use the corresponding PECL outputs. ... | Original |
1 pages, |
ICS1523 ICS1523 abstract |
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| Abstract: ® White Paper MAX 7000B 7000B I/O MAX 7000B 7000B SDRAM GTL+SSTL-2 SSTL-3 I/O GTL+SSTL-2 SSTL-3 I/O LVCMOS LVTTL GTL+ PLD LVTTL I/O MAX 7000B 7000B I/O White Paper I/O I/O , http://www.altera.com Literature GTL+ SSTL-2 SSTL-3 Class I Class II M-WP-MAX7000B-01/J M-WP-MAX7000B-01/J , Drivers 2 SSTL-2SSTL-3 Fairchild 1 2 3 4 5 6 7 20-bit SSTL-3 universal bus driver class I outputs 20-bit SSTL-3 universal bus driver class II outputs 20-bit SSTL-3 ... | Original |
9 pages, |
sstl lvttl Translator SN74GTLPH16612 SN74GTLPH1645 SN74GTLPH1616 SN74GTLPH1612 SN74GTLP1394 GTLP16612 7000B 7000B abstract |
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| Abstract: 1.0 N/A 1.5 SSTL-2 Class I and II 1.125 2.5 1.125 SSTL-3 Class I and II , I/O s LVTTL s LVCMOS s 2.5V s 1.8V s 3.3V PCI s GTL+ s SSTL_3 Class I and II s SSTL_2 Class , LVTTL() LVCMOS 3.3V PCI LVDS 2.5V 1.8V GTL+ SSTL-2 Class I SSTL-2 Class II SSTL-3 Class I SSTL-3 Class II AGP CTT 2 Altera Corporation Using I/O Standards in the Quartus , VCCIO I/O I/O ( )() VCCIO I/O VREF VREF I/O GTL+ SSTL-3 Class I 7 Using I/O ... | Original |
15 pages, |
EP20K400EBC652-1X EP20K100E APEXTM20KE APEXTM20KE abstract |
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| Abstract: SO-8PSOP-8LLP-16 SO-8PSOP-8LLP-16 DDR SSTL-2 SSTL-3 20020514 © National Semiconductor , VREF VTT 1.25V SSTL-3 0.5 VDDQ Ã- 0.45 VDDQ , TTVREF VDDQ Ã-0.45 V 2 50k VTT VDDQ Ã- 0.5 SSTL-3 0.5 FIGURE 6. SSTL-3 Implementation VTT VDDQ Ã- 0.5 VTTGND VSENSE VREF VTT ... | Original |
12 pages, |
SO-8PSOP-8LLP-16 M08A LP2995 LP2955 LP2995 abstract |
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| Abstract: SO-8PSOP-8LLP-16 SO-8PSOP-8LLP-16 DDR SSTL-2 SSTL-3 20020514 © National Semiconductor , VREF VTT 1.25V SSTL-3 0.5 VDDQ Ã- 0.45 VDDQ , TTVREF VDDQ Ã-0.45 V 2 50k VTT VDDQ Ã- 0.5 SSTL-3 0.5 FIGURE 6. SSTL-3 Implementation VTT VDDQ Ã- 0.5 VTTGND VSENSE VREF VTT ... | Original |
12 pages, |
M08A LP2995 LP2955 LP2995 abstract |
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| Abstract: VCCIO ) and SSTL-3 class II (3.3-V VCCIO ), use two separate I/O banks. Different I/O standards need , termination resistor (RS) for single-ended voltage-referenced I/O standard such as SSTL-2 and SSTL-3. The , Supported I/O Standards SSTL-3 class I VCCIO (V) 3.3 SSTL-3 class II 3.3 SSTL-2 class I 2.5 , termination is supported for SSTL-2, SSTL-3, HSTL (class I and II), GTL, GTL+, and CTT I/O standards. All the , Termination (RT1) Parallel Termination (RT2) VCCIO (V) SSTL-3 class I N/A 50 3.3 ... | Original |
14 pages, |
SSTL-3 datasheet abstract |
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| Abstract: the GTL+, SSTL-2, and SSTL-3 standards used in processor interfaces, backplane drivers, and SDRAM , to convert GTL+, SSTL-2, or SSTL-3 signals to LVCMOS or to LVTTL before transferring these signals , www.altera.com. Table 1 lists the available GTL+ drivers and Table 2 lists the SSTL-2 and SSTL-3 drivers , SN74GTLPH306 SN74GTLPH306 GTLP6C816 GTLP6C816 Table 2. Part Numbers for SSTL-2 & SSTL-3 Drivers (Part 1 of 2) Number Description Part Numbers Fairchild National Philips Tl 1 20-bit SSTL-3 universal bus ... | Original |
12 pages, |
SN74GTLPH16612 SN74GTLPH1616 SN74GTLPH1612 SN74GTLP1394 GTLP16T1655 GTLP16612 altera EPM7032B 7000B 7000B abstract |
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| Abstract: the GTL+, SSTL-2, and SSTL-3 standards used in processor interfaces, backplane drivers, and SDRAM , to convert GTL+, SSTL-2, or SSTL-3 signals to LVCMOS or to LVTTL before transferring these signals , www.altera.com. Table 1 lists the available GTL+ drivers and Table 2 lists the SSTL-2 and SSTL-3 drivers , SN74GTLPH306 SN74GTLPH306 GTLP6C816 GTLP6C816 Table 2. Part Numbers for SSTL-2 & SSTL-3 Drivers (Part 1 of 2) Number Description Part Numbers Fairchild National Philips Tl 1 20-bit SSTL-3 universal bus ... | Original |
12 pages, |
SN74GTLPH16612 SN74GTLPH1616 SN74GTLPH1612 SN74GTLP1394 GTLP16T1655 GTLP16612 7000B 7000B abstract |
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| Abstract: G2992 G2992 Global Mixed-mode Technology Inc. 3A DDR Bus Termination Regulator General Description Features The G2992 G2992 is a linear regulator designed to meet the JEDEC SSTL-18 SSTL-18, SSTL-2 and SSTL-3 (Series Stub Termination Logic) specifications for termination of DDR I / II -SDRAM. It contains a high-speed operational amplifier that provides excellent response to the load transients. This device can deliver 3A , Voltage DDR I / DDR II Termination Voltage SSTL-18 SSTL-18 SSTL-2 SSTL-3 Ordering Information ORDER ... | Original |
1 pages, |
SSTL18 SSTL-18 SOP-8 FD SOP-8 2N7002 SSTL-3 G2992 DDR RAM POWER SUPPLY G2992F1U G2992 abstract |
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| Abstract: 7000B 7000B device is the only product-term device capable of supporting the GTL+, SSTL-2, and SSTL-3 , , discrete I/O translators, buffers, drivers, and transceivers are used to convert GTL+, SSTL-2, or SSTL-3 , SSTL-2 and SSTL-3 drivers supporting outputs in the Class I and Class II standards. M-WP-MAX7000B-01 M-WP-MAX7000B-01 , Corporation Using MAX 7000B 7000B Devices to Replace I/O Drivers Table 2. Part Numbers for SSTL-2 & SSTL-3 Drivers Number Description Part Numbers Fairchild 1 2 3 4 5 6 7 20-bit SSTL-3 ... | Original |
9 pages, |
SSTL-3 sstl lvttl Translator SN74GTLPH16612 SN74GTLPH1645 SN74GTLPH1616 SN74GTLPH1612 SN74GTLP1394 GTLP16612 7000B 7000B abstract |
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| Data Sheet Abstract: SN74SSTL16847 SN74SSTL16847 SN74SSTL16847 SN74SSTL16847:20-BIT 20-BIT 20-BIT 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SN74SSTL16847 SN74SSTL16847 SN74SSTL16847 SN74SSTL16847 20-BIT 20-BIT 20-BIT 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A SCBS709A SCBS709A SCBS709A - OCTOBER 1997 - REVISED MAY 1998 features Member of the Texas Instruments Widebus TM Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB Layout Meets SSTL_3 Class I and Class II designed for 3-V to 3.6-V V CC operation and SSTL_3 input levels. Data flow from A to Y is controlled by www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/datasht/scbs709a.htm |
Texas Instruments | 01/06/1998 | 5.45 Kb | HTM | scbs709a.htm |
| Data Sheet Abstract: SN74SSTL16837 SN74SSTL16837 SN74SSTL16837 SN74SSTL16837:20-BIT 20-BIT 20-BIT 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SN74SSTL16837 SN74SSTL16837 SN74SSTL16837 SN74SSTL16837 20-BIT 20-BIT 20-BIT 20-BIT SSTL_3 sheet. features Member of the Texas Instruments Widebus TM Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB Layout Meets SSTL_3 Class I and Class II Specifications designed for 3-V to 3.6-V V CC operation and SSTL_3 or LVTTL I/O levels. Data flow from A to Y is www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/datasht/scbs675e.htm |
Texas Instruments | 01/06/1998 | 5.94 Kb | HTM | scbs675e.htm |
| SSTL3_I SSTL3_II 0 0 AGP CTT SSTL3_I SSTL3_II 0 0 AGP CTT SSTL3_I SSTL3_II 0 0 AGP CTT SSTL3_I SSTL3_II 0 0 AGP CTT SSTL3_I SSTL3_II 0 0 AGP CTT www.datasheetarchive.com/files/xilinx/docs/rp00004/rp00479.htm |
Xilinx | 06/03/2000 | 50.61 Kb | HTM | rp00479.htm |
| .90 IBUFG_HSTL_IV HSTL_IV 0.75 IBUFG_SSTL2_I SSTL2_I 1.10 IBUFG_SSTL2_II SSTL2_II 1.10 IBUFG_SSTL3_I SSTL3_I 0.90 IBUFG_SSTL3_II SSTL3_II 1.50 IBUFG_CTT CTT 1.50 IBUFG_AGP AGP 1.32 www.datasheetarchive.com/files/xilinx/docs/wcd00040/wcd040d8.htm |
Xilinx | 16/02/1999 | 3.91 Kb | HTM | wcd040d8.htm |
| _HSTL_IV HSTL_IV 1.5 OBUF_SSTL2_I SSTL2_I 2.5 OBUF_SSTL2_II SSTL2_II 2.5 OBUF_SSTL3_I SSTL3_I 3.3 OBUF_SSTL3_II SSTL3_II 3.3 OBUF_CTT CTT 3.3 OBUF_AGP AGP 3.3 www.datasheetarchive.com/files/xilinx/docs/wcd00040/wcd040dd.htm |
Xilinx | 16/02/1999 | 5.08 Kb | HTM | wcd040dd.htm |
| name extensions (LVCMOS2, PCI33 PCI33 PCI33 PCI33_3, PCI33 PCI33 PCI33 PCI33_5, etc.) specify the standard. For example, IBUF_SSTL3_II is a single input buffer that uses the SSTL3_II I/O-signaling standard. An IBUF isolates the internal .75 IBUF_SSTL2_I SSTL2_I 1.10 IBUF_SSTL2_II SSTL2_II 1.10 IBUF_SSTL3_I SSTL3_I 0.90 IBUF_SSTL3_II SSTL3_II 1.50 IBUF_CTT CTT 1.50 IBUF_AGP AGP 1.32 SelectI/O Usage Rules The Virtex .10 SSTL3_I 3.3 0.90 SSTL3_II 3.3 1.50 CTT 3.3 1.50 AGP 3.3 1.32 Input Banking (VREF www.datasheetarchive.com/files/xilinx/docs/wcd00040/wcd040d7.htm |
Xilinx | 16/02/1999 | 10 Kb | HTM | wcd040d7.htm |
| Synchronous DRAM, High-Speed Microprocessors, and SSTL_3 Applications LVTTL- or SSTL_3 -Speed Switching Noise Meets SSTL_3 Class 1 and 2 Specifications Packaged in 56-Pin Plastic provides LVTTL- or SSTL_3-compatible inputs and outputs. The CDC2587 CDC2587 CDC2587 CDC2587 operates at frequencies from 16 and FBIN can be configured to switch at SSTL_3 input levels by connecting V REF to a nominal www.datasheetarchive.com/files/texas-instruments/data/html/scas560b-v1.htm |
Texas Instruments | 18/08/1997 | 4.48 Kb | HTM | scas560b-v1.htm |
| Synchronous DRAM, High-Speed Microprocessors, and SSTL_3 Applications LVTTL- or SSTL_3 -Speed Switching Noise Meets SSTL_3 Class 1 and 2 Specifications Packaged in 56-Pin Plastic provides LVTTL- or SSTL_3-compatible inputs and outputs. The CDC2587 CDC2587 CDC2587 CDC2587 operates at frequencies from 16 and FBIN can be configured to switch at SSTL_3 input levels by connecting V REF to a nominal www.datasheetarchive.com/files/texas-instruments/data/html/scas560b.htm |
Texas Instruments | 17/11/1997 | 4.48 Kb | HTM | scas560b.htm |
| , such as LVTTL, LVCMOS, PCI, GTL, HSTL Class I III and IV, SSTL3 class I and II, SSTL2 class I and www.datasheetarchive.com/files/xilinx/docs/rp00018/rp0186c.htm |
Xilinx | 29/02/2000 | 4.08 Kb | HTM | rp0186c.htm |
| _5, PCI66 PCI66 PCI66 PCI66_3, S_2, S_4, S_6, S_8, S_12, S_16, S_24, SSTL2_I, SSTL2_II, SSTL3_I, SSTL3_II Please ); q : out std_logic_vector(3 downto 0); attribute xc_padtype of a : signal is "IBUF_SSTL3_I www.datasheetarchive.com/files/xilinx/docs/rp00010/rp010d2.htm |
Xilinx | 29/02/2000 | 5.94 Kb | HTM | rp010d2.htm |