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74SSTL16847DGGRE4 Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64 pdf Buy
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SSTL16857DGG,112 NXP Semiconductors Registers 14-BIT SSTL 2 REG DRIVER (Sep 2016) Mouser Electronics Buy
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SSTL-3

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: Integrated Circuit Systems, Inc. DATA SHEET ICS1524 ICS1524 ICS1524 ICS1524 Dual Output Phase Controlled SSTL_3/PECL Clock Generator Dual Output Phase Controlled SSTL_3/PECL Clock Generator General Description The , DPACLK. These two output channels have both 250 MHz PECL differential and 150 MHz SSTL_3 single-ended , range · 8 kHz to 100 MHz 250 MHz balanced PECL differential outputs 150 MHz single-ended SSTL_3 clock , upon by the customer is current and accurate. 2 IDTTM / ICSTM Dual Output Phase Controlled SSTL_3 ... Integrated Device Technology
Original
datasheet

24 pages,
567.21 Kb

PSD01 1523AN4 ICS1524 TEXT
datasheet frame
Abstract: ® White Paper MAX 7000B 7000B I/O MAX 7000B 7000B SDRAM GTL+SSTL-2 SSTL-3 I/O GTL+SSTL-2 SSTL-3 I/O LVCMOS LVTTL GTL+ PLD LVTTL I/O MAX 7000B 7000B I/O White Paper I/O I/O , http://www.altera.com Literature GTL+ SSTL-2 SSTL-3 Class I Class II M-WP-MAX7000B-01/J M-WP-MAX7000B-01/J , Drivers 2 SSTL-2SSTL-3 Fairchild 1 2 3 4 5 6 7 20-bit SSTL-3 universal bus driver class I outputs 20-bit SSTL-3 universal bus driver class II outputs 20-bit SSTL-3 ... Altera
Original
datasheet

9 pages,
63.15 Kb

sstl lvttl Translator SN74GTLPH16612 SN74GTLPH1645 SN74GTLPH1616 SN74GTLPH1612 SN74GTLP1394 GTLP16612 7000B TEXT
datasheet frame
Abstract: ® 7000B 7000B device is the only product-term device capable of supporting the GTL+, SSTL-2, and SSTL-3 , , discrete I/O translators, buffers, drivers, and transceivers are used to convert GTL+, SSTL-2, or SSTL-3 , -2 and SSTL-3 drivers supporting outputs in the Class I and Class II standards. M-WP-MAX7000B M-WP-MAX7000B , Corporation Using MAX 7000B 7000B Devices to Replace I/O Drivers Table 2. Part Numbers for SSTL-2 & SSTL-3 Drivers Number Description Part Numbers Fairchild 1 2 3 4 5 6 7 20-bit SSTL-3 ... Altera
Original
datasheet

9 pages,
51.38 Kb

SSTL-3 sstl lvttl Translator SN74GTLPH16612 SN74GTLPH1645 SN74GTLPH1616 SN74GTLPH1612 SN74GTLP1394 GTLP16612 7000B TEXT
datasheet frame
Abstract: outputs · Up to 250 MHz · SSTL_3 Single-ended clock outputs · Up to 150 MHz · Dynamic Phase Adjust , differential (PECL) and single-ended (SSTL_3) high-speed clock outputs and the FUNC output. The ICS1523 ICS1523 has , FUNC The ICS1523 ICS1523 also has SSTL_3 (EIA/JESD8-8) and low-voltage PECL (Positive ECL) outputs , transition time. REF can be output on pin 14. The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs can be ... Integrated Device Technology
Original
datasheet

21 pages,
335.18 Kb

POWER TECH INC MAN09 ICS1523MLF ICS1523 132 kv gis 734 coaxial cable data 1523MLFT TEXT
datasheet frame
Abstract: LVTTL 44 TSOP 1 1(400MIL 400MIL) SSTL-3 NOW 50 TSOP I I (400MIL 400MIL) 66/83/100 MHz SSTL-3 LVTTL SSTL-3 LVTTL SSTL-3 LVTTL SSTL-3 4K LVTTL SSTL-3 LVTTL SSTL-3 LVTTL SSTL-3 MHz 54 TSOP 1 1 (400MIL 400MIL) NOW *NOTE LVTTL : Low Voltage Transistor Transistor Logic CTT : Center Tapped Termination SSTL-3 ... OCR Scan
datasheet

7 pages,
245.16 Kb

GMM2645233CTG gm72v16821ct gm72v16821 TEXT
datasheet frame
Abstract: the GTL+, SSTL-2, and SSTL-3 standards used in processor interfaces, backplane drivers, and SDRAM , to convert GTL+, SSTL-2, or SSTL-3 signals to LVCMOS or to LVTTL before transferring these signals , www.altera.com. Table 1 lists the available GTL+ drivers and Table 2 lists the SSTL-2 and SSTL-3 drivers , GTLP8T306 GTLP8T306 transceiver GTLP8T306 GTLP8T306 SN74GTLPH306 SN74GTLPH306 GTLP6C816 GTLP6C816 Table 2. Part Numbers for SSTL-2 & SSTL-3 , 20-bit SSTL-3 universal bus driver class I outputs SN74SSTL16837A SN74SSTL16837A (2) 2 20-bit SSTL-3 ... Altera
Original
datasheet

12 pages,
74.62 Kb

SN74GTLPH16612 SN74GTLPH1616 SN74GTLPH1612 SN74GTLP1394 GTLP16T1655 GTLP16612 7000B TEXT
datasheet frame
Abstract: the GTL+, SSTL-2, and SSTL-3 standards used in processor interfaces, backplane drivers, and SDRAM , to convert GTL+, SSTL-2, or SSTL-3 signals to LVCMOS or to LVTTL before transferring these signals , www.altera.com. Table 1 lists the available GTL+ drivers and Table 2 lists the SSTL-2 and SSTL-3 drivers , GTLP8T306 GTLP8T306 transceiver GTLP8T306 GTLP8T306 SN74GTLPH306 SN74GTLPH306 GTLP6C816 GTLP6C816 Table 2. Part Numbers for SSTL-2 & SSTL-3 , 20-bit SSTL-3 universal bus driver class I outputs SN74SSTL16837A SN74SSTL16837A (2) 2 20-bit SSTL-3 ... Altera
Original
datasheet

12 pages,
91.33 Kb

SN74GTLPH16612 SN74GTLPH1616 SN74GTLPH1612 SN74GTLP1394 GTLP16T1655 GTLP16612 altera EPM7032B 7000B TEXT
datasheet frame
Abstract: -V VCCIO ) and SSTL-3 class II (3.3-V VCCIO ), use two separate I/O banks. Different I/O standards need , resistor (RS) for single-ended voltage-referenced I/O standard such as SSTL-2 and SSTL-3. The series , Supported I/O Standards SSTL-3 class I VCCIO (V) 3.3 SSTL-3 class II 3.3 SSTL-2 class I 2.5 , resistors. Parallel termination is supported for SSTL-2, SSTL-3, HSTL (class I and II), GTL, GTL+, and CTT , ) SSTL-3 class I N/A 50 3.3 SSTL-3 class II (1) 50 50 3.3 SSTL-2 class I N ... Altera
Original
datasheet

14 pages,
94.92 Kb

SSTL-3 TEXT
datasheet frame
Abstract: frequency range · 15.734 kHz to 100 MHz · PECL differential outputs · Up to 250 MHz · SSTL_3 Single-ended , single-ended (SSTL_3) high-speed clock outputs and the FUNC output. The ICS1523 ICS1523 has the ability to operate in , . See 0x0:5. 1.14 Output Drivers The ICS1523 ICS1523 also has SSTL_3 (EIA/JESD8-8) and low-voltage PECL (Positive ECL) outputs, operating off the 3.3 V supply voltage. The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs ... Integrated Circuit Systems
Original
datasheet

22 pages,
570.32 Kb

ICS1523 TEXT
datasheet frame
Abstract: voltage (VREF). · Voltage-referenced ­ GTL+, SSTL2 Classes I/II, SSTL3 Classes I/II, HSTL Class I , . SSTL3 SSTL3 is a 2.5V memory bus interface standard sponsored by IBM and Hitachi. There are two , 3.6 LVTTL, 3.3V PCI, LVPECL, GTL+, SSTL3 2.5 2.7 LVCMOS 2.5V, GTL+, SSTL2 1.7 1.8 , I SSTL2 Class I & II SSTL3 Class I & II LVDS (VREF=1.0V) LVDS (VREF , ), when VREF = 1.0V (GTL+ requirement). b) LVTTL can be used with 3.3V PCI/PCI-X, and SSTL3 Class I & II ... Actel
Original
datasheet

11 pages,
139.22 Kb

LVCMOS25 LVCMOS15 JESD8-8 IDTQS32X2384 AC182 TEXT
datasheet frame
Abstract: SSTL_3 Single-ended clock outputs · Up to 150 MHz · Dynamic Phase Adjust (DPA) for all outputs · I2C , (SSTL_3) high-speed clock outputs and the FUNC output. The ICS1523 ICS1523 has the ability to operate in , then output on the FUNC pin. See Reg 0:5. The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs can be operated , VSYNC signals. 1.12 Output Drivers The ICS1523 ICS1523 also has SSTL_3 (EIA/JESD8-8) and low-voltage PECL ... Integrated Circuit Systems
Original
datasheet

20 pages,
337.54 Kb

ICS1523 TEXT
datasheet frame
Abstract: outputs · Up to 250 MHz · SSTL_3 Single-ended clock outputs · Up to 150 MHz · Dynamic Phase Adjust , differential (PECL) and single-ended (SSTL_3) high-speed clock outputs and the FUNC output. The ICS1523 ICS1523 has , . 1.14 Output Drivers 1.8 Feedback Divider (FD) and FUNC The ICS1523 ICS1523 also has SSTL_3 (EIA/JESD8 , the FUNC output aligned. The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs can be operated ... Integrated Device Technology
Original
datasheet

21 pages,
226.86 Kb

MAN09 ICS1523MLF ICS1523 1523MLFT TEXT
datasheet frame
Abstract: outputs · Up to 250 MHz · SSTL_3 Single-ended clock outputs · Up to 150 MHz · Dynamic Phase Adjust , occurs on all PLL outputs including the differential (PECL) and single-ended (SSTL_3) high-speed clock , (FD) and FUNC The ICS1523 ICS1523 also has SSTL_3 (EIA/JESD8-8) and low-voltage PECL (Positive ECL , with a short transition time. REF can be output on pin 14. The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 ... Integrated Device Technology
Original
datasheet

21 pages,
326.63 Kb

MAN09 ICS1523MT ICS1523MLFT ICS1523MLF ICS1523M ICS1523 Hex schmitt trigger ecl 132 kv gis TEXT
datasheet frame

Archived Files

Abstract Saved from Date Saved File Size Type Download
Data Sheet Abstract: SN74SSTL16847 SN74SSTL16847:20-BIT 20-BIT SSTL_3 INTERFACE BUFFER WITH SN74SSTL16847 SN74SSTL16847 20-BIT 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A SCBS709A - OCTOBER 1997 - REVISED MAY 1998 features Member of the Texas Instruments Widebus TM Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB Layout Meets SSTL_3 Class I and Incorporated. description This 20-bit buffer is designed for 3-V to 3.6-V V CC operation and SSTL_3
/datasheets/files/texas-instruments/sc/psheets/abstract/datasht/scbs709a.htm
Texas Instruments 01/06/1998 5.45 Kb HTM scbs709a.htm
Data Sheet Abstract: SN74SSTL16837 SN74SSTL16837:20-BIT 20-BIT SSTL_3 INTERFACE UNIVERSAL SN74SSTL16837 SN74SSTL16837 20-BIT 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS675E SCBS675E - Instruments Widebus TM Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB Layout Meets SSTL_3 Class I and Class II Specifications Latch-Up Performance Exceeds 250 3-V to 3.6-V V CC operation and SSTL_3 or LVTTL I/O levels. Data flow from A to Y is controlled by
/datasheets/files/texas-instruments/sc/psheets/abstract/datasht/scbs675e.htm
Texas Instruments 01/06/1998 5.94 Kb HTM scbs675e.htm
Synchronous DRAM, High-Speed Microprocessors, and SSTL_3 Applications LVTTL- or SSTL_3-Compatible Inputs and Outputs Distributed V CC and GND Pin Configuration Minimize High-Speed Switching Noise Meets SSTL_3 Class 1 and 2 Specifications Packaged in 56-Pin Plastic or SSTL_3-compatible inputs and outputs. The CDC2587 CDC2587 operates at frequencies from 16.67 MHz to 150 ) connections are provided for VCO stability. CLKIN and FBIN can be configured to switch at SSTL_3 input
/datasheets/files/texas-instruments/data/html/scas560b-v1.htm
Texas Instruments 18/08/1997 4.48 Kb HTM scas560b-v1.htm
Synchronous DRAM, High-Speed Microprocessors, and SSTL_3 Applications LVTTL- or SSTL_3-Compatible Inputs and Outputs Distributed V CC and GND Pin Configuration Minimize High-Speed Switching Noise Meets SSTL_3 Class 1 and 2 Specifications Packaged in 56-Pin Plastic or SSTL_3-compatible inputs and outputs. The CDC2587 CDC2587 operates at frequencies from 16.67 MHz to 150 ) connections are provided for VCO stability. CLKIN and FBIN can be configured to switch at SSTL_3 input
/datasheets/files/texas-instruments/data/html/scas560b.htm
Texas Instruments 17/11/1997 4.48 Kb HTM scas560b.htm
The LP2994 LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 SSTL-2 SSTL-3 DDR-SDRAM Termination DDR-II Termination [Information as of
/datasheets/files/national/htm/nsc03718.htm
National 16/08/2002 11.87 Kb HTM nsc03718.htm
will also support important low-voltage standards such as LVTTL, LVCMOS, GTL+ and SSTL3. The versatile access compatible with the SSTL3 I/O standard. Kilobytes of data can be stored in block SelectRAM memory.
/datasheets/files/xilinx/docs/wcd00001/wcd0015f.htm
Xilinx 17/07/1998 8.53 Kb HTM wcd0015f.htm
LP2994 LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 SSTL-2 SSTL-3 DDR-SDRAM Termination DDR-II Termination Application Notes
/datasheets/files/national/lp2994.html
National 25/09/2003 13.87 Kb HTML lp2994.html
JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed Voltage SSTL-2 SSTL-3 Application Notes Title Size in Kbytes Date View
/datasheets/files/national/htm/nsc02633-v5.htm
National 01/11/2002 21.87 Kb HTM nsc02633-v5.htm
designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications (Series Stub Low cost and easy to use Shutdown pin Applications SSTL-2 SSTL-3
/datasheets/files/national/htm/nsc02632-v5.htm
National 01/11/2002 15.44 Kb HTM nsc02632-v5.htm
regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications SSTL-3 DDR-SDRAM Termination DDR-II Termination Reliability Metrics Part
/datasheets/files/national/pf/lp2994.html
National 17/02/2005 14.11 Kb HTML lp2994.html