NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| SN74SSQE32882ZCJR | Texas Instruments | SN74SSQE32882 JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test | 
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| SN74SSQEC32882ZALR | Texas Instruments | JEDEC SSTE32882 Compliant Low Power 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 |
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| SN74SSQEA32882ZALR | Texas Instruments | JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 |
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| SN74SSQE32882ZALR | Texas Instruments | JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 |
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| SN74SSQEB32882ZALR | Texas Instruments | JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: [2-0] Support Device Bit[7-3] Reserved [SSTE32882]: RC1 (MS Nibble) / RC0 (LS Nibble) [SSTE32882]: RC3 , /DBA0,1 value, Command/Address B Outputs [SSTE32882]: RC5 (MS Nibble) / RC4 (LS Nibble) - Drive Strength , value, Y0/Y0# and Y2/Y2# Clock Outputs [SSTE32882]: RC7 (MS Nibble) / RC6 (LS Nibble). [SSTE32882]: RC9 (MS Nibble) / RC8 (LS Nibble). [SSTE32882]: RC11 (MS Nibble) / RC10 (LS Nibble). [SSTE32882]: RC13 (MS Nibble) / RC12 (LS Nibble). [SSTE32882]: RC15 (MS Nibble) / RC14 (LS Nibble). Module-Specific Section ... | Original |
13 pages, |
rdimm thermal PC3-12800R-11-11-A0 Dataram Corporation PC3-12800 SSTE32882 DTM64369C PC3-10600 PC3-8500 PC3-6400 DDR3-1600 DTM64369C abstract |
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| Abstract: About CMR Commands 1 www.ti.com About CMR Commands SSTE32882-compliant DDR3 registers have , both DCS0# and DCS1# or DCS2# and DCS3# or all four DCS[n:0]. SSTE32882-compliant DDR3 Registers , are compliant with the JEDEC SSTE32882 specification. 1 2 3 4 Contents About CMR Commands , are LOW. According SSTE32882 JEDEC specification, DA5 through DA15 must be LOW to access the , Pair Differential Clock PLL Driver data sheet (SCAS879 SCAS879) 3. SSTE32882 JEDEC Specification SCAA102 SCAA102 ... | Original |
8 pages, |
SCAA102 RC12 RC11 RC10 TI ddr3 controller SSTE32882 SCAA102 abstract |
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| Abstract: SSTE32882-compliant DDR3 registers have internal control bits (also called Control Mode registers) to configure , both DCS0# and DCS1# or DCS2# and DCS3# or all four DCS[n:0]. SSTE32882-compliant DDR3 registers , them, see the SSTE32882 JEDEC Specification or TI application report SCAA102 SCAA102. 2 Extended CMR , Programming for DDR3 Registers application report (SCAA102 SCAA102) 4. SSTE32882 JEDEC Specification 4 ... | Original |
5 pages, |
SN74SSQE32882 CMR23 dba1 SSTE32882 SCAA108 SN74SSQEA32882 SCAA108 abstract |
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| Abstract: SN74SSQE32882ZALR SN74SSQE32882ZALR Part Number/Top Marking information March 2008 Part Number SN74SSQE32882ZALR SN74SSQE32882ZALR SN74: Standard Prefix for commercial Products Derived from JEDEC naming for DDR3 Register (SSTE32882) E: 1.5V Voltage Range, up to DDR3-1333 DDR3-1333 Q: QuadRank Support ZAL: Package Designator R: Tape&Reel Packing Top Marking TE32882 TE32882 YMZLLSG1 Top Marking Scheme : YM: Year and Month Z: Example top marking Revision Information (E=V3.1 ... | Original |
4 pages, |
SN74SSQE32882ZALR SN74 DDR3-1333 32882 marking ti texas instruments assembly year SSTE32882 SN74SSQE32882ZALR abstract |
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| Abstract: SSTE32882 00h 69 Register Control Word Functions(RC0/RC1) Default 00h 70 Register ... | Original |
2 pages, |
samsung ddr3 RC12 RC11 RC10 K4B2G0446 SSTE32882 HCH9 samsung dimm DDR3 SPD inphi M393B1K70BH1-CF701/CF801/CH901/CK001 K4B2G0446B-HCF7/HCF8/HCH9/HCK0 GS-04 M393B1K70BH1-CF701/CF801/CH901/CK001 abstract |
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| Abstract: SSTE32882 00h Register Control Word Functions(RC0/RC1) Default 00h 70 Register Control ... | Original |
2 pages, |
samsung dimm DDR3 SPD samsung DDR3 SDRAM 2GB samsung ddr3 RC12 RC11 RC10 K4B2G0446B-HCF7 DDR3 DIMM SPD JEDEC inphi M393B5270BH1-CF701/CF801/CH901/CK001 K4B2G0446B-HCF7/HCF8/HCH9/HCK0 GS-04 M393B5270BH1-CF701/CF801/CH901/CK001 abstract |
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| Abstract: IDT LV-DDR3 B 61h SSTE32882 00h Register Control Word Functions(RC0/RC1) Default 00h ... | Original |
2 pages, |
samsung ddr3 RC12 RC11 RC10 K4B1G0846E HCH9 samsung dimm DDR3 SPD CF804 SSTE32882 M393B5673EH1-CF704/CF804/CH904/CK004 K4B1G0846E-HCF7/HCF8/HCH9/HCK0 M393B5673EH1-CF704/CF804/CH904/CK004 abstract |
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| Abstract: B3h Inphi GS-04 GS-04 B2 03h SSTE32882 00h Register Control Word Functions(RC0/RC1 ... | Original |
2 pages, |
samsung ddr3 RC12 RC11 RC10 SSTE32882 samsung dimm DDR3 SPD inphi M393B5673EH1-CF701/CF801/CH901/CK001 K4B1G0846E-HCF7/HCF8/HCH9/HCK0 GS04-B2 M393B5673EH1-CF701/CF801/CH901/CK001 abstract |
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| Abstract: signal travel speed. The SSTE32882HLB has two basic modes of operation associated with the Quad Chip , chip select outputs. SSTE32882HLB has occurred on the open-drain ERROUT pin (active low). The , clock has been supplied, RESET must be held in the low state during power-up. The SSTE32882HLB is , SSTE32882HLB includes a high-performance, low-jitter, low-skew buffer that distributes a differential clock , When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The SSTE32882HLB ... | Original |
73 pages, |
optimum recievers DDR3 layout DDR3 pcb layout DDR3L JESD8-11A DA11 QAA14 QBA11 QBA15 DA10 dba1 qbba1 SSTE32882HLB transistor DA3 307 SSTE32882HLB abstract |
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| Abstract: DATASHEET 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT SSTE32882HLB , speed. The SSTE32882HLB has two basic modes of operation associated with the Quad Chip Select Enable , SSTE32882HLB includes a high-performance, low-jitter, low-skew buffer that distributes a differential clock , is grounded, the PLL is turned off and bypassed for test purposes. The SSTE32882HLB operates from a , is reduced. The SSTE32882HLB accepts a parity bit from the memory controller on the parity (PAR_IN ... | Original |
73 pages, |
JESD8-11A dba1 SSTE32882 SSTE32882HLB SSTE32882HLB abstract |
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| Texas Instruments Part | Industry Part | Manufacturer | Type | Comment | Description |
| SN74SSQE32882 Buy | SSTE32882HLB Buy | Integrated Device Technology | Direct Replacement | JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test | |
| SN74SSQEB32882 Buy | SSTE32882KA1 Buy | Integrated Device Technology | Direct Replacement | JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test | |
| SN74SSQEC32882 Buy | SSTE32882KB1 Buy | Integrated Device Technology | Direct Replacement | JEDEC SSTE32882 Compliant Low Power 28-Bit to 56-Bit Registered Buffer with Address-Parity Test |