SST45LF010 S71128-04-000 00000H SST45LF010-10-4C-SA-DD014 0000H 0001H A23-A16

SST45LF010 Data Sheet SST45LF0101Mb 4-wire Serial Interface flash memory FEATURES: · · · · Single

1 Mbit Serial Flash SST45LF010 SST45LF010 Data Sheet SST45LF0101Mb 4-wire Serial Interface flash memory FEATURES: · · · · Single 3.0-3.6V Read and Write Operations Serial Interface Architecture Byte Serial Read with Single Command Superior Reliability Endurance: 100,000 Cycles (typical) Greater than 100 years Data Retention · Low Power Consumption Active Current: 10 mA (typical) Standby Current: 10 µA (typical) · Sector or Chip-Erase Capability Uniform 4 KByte sectors · Fast Erase and Byte-Program Chip-Erase Time: 70 ms (typical) Sector-Erase Time: 18 ms (typical) Byte-Program Time: 14 µs (typical) · Automatic Write Timing Internal VPP Generation · End-of-Write Detection Software Status · 10 MHz Max Clock Frequency · Hardware Reset Pin (RST#) Resets the device to Standby Mode · CMOS I/O Compatibility · Hardware Data Protection (WP#) Protects and unprotects the device from Write operation · Packages Available 8-lead SOIC (4.9mm x 6mm) 8-contact WSON PRODUCT DESCRIPTION The SST45LF010 SST45LF010 is a 1 Mbit serial flash memory manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The 1 Mbit of memory is organized as 32 sectors of 4096 Bytes. The flash memory uses a 4wire serial interface and a chip enable to select and sequentially access its data. The serial interface consists of; serial data input (SI), serial data output (SO), serial clock (SCK), and chip enable (CE#). A write protect (WP#) inhibits the entire memory from Write operation and a hardware reset pin (RST#) resets the device to standby mode. Read The SST45LF010 SST45LF010 device is offered in both 8-lead SOIC and 8-contact WSON packages. See Figure 2 for the pin assignments. Sector/Chip-Erase Operation Device Operation The SST45LF010 SST45LF010 uses bus cycles of 8 bits each for commands, data, and addresses to execute operations. The operation instructions are listed in Table 3. All instructions are synchronized off a high to low transition of CE#. The first low to high transition on SCK will initiate the instruction sequence. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. Any low to high transition on CE# before the input instruction completes will terminate any instruction in progress and return the device to the standby mode. ©2003 Silicon Storage Technology, Inc. S71128-04-000 S71128-04-000 3/03 372 1 The Read operation outputs the data in order from the initial accessed address. While SCK is input, the address will be incremented automatically until end (top) of the address space (1FFFFH), then the internal address pointer automatically increments to beginning (bottom) of the address space (00000H 00000H), and data out stream will continue. The read data stream is continuous through all addresses until terminated by a low to high transition on CE#. The Sector-Erase operation clears all bits in the selected sector to FFH. The Chip-Erase instruction clears all bits in the device to FFH. Byte-Program Operation The Byte-Program operation programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. The data is input from bit 7 to bit 0 in order. Software Status Operation The Status operation determines if an Erase or Program operation is in progress. If bit 0 is at a "0" an Erase or Program operation is in progress, the device is busy. If bit 0 is at a "1" the device is ready for any valid operation. The status read is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 1 Mbit Serial Flash SST45LF010 SST45LF010 Data Sheet Reset Reduced-Function Option (SST45LF010-10-4C-SA-DD014 SST45LF010-10-4C-SA-DD014) Reset will terminate any operation, e.g., Read, Erase and Program, in progress. It is activated by a high to low transition on the RST# pin. The device will remain in reset condition as long as RST# is low. Minimum reset time is 10 µs. See Figure 15 for reset timing diagram. RST# is internally pulled-up and could remain unconnected during normal operation. After reset, the device is in standby mode, a high to low transition on CE# is required to start the next operation. The SST45LF010-10-4C-SA-DD014 SST45LF010-10-4C-SA-DD014 is a reduced-function option of the SST45LF010-10-4C-xA. For these devices, SST only tests and guarantees functionality when separate serial input and serial output data lines are used. Valid connections must be as illustrated in Figure 1. The RESET# pin is not tested during production; it must be left unconnected or tied to VDD. An internal power-on reset circuit protects against accidental data writes. Applying a logic level low to RST# during the power-on process then changing to a logic level high when VDD has reached the correct voltage level will provide additional protection against accidental writes during power on. Host Controller SST45LF010-10-4C-SA-DD014 SST45LF010-10-4C-SA-DD014 Read SST ID/Read Device ID SCK The Read SST ID and Read Device ID operations read the JEDEC assigned manufacturer's identification and the manufacturer assigned device IDs. These IDs may be used to determine the actual device resident in the system. SCK SO SI SI SO TABLE 1: PRODUCT IDENTIFICATION 372 ILL F21.0 Byte Data Manufacturer's ID 0000H 0000H BFH Device ID 0001H 0001H 42H FIGURE 1: VALID CONNECTIONS FOR SST45LF010-10-4C-SA-DD014 SST45LF010-10-4C-SA-DD014 T1.2 372 Write Protect The WP# pin provides inadvertent write protection. The WP# pin must be held high for any Erase or Program operation. The WP# pin can be VIL or VIH, but no other value, for all other operations. In typical use, the WP# pin is connected to VSS with a standard pull-down resistor. WP# is then driven high whenever an Erase or Program operation is required. If the WP# pin is tied to VDD with a pull-up resistor, then all operations may occur and the write protection feature is disabled. The WP# pin has an internal pull-up and could remain unconnected when not used. ©2003 Silicon Storage Technology, Inc. S71128-04-000 S71128-04-000 3/03 2 372 1 Mbit Serial Flash SST45LF010 SST45LF010 Data Sheet FUNCTIONAL BLOCK DIAGRAM SuperFlash Memory X - Decoder Address Buffers and Latches Y - Decoder I/O Buffers and Data Latches Control Logic Serial Interface CE# SCK SI SO ©2003 Silicon Storage Technology, Inc. WP# RST# 372 ILL B1.4 S71128-04-000 S71128-04-000 3/03 3 372 1 Mbit Serial Flash SST45LF010 SST45LF010 Data Sheet WP# 1 VDD 8 2 RST# WP# 1 7 VSS VDD 2 Top View 8 RST# 7 VSS Top View CE# 3 6 SO CE# 3 6 SO SCK 4 5 SI SCK 4 5 SI 372 ILL F01a.2 372 ILL F01.6 8-LEAD SOIC 8-CONTACT WSON FIGURE 2: PIN ASSIGNMENTS TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. SI Serial Data Input To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. SO Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. CE# Chip Enable The device is enabled by a high to low transition on CE#. WP# Write Protect To protect the device from unintentional Write (Erase or Program) operations. When WP# is low, all Erase and Program commands are ignored. When WP# is high, the device may be erased or programmed. This pin has an internal pull-up and could remain unconnected when not used. RST# Reset A high to low transition on RST# will terminate any operation in progress and reset the internal logic to the standby mode. The device will remain in the reset condition as long as the RST# is low. Operations may only occur when RST# is high. This pin has an internal pull-up and could remain unconnected when not used. VDD Power Supply To provide power supply (3.0-3.6V). VSS Ground T2.5 372 ©2003 Silicon Storage Technology, Inc. S71128-04-000 S71128-04-000 3/03 4 372 1 Mbit Serial Flash SST45LF010 SST45LF010 Data Sheet TABLE 3: DEVICE OPERATION INSTRUCTIONS1 Bus Cycle2 1 2 3 4 Cycle Type/ Operation3,4 SIN SOUT SIN SOUT SIN SOUT SIN Read FFH Hi-Z A23-A16 A23-A16 Hi-Z A15-A8 A15-A8 Hi-Z A7-A0 Sector-Erase5 20H Hi-Z A23-A16 A23-A16 Hi-Z A15-A8 A15-A8 Hi-Z X 5 SOUT 6 7 SIN SOUT SIN SOUT SIN SOUT Hi-Z X Hi-Z X Hi-Z X DOUT Hi-Z D0H Hi-Z X Hi-Z X Hi-Z Chip-Erase 60H Hi-Z X Hi-Z X Hi-Z X Hi-Z D0H Hi-Z X Hi-Z X Hi-Z Byte-Program 10H Hi-Z A23-A16 A23-A16 Hi-Z A15-A8 A15-A8 Hi-Z A7-A0 Hi-Z DIN Hi-Z X Hi-Z X Hi-Z X Note6 X Note6 X Note6 X Note6 ID Addr7 Hi-Z X DOUT7 X Note8 X Status Reg. 9FH X X DOUT X Note6 Read-ID 90H Hi-Z 00H Hi-Z 00H Hi-Z Note8 T3.10 372 1. 2. 3. 4. 5. 6. 7. 8. For SST45LF010 SST45LF010, A23-A17 A23-A17 can be VIL or VIH, but no other value. One bus cycle is eight clock periods Operation: SIN=Serial In, SOUT=Serial Out X = Dummy cycles (can be VIL or VIH, but no other value.) A16-A12 A16-A12 are used to determine sector address, A11-A8 A11-A8 can be VIL or VIH, but no other value. The status read is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. Manufacturer's ID = BFH, is read with A0 = 0 and Device ID = 42H, is read with A0 = 1; All other address bits are 0 The data output is arbitrary. TABLE 4: DEVICE OPERATION TABLE Operation SI SO CE#1 WP# RST# Read X DOUT Low X High Sector-Erase X X Low High High Chip-Erase X X Low High High DIN X Low High High Software-Status X DOUT Low X High Reset2 X X X X Low Read SST ID X DOUT Low X High Read Device ID X DOUT Low X High Byte-Program T4.6 372 1. A high to low transition on CE# will be required to start any device operation except for Reset. 2. The RST# low will return the device to standby and terminate any Erase or Program operation in progress. ©2003 Silicon Storage Technology, Inc. S71128-04-000 S71128-04-000 3/03 5 372 1 Mbit Serial Flash SST45LF010 SST45LF010 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (