SST39WF400A SST39WF400A1 S71220-05-000 5555H DQ15DQ8 0000H 00BFH 0001H 272FH - Datasheet Archive

 

SST39WF400A SST39WF400A1.8V 4Mb (x16) MPF memory Data Sheet FEATURES: · Organized as 256K x16 · Single Voltage Read

 

4 Mbit (x16) Multi-Purpose Flash SST39WF400A SST39WF400A SST39WF400A1 SST39WF400A1.8V 4Mb (x16) MPF memory Data Sheet FEATURES: · Organized as 256K x16 · Single Voltage Read and Write Operations ­ 1.65-1.95V · Superior Reliability ­ Endurance: 100,000 Cycles (typical) ­ Greater than 100 years Data Retention · Low Power Consumption (typical values at 5 MHz) ­ Active Current: 5 mA (typical) ­ Standby Current: 1 µA (typical) · Sector-Erase Capability ­ Uniform 2 KWord sectors · Block-Erase Capability ­ Uniform 32 KWord blocks · Fast Read Access Time ­ 90 ns ­ 100 ns · Latched Address and Data · Fast Erase and Word-Program ­ Sector-Erase Time: 36 ms (typical) ­ Block-Erase Time: 36 ms (typical) ­ Chip-Erase Time: 140 ms (typical) ­ Word-Program Time: 28 µs (typical) · Automatic Write Timing ­ Internal VPP Generation · End-of-Write Detection ­ Toggle Bit ­ Data# Polling · CMOS I/O Compatibility · JEDEC Standard ­ Flash EEPROM Pinouts and command sets · Packages Available ­ 48-ball TFBGA (6mm x 8mm) ­ 48-ball WFBGA (4mm x 6mm) Micro-Package ­ 48-bump XFLGA (4mm x 6mm) Micro-Package PRODUCT DESCRIPTION The SST39WF400A SST39WF400A device is a 256K x16 CMOS MultiPurpose Flash (MPF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39WF400A SST39WF400A writes (Program or Erase) with a 1.65-1.95V power supply. This device conforms to JEDEC standard pin assignments for x16 memories. Featuring high-performance Word-Program, the SST39WF400A SST39WF400A device provides a typical Word-Program time of 28 µsec. The device uses Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent writes, it has on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, this device is offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39WF400A SST39WF400A device is suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, it significantly improves performance and reliability, while lowering power consumption. It inherently uses less energy ©2004 Silicon Storage Technology, Inc. S71220-05-000 S71220-05-000 6/04 1 during Erase and Program than alternative flash technologies. When programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet surface mount requirements, the SST39WF400A SST39WF400A is offered in both a 48-ball TFBGA package and 48-ball Micro-Packages. See Figures 1 and 2 for pin assignments. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 4 Mbit Multi-Purpose Flash SST39WF400A SST39WF400A Data Sheet Device Operation operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-ofErase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 9 and 10 for timing waveforms. Any commands issued during the Sectoror Block-Erase operation are ignored. Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Read The Read operation of the SST39WF400A SST39WF400A is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3). Chip-Erase Operation The SST39WF400A SST39WF400A provides a Chip-Erase operation, which allows the user to erase the entire memory array to the "1" state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 8 for timing diagram, and Figure 19 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. Word-Program Operation The SST39WF400A SST39WF400A is programmed on a word-by-word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 40 µs. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 16 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. Write Operation Status Detection The SST39WF400A SST39WF400A provides two software means to detect the completion of a write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile Write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both Reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST39WF400A SST39WF400A offers both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase ©2004 Silicon Storage Technology, Inc. S71220-05-000 S71220-05-000 2 6/04 4 Mbit Multi-Purpose Flash SST39WF400A SST39WF400A Data Sheet Data# Polling (DQ7) Software Data Protection (SDP) When the SST39WF400A SST39WF400A is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling timing diagram and Figure 17 for a flowchart. The SST39WF400A SST39WF400A provides the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. This group of devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15DQ8 DQ15DQ8 can be VIL or VIH, but no other value, during any SDP command sequence. Common Flash Memory Interface (CFI) Toggle Bit (DQ6) The SST39WF400A SST39WF400A also contains the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as Software ID Entry command with 98H (CFI Query command) to address 5555H 5555H in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 5 through 7. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle Bit timing diagram and Figure 17 for a flowchart. Data Protection The SST39WF400A SST39WF400A provides both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.0V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. ©2004 Silicon Storage Technology, Inc. S71220-05-000 S71220-05-000 3 6/04 4 Mbit Multi-Purpose Flash SST39WF400A SST39WF400A Data Sheet Product Identification Product Identification Mode Exit/ CFI Mode Exit The Product Identification mode identifies the devices as the SST39WF400A SST39WF400A and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 11 for the Software ID Entry and Read timing diagram, and Figure 18 for the Software ID Entry command sequence flowchart. In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 13 for timing waveform, and Figure 18 for a flowchart. TABLE 1: PRODUCT IDENTIFICATION TABLE Address Data 0000H 0000H 00BFH 00BFH 0001H 0001H Manufacturer's ID 272FH 272FH Device ID SST39WF400A SST39WF400A T1.0 1220 FUNCTIONAL BLOCK DIAGRAM X-Decoder Memory Address SuperFlash Memory Address Buffer & Latches Y-Decoder CE# OE# I/O Buffers and Data Latches Control Logic WE# DQ15 - DQ0 1220 B1.0 ©2004 Silicon Storage Technology, Inc. S71220-05-000 S71220-05-000 4 6/04 4 Mbit Multi-Purpose Flash SST39WF400A SST39WF400A Data Sheet TOP VIEW (balls facing down) SST39WF400A SST39WF400A 6 A13 A12 A14 A15 A16 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 WE# NC NC NC DQ5 DQ12 VDD DQ4 NC NC NC NC DQ2 DQ10 DQ11 DQ3 A7 A17 A6 A5 A3 A4 A2 A1 A0 CE# OE# VSS A B C D E F 5 NC DQ15 VSS 3 2 DQ0 DQ8 DQ9 DQ1 1 G 1220 48-tfbga P01.0 4 H FIGURE 1: PIN ASSIGNMENTS FOR 48-BALL 48-BALL TFBGA TOP VIEW (balls facing down) SST39WF400A SST39WF400A 6 A2 A4 A6 A17 A1 A3 A7 NC A0 A5 NC WE# A9 A11 A10 A13 A14 A8 NC NC NC NC A12 A15 5 3 CE# DQ8 DQ10 VSS OE# DQ9 DQ4 DQ11 A16 2 NC NC DQ5 DQ6 DQ7 1 DQ0 DQ1 DQ2 DQ3 A B C D E VDD DQ12 DQ13 DQ14 DQ15 VSS F G H J K 1220 48-wfbga-xflga P03_4.0 4 L FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL 48-BALL WFBGA AND 48-BUMP 48-BUMP XFLGA ©2004 Silicon Storage Technology, Inc. S71220-05-000 S71220-05-000 5 6/04 4 Mbit Multi-Purpose Flash SST39WF400A SST39WF400A Data Sheet TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses. During Sector-Erase AMS-A11 AMS-A11 address lines will select the sector. During Block-Erase AMS-A15 AMS-A15 address lines will select the block. DQ15-DQ0 DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. VDD Power Supply To provide power supply voltage: VSS Ground NC No Connection 1.65-1.95V for SST39WF400A SST39WF400A Unconnected pins. T2.0 1220 1. AMS = Most significant address AMS = A17 for SST39WF400A SST39WF400A TABLE 3: OPERATION MODES SELECTION Mode CE# OE# WE# Read Program DQ Address VIL VIL VIL VIH VIH DOUT AIN VIL DIN AIN X1 Sector or Block address, XXH for Chip-Erase Erase VIL VIH VIL Standby VIH X X High Z X X VIL X High Z/ DOUT X X X VIH High Z/ DOUT X VIL VIL VIH Write Inhibit Product Identification Software Mode See Table 4 T3.0 1220 1. X can be VIL or VIH, but no other value. ©2004 Silicon Storage Technology, Inc. S71220-05-000 S71220-05-000 6 6/04 4 Mbit Multi-Purpose Flash SST39WF400A SST39WF400A Data Sheet TABLE 4: SOFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle Addr1 Data2 2nd Bus Write Cycle Addr1 Data2 3rd Bus Write Cycle Addr1 4th Bus Write Cycle Data2 Addr1 Data2 6th Bus Write Cycle Data AAH 5th Bus Write Cycle Word-Program 5555H 5555H AAH 2AAAH 55H 5555H 5555H A0H WA3 Sector-Erase 5555H 5555H AAH 2AAAH 55H 5555H 5555H 80H 5555H 5555H Addr1 Data2 Addr1 Data2 2AAAH 55H SAX4 30H 4 Block-Erase 5555H 5555H AAH 2AAAH 55H 5555H 5555H 80H 5555H 5555H AAH 2AAAH 55H BAX Chip-Erase 5555H 5555H AAH 2AAAH 55H 5555H 5555H 80H 5555H 5555H AAH 2AAAH 55H 5555H 5555H Software ID Entry5,6 5555H 5555H AAH 2AAAH 55H 5555H 5555H 90H CFI Query Entry5 5555H 5555H AAH 2AAAH 55H 5555H 5555H 98H XXH F0H 5555H 5555H AAH 2AAAH 55H 5555H 5555H F0H Software ID CFI Exit Exit7/ Software ID Exit7/ CFI Exit 50H 10H T4.0 1220 1. Address format A14-A0 A14-A0 (Hex), Addresses AMS-A15 AMS-A15 can be VIL or VIH, but no other value, for the Command sequence. AMS = Most significant address AMS = A17 for SST39WF400A SST39WF400A 2. DQ15-DQ8 DQ15-DQ8 can be VIL or VIH, but no other value, for the Command sequence 3. WA = Program word address 4. SAX for Sector-Erase; uses AMS-A11 AMS-A11 address lines BAX for Block-Erase; uses AMS-A15 AMS-A15 address lines 5. The device does not remain in Software Product ID mode if powered down. 6. With AMS-A1 = 0; SST Manufacturer's ID = 00BFH 00BFH, is read with A0 = 0, SST39WF400A SST39WF400A Device ID = 272FH 272FH, is read with A0 = 1. 7. Both Software ID Exit operations are equivalent TABLE 5: CFI QUERY IDENTIFICATION STRING1 FOR SST39WF400A SST39WF400A Address 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Data 0051H 0051H 0052H 0052H 0059H 0059H 0001H 0001H 0007H 0007H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Data Query Unique ASCII string "QRY" Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits) T5.0 1220 1. Refer to CFI publication 100 for more details. ©2004 Silicon Storage Technology, Inc. S71220-05-000 S71220-05-000 7 6/04 4 Mbit Multi-Purpose Flash SST39WF400A SST39WF400A Data Sheet TABLE 6: SYSTEM INTERFACE INFORMATION FOR SST39WF400A SST39WF400A Address Data 1BH 0016H 0016H VDD Min (Program/Erase) Data 1CH 0020H 0020H VDD Max (Program/Erase) 1DH 0000H 0000H VPP min (00H = no VPP pin) 1EH 0000H 0000H VPP max (00H = no VPP pin) 1FH 0005H 0005H Typical time out for Word-Program 2N µs (25 = 32 µs) 20H 0000H 0000H Typical time out for min size buffer program 2N µs (00H = not supported) 21H 0005H 0005H Typical time out for individual Sector/Block-Erase 2N ms (25 = 32 ms) 22H 0007H 0007H Typical time out for Chip-Erase 2N ms (27 = 128 ms) 23H 0001H 0001H Maximum time out for Word-Program 2N times typical (21 x 25 = 64 µs) 24H 0000H 0000H Maximum time out for buffer program 2N times typical 25H 0001H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 25 = 64 ms) 26H 0001H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 27 = 256 ms) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts T6.0 1220 TABLE 7: DEVICE GEOMETRY INFORMATION FOR SST39WF400A SST39WF400A Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 0013H 0013H 0001H 0001H 0000H 0000H 0000H 0000H 0000H 0000H 0002H 0002H 007FH 007FH 0000H 0000H 0010H 0010H 0000H 0000H 0007H 0007H 0000H 0000H 0000H 0000H 0001H 0001H Data Device size = 2N Byte (13H = 19; 219 = 512 KByte) Flash Device Interface description; 0001H 0001H = x16-only asynchronous interface Maximum number of byte in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 127 + 1 = 128 sectors (007FH 007FH = 127) z = 16 x 256 Bytes = 4 KByte/sector (0010H 0010H = 16) Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 7 + 1 = 8 blocks (0007H 0007H = 7) z = 256 x 256 Bytes = 64 KByte/block (0100H 0100H = 256) T7.0 1220 ©2004 Silicon Storage Technology, Inc. S71220-05-000 S71220-05-000 8 6/04 4 Mbit Multi-Purpose Flash SST39WF400A SST39WF400A Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (