SST28SF040 SST28LF040 SST28VF040 28SF040 28LF040 28VF040 - Datasheet Archive

 

SST28SF040, SST28LF040, SST28VF040 Data Sheet FEATURES: · Single Voltage Read and Write Operations ­ 5.0V-only for the

 

4 Megabit (512K x 8) SuperFlash EEPROM SST28SF040 SST28SF040, SST28LF040 SST28LF040, SST28VF040 SST28VF040 Data Sheet FEATURES: · Single Voltage Read and Write Operations ­ 5.0V-only for the 28SF040 28SF040 ­ 3.0V-only for the 28LF040 28LF040 ­ 2.7V-only for the 28VF040 28VF040 · Superior Reliability ­ Endurance: 100,000 Cycles (typical) ­ Greater than 100 years Data Retention · Memory Organization: 512K x 8 · Sector Erase Capability: 256 bytes per Sector · Low Power Consumption ­ Active Current: 15 mA (typical) for 5.0V and 10 mA (typical) for 3.0/2.7V ­ Standby Current: 5 µA (typical) · Fast Sector Erase/Byte Program Operation ­ Byte Program Time: 35 µs (typical) ­ Sector Erase Time: 2 ms (typical) ­ Complete Memory Rewrite: 20 sec (typical) · Fast Read Access Time ­ 5.0V-only operation: 120 and 150 ns ­ 3.0V-only operation: 200 and 250 ns ­ 2.7V-only operation: 250 and 300 ns · Latched Address and Data · Hardware and Software Data Protection ­ 7-Read-Cycle-Sequence Software Data Protection · End of Write Detection ­ Toggle Bit ­ Data# Polling · TTL I/O Compatibility · Packages Available ­ 32-Pin TSOP (8 mm x 20 mm) ­ 32-Pin PLCC ­ 32-Pin PDIP 1 2 3 4 5 6 7 PRODUCT DESCRIPTION The 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 are 512K x 8 bit CMOS sector erase, byte program EEPROMs. The 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 are manufactured using SST's proprietary, high performance CMOS SuperFlash EEPROM Technology. The split gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternative approaches. The 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 erase and program with a single power supply. The 28SF040/ 28SF040/ 28LF040/28VF040 28LF040/28VF040 conform to JEDEC standard pinouts for byte wide memories and are compatible with existing industry standard EPROM, flash EPROM and EEPROM pinouts. Featuring high performance programming, the 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 typically byte program in 35 µs. The 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 typically sector erase in 2 ms. Both program and erase times can be optimized using interface features such as Toggle bit or Data# Polling to indicate the completion of the write cycle. To protect against an inadvertent write, the 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 have on chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 are offered with a guaranteed sector endurance of 104 or 103 cycles. Data retention is rated greater than 100 years. The 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 are best suited for applications that require reprogrammable nonvolatile mass storage of program, configuration, or data memory. For all system applications, the 28SF040/ 28SF040/ 28LF040/28VF040 28LF040/28VF040 significantly improve performance and reliability, while lowering power consumption when compared with floppy diskettes or EPROM approaches. EEPROM technology makes possible convenient and economical updating of codes and control programs online. The 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 improve flexibility, while lowering the cost of program and configuration storage application. The functional block diagram shows the functional blocks of the 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040. Figures 1 and 2 show the pin assignments for the 32 pin TSOP, 32 pin PDIP, and 32 pin PLCC packages. Pin description and operation modes are described in Tables 1 through 4. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Note, during the software data protection sequence the address are latched on the rising edge of OE# or CE#, whichever occurs first. © 1998 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 310-04 12/97 3 8 9 10 11 12 13 14 15 16 4 Megabit SuperFlash EEPROM SST28SF040 SST28SF040, SST28LF040 SST28LF040, SST28VF040 SST28VF040 Command Definitions Table 3 contains a command list and a brief summary of the commands. The following is a detailed description of the operations initiated by each command. write the entire memory array. The Chip_Erase operation will terminate after a maximum of 20 ms. A Reset command can be executed to terminate the Erase operation; however, if the Erase operation is terminated prior to the 20 ms time-out, the chip may not be completely erased. If an erase error occurs an erase command can be reissued as many times as necessary to complete the Erase operation. The 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 cannot be "overerased". (See Figure 7) Sector_Erase Operation The Sector_Erase operation erases all bytes within a sector and is initiated by a setup command and an execute command. A sector contains 256 bytes. This sector erasability enhances the flexibility and usefulness of the 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040, since most applications only need to change a small number of bytes or sectors, not the entire chip. Byte_Program Operation The Byte_Program operation is initiated by writing the setup command (10H). Once the program setup is performed, programming is executed by the next WE# pulse. See Figures 4 and 5 for timing waveforms. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first, and begins the program operation. The Program operation is terminated automatically by an internal timer. See Figure 15 for the programming flowchart. The setup command is performed by writing 20H to the device. The execute command is performed by writing D0H to the device. The Erase operation begins with the rising edge of the WE# or CE#, whichever occurs first and terminates automatically by using an internal timer. The end of Erase can be determined using either Data# Polling, Toggle Bit, or Successive Reads detection methods. See Figure 8 for timing waveforms. The two-step sequence of a setup command followed by an execute command ensures that only the addressed byte is programmed and other bytes are not inadvertently programmed. The two-step sequence of setup command followed by an execute command ensures that only memory contents within the addressed sector are erased and other sectors are not inadvertently erased. The Byte_Program Flowchart Description Programming data into the 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 is accomplished by following the Byte_Program flowchart shown in Figure 15. The Byte_Program command sets up the byte for programming. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first and begins the Program operation. The end of program can be detected using either the Data# Polling, Toggle bit, or Successive reads. Sector_Erase Flowchart Description Fast and reliable erasing of the memory contents within a sector is accomplished by following the sector erase flowchart as shown in Figure 17. The entire procedure consists of the execution of two commands. The Sector_Erase operation will terminate after a maximum of 4 ms. A Reset command can be executed to terminate the erase operation; however, if the Erase operation is terminated prior to the 4 ms time-out, the sector may not be fully erased. An erase command can be reissued as many times as necessary to complete the erase operation. The 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 cannot be "overerased". Reset Operation The Reset command is provided as a means to safely abort the Erase or Program command sequences. Following either setup commands (erase or program) with a write of FFH will safely abort the operation. Memory contents will not be altered. After the Reset command, the device returns to the read mode. The Reset command does not enable software data protection. See Figure 7 for timing waveforms. Chip_Erase Operation The Chip_Erase operation is initiated by a setup command (30H) and an execute command (30H). The Chip_Erase operation allows the entire array of the 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 to be erased in one operation, as opposed to 2048 sector erase operations. Using the Chip_Erase operation will minimize the time to re- © 1998 Silicon Storage Technology, Inc. 2-4 310-04 12/97 4 Megabit SuperFlash EEPROM SST28SF040 SST28SF040, SST28LF040 SST28LF040, SST28VF040 SST28VF040 Read The Read operation is initiated by setting CE#, and OE# to logic low and setting WE# to logic high (See Table 2). See Figure 3 for read memory timing waveform. The Read operation from the host retrieves data from the array. The device remains enabled for read until another operation mode is accessed. During initial power-up, the device is in the Read mode and is software data protected. The device must be unprotected to execute a Write command. Software Data Protection (SDP) The 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 have software methods to further prevent inadvertent writes. In order to perform an Erase or Program operation, a two-step command sequence consisting of a set-up command followed by an execute command avoids inadvertent erasing and programming of the device. The 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 will default to software data protection after power up. A sequence of seven consecutive reads at specific addresses will unprotect the device The address sequence is 1823H 1823H, 1820H 1820H, 1822H 1822H, 0418H 0418H, 041BH 041BH, 0419H 0419H, 041AH 041AH. The address bus is latched on the rising edge of OE# or CE#, whichever occurs first. A similar seven read sequence of 1823H 1823H, 1820H 1820H, 1822H 1822H, 0418H 0418H, 041BH 041BH, 0419H 0419H, 040AH 040AH will protect the device. Also refer to Figures 9 and 10 for the 6 read cycle sequence Software Data Protection. The I/O pins can be in any state (i.e., high, low, or tristate). The Read operation of the 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 are controlled by OE# and CE# at logic low. When CE # is high, the chip is deselected and only standby power will be consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when CE# or OE# are high. Read_ID operation The Read_ID operation is initiated by writing a single command (90H). A read of address 0000H 0000H will output the manufacturer's code (BFH). A read of address 0001H 0001H will output the device code (04H). Any other valid command will terminate this operation. 2 3 4 5 6 Write Operation Status Detection The 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 provide three means to detect the completion of a write cycle, in order to optimize the system write cycle time. The end of a write cycle (erase or program) can be detected by three means: 1) monitoring the Data# Polling bit; 2) monitoring the Toggle bit; or 3) by two successive reads of the same data. These three detection mechanisms are described below. Hardware Data Protection The 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 are designed with hardware features to prevent inadvertent writes. This is done in the following ways: 1. Write Inhibit Mode: OE# low, CE#, or WE# high will inhibit the Write operation. 2. Noise/Glitch Protection: A WE# pulse width of less than 15 ns will not initiate a write cycle. 3. VCC Power Up/Down Detection: The Write operation is inhibited when VCC is less than 2.5V. 7 The actual completion of the nonvolatile Write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with the DQ used. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. Data Protection In order to protect the integrity of nonvolatile data storage, the 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 provide both hardware and software features to prevent inadvertent writes to the device, for example, during system powerup or power-down. Such provisions are described below. 10 Data# Polling (DQ7) The 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 feature Data# Polling to indicate the Write operation status. During a Write operation, any attempt to read the last byte loaded during the byte-load cycle will receive the complement of the true data on DQ7. Once the write cycle is completed, DQ7 will show true data. The device is then ready for the next operation. See Figure 11 for Data Polling timing waveforms. In order for Data# Polling to function correctly , the byte being polled must be erased prior to programming. 4. After power-up the device is in the read mode and the device is in the software data protect state. © 1998 Silicon Storage Technology, Inc. 1 2-5 310-04 12/97 8 9 11 12 13 14 15 16 4 Megabit SuperFlash EEPROM SST28SF040 SST28SF040, SST28LF040 SST28LF040, SST28VF040 SST28VF040 Toggle Bit ( DQ6) An alternative means for determining the Write operation status is by monitoring the Toggle Bit, DQ6. During a Write operation, consecutive attempts to read data from the device will result in DQ6 toggling between logic 0 (low) and logic 1 (high). When the write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 12 for Toggle Bit timing waveforms. Product Identification The Product Identification mode identifies the device as 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 and the manufacturer as SST. This mode may be accessed by hardware and software operations. The hardware operation is typically used by an external programmer to identify the correct algorithm for the 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040. Users may wish to use the software operation to identify the device (i.e., using the device code). For details see Table 2 for the hardware operation and Figure 18 for the software operation. The manufacturer and device codes are the same for both operations. Successive Reads An Alternative means for determining an end of a write cycle is by reading the same address for two consecutive data matches. PRODUCT IDENTIFICATION TABLE Manufacturer's Code Device Code Byte 0000 H 0001 H Data BF H 04 H FUNCTIONAL BLOCK DIAGRAM OF SST 28SF040/28LF040/28VF040 28SF040/28LF040/28VF040 X-Decoder A18-A0 A18-A0 4,194,304 Bit EEPROM Cell Array Address buffer & Latches Y-Decoder CE# OE# Control Logic I/O Buffers and Data Latches WE# DQ7 - DQ0 310 MSW B1.2 © 1998 Silicon Storage Technology, Inc. 2-6 310-04 12/97 4 Megabit SuperFlash EEPROM SST28SF040 SST28SF040, SST28LF040 SST28LF040, SST28VF040 SST28VF040 A11 A9 A8 A13 A14 A17 WE# VCC A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Standard Pinout Top View Die up OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 1 2 3 4 310 MSW F01.0 5 FIGURE 1: STANDARD PIN ASSIGNMENTS FOR 32-PIN 32-PIN TSOP PACKAGES 6 A18 1 32 A16 A15 2 3 31 30 A12 A7 4 5 29 28 A6 A5 A4 A3 6 7 27 26 32-Pin PDIP 8 25 Top View 24 9 A2 A1 10 11 A0 DQ0 12 13 23 22 21 20 DQ1 DQ2 14 15 19 18 Vss 16 17 A15 Vcc WE# A12 A17 A14 4 3 A18 WE# A16 Vcc A17 2 1 7 32 31 30 A13 A8 A7 5 29 A14 A6 6 28 A13 A9 A11 A5 7 27 A8 A4 8 26 A9 A3 9 25 A11 A2 10 24 OE# A1 11 23 A10 A0 12 22 CE# DQ0 13 21 DQ7 OE# A10 CE# DQ7 DQ6 DQ5 32-Lead PLCC Top View 14 15 16 DQ4 17 18 19 8 9 20 10 DQ3 DQ1 Vss DQ4 DQ6 DQ2 DQ3 DQ5 310 MSW F02.0 11 FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN 32-PIN PLASTIC DIPS AND 32-PIN 32-PIN PLCCS TABLE 1: PIN DESCRIPTION Symbol Pin Name A18-A8 A18-A8 Row Address Inputs A7-A0 Column Address Inputs DQ7-DQ0 Data Input/Output CE# OE# WE# Vcc Chip Enable Output Enable Write Enable Power Supply Vss Functions To provide memory addresses. Row addresses define a sector. Selects the byte within the sector. To output data during read cycles and receive input data during write cycles. Data is internally latched during a write cycle. The outputs are in tri-state when OE#, CE # is high. To activate the device when CE # is low. (1) To gate the data output buffers. (1) To control the write operations. (1) To provide 5-volt supply (± 10%) for the 28SF040 28SF040, 3-volt supply (3.0-3.6V) for the 28LF040 28LF040 and 2.7-volt supply (2.7-3.6V) for the 28VF040 28VF040 Ground Note: (1) This pin is considered an input for the purposes of the DC Operation Characteristics Table. 310 PGM T1.0 © 1998 Silicon Storage Technology, Inc. 310-04 12/97 2-7 12 13 14 15 16 4 Megabit SuperFlash EEPROM SST28SF040 SST28SF040, SST28LF040 SST28LF040, SST28VF040 SST28VF040 TABLE 2: OPERATION MODES SELECTION Mode CE# OE# Read VIL VIL Byte Program VIL VIH Sector Erase VIL VIH Standby VIH X Write Inhibit X VIL Write Inhibit X X Software Chip Erase VIL VIH Product Identification Hardware Mode VIL VIL Software Mode SDP Enable & Disable Mode Reset WE# VIH VIL VIL X X VIH VIL DQ DOUT DIN DIN High Z High Z/ DOUT High Z/ DOUT DIN Address AIN AIN, See Table 3 AIN, See Table 3 X X X See Table 3 VIH Manufacturer Code (BF) Device Code (04) VIL VIL VIL VIL VIH VIH A18-A1 A18-A1=VIL, A9=VH, A0=V IL A18-A1 A18-A1=VIL, A9=VH, A0=V IH See Table 3 See Table 3 VIL VIH VIL See Table 3 310 PGM T2.1 TABLE 3: SOFTWARE COMMAND SUMMARY Command Summary Sector_Erase Byte_Program Chip_Erase Reset Read_ID Software_Data_Protect Software_Data_Unprotect Notes: 1. 2. 3. 4. 5. 6. 7. 8. Required Setup Command Cycle Execute Command Cycle Cycle(s) Type(1) Addr(2,3) Data(4) Type(1) Addr(2,3) Data(4) 2 W X 20H W SA D0H 2 W X 10H W PA PD 2 W X 30H W X 30H 1 W X FFH 3 W X 90H R (8) (8) 7 R (6) 7 R (7) SDP(5) N N N Y Y 310 PGM T3.0 Type definition: W = Write, R = Read, X= don't care Addr (Address) definition: SA = Sector Address = A18 - A8, sector size = 256 bytes; A7- A0 = X for this command. Addr (Address) definition: PA = Program Address = A 18 - A0. Data definition: PD = Program Data, H = number in hex. SDP = Software Data Protect mode using 7 Read Cycle Sequence. a) Y = the operation can be executed with protection enabled b) N = the operation cannot be executed with protection enabled Refer to Figure 10 for the 7 Read Cycle sequence for Software_Data_Protect. Refer to Figure 9 for the 7 Read Cycle sequence for Software_Data_Unprotect. Address 0000H 0000H retrieves the manufacturer' code of BFH and address 0001H 0001H retrieves the device code of 04H. TABLE 4: MEMORY ARRAY DETAIL Sector Select Byte Select A18 - A8 A7 - A0 310 PGM T4.0 © 1998 Silicon Storage Technology, Inc. 2-8 310-04 12/97 4 Megabit SuperFlash EEPROM SST28SF040 SST28SF040, SST28LF040 SST28LF040, SST28VF040 SST28VF040 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . -55°C to +125°C Storage Temperature . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . -0.5V to VCC+ 0.5V Transient Voltage ( A12 ARE "DON'T CARE" 310 ILL F09.1 FIGURE 9: SOFTWARE DATA UNPROTECT TIMING DIAGRAM OE# TPCH TPCP CE# WE# ADDRESS 1823 TPAS 1820 1822 0418 041B 0419 040A TPAH NOTE: A. ADDRESSES ARE LA TCHED INTERNALLY ON THE RISING EDGE OF: 1. OE# IF CE# IS KEPT AT LOW ALL TIME. 2. CE# IF OE# IS KEPT AT LOW ALL TIME. 3. THE FIRST PIN TO GO HIGH IF BOTH ARE TOGGLED. B. ABOVE ADDRESS VALUES ARE IN HEX. C. ADDRESSES > A12 ARE "DON'T CARE" 310 ILL F10.2 FIGURE 10: SOFTWARE DATA PROTECT TIMING DIAGRAM © 1998 Silicon Storage Technology, Inc. 2-18 310-04 12/97 4 Megabit SuperFlash EEPROM SST28SF040 SST28SF040, SST28LF040 SST28LF040, SST28VF040 SST28VF040 1 2 3 4 5 6 310 AC F11.0 7 FIGURE 11: DATA# POLLING TIMING DIAGRAM 8 9 10 11 12 13 14 15 310 AC F12.0 FIGURE 12: TOGGLE BIT TIMING DIAGRAM © 1998 Silicon Storage Technology, Inc. 2-19 310-04 12/97 16 4 Megabit SuperFlash EEPROM SST28SF040 SST28SF040, SST28LF040 SST28LF040, SST28VF040 SST28VF040 2.4 2.0 INPUT 2.0 OUTPUT REFERENCE POINTS 0.8 0.8 0.4 310 MSW F13.0 AC test inputs are driven at VOH (2.4 VTTL) for a logic "1" and VOL (0.4 VTTL) for a logic "0". Measurement reference points for inputs and outputs are VIH (2.0 VTTL) and VIL (0.8 VTTL). Inputs rise and fall times (10% 90%) are