OMAP5910 SPRU677 SPRU671 SPRU672 SPRU673 SPRU674 SPRU675 SPRU676 SPRU678 - Datasheet Archive

 

Universal Serial Bus (USB) and Frame Adjustment Counter (FAC) Reference Guide Literature Number: SPRU677 October 2003 IMPORTANT

 

OMAP5910 OMAP5910 Dual-Core Processor Universal Serial Bus (USB) and Frame Adjustment Counter (FAC) Reference Guide Literature Number: SPRU677 SPRU677 October 2003 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated Preface Read This First About This Manual This document describes the universal serial bus (USB) and frame adjustment counter (FAC) host of the OMAP5910 OMAP5910 multimedia processor. Notational Conventions This document uses the following conventions. - Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. Related Documentation From Texas Instruments The following documents describe the OMAP5910 OMAP5910 device and related peripherals. Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com. OMAP5910 OMAP5910 Dual-Core Processor MPU Subsystem Reference Guide (literature number SPRU671 SPRU671) OMAP5910 OMAP5910 Dual-Core Processor DSP Subsystem Reference Guide (literature number SPRU672 SPRU672) OMAP5910 OMAP5910 Dual-Core Processor Memory Interface Traffic Controller Reference Guide (literature number SPRU673 SPRU673) OMAP5910 OMAP5910 Dual-Core Processor System DMA Controller Reference Guide (literature number SPRU674 SPRU674) OMAP5910 OMAP5910 Dual-Core Processor LCD Controller Reference Guide (literature number SPRU675 SPRU675) OMAP5910 OMAP5910 Dual-Core Processor Universal Asynchronous Receiver/Transmitter (UART) Devices Reference Guide (literature number SPRU676 SPRU676) SPRU677 SPRU677 5 Trademarks Related Documentation From Texas Instruments / Trademarks OMAP5910 OMAP5910 Dual-Core Processor Universal Serial Bus (USB) and Frame Adjustment Counter (FAC) Reference Guide (literature number SPRU677 SPRU677) OMAP5910 OMAP5910 Dual-Core Processor Clock Generation and System Reset Management Reference Guide (literature number SPRU678 SPRU678) OMAP5910 OMAP5910 Dual-Core Processor General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU679 SPRU679) OMAP5910 OMAP5910 Dual-Core Processor MMC/SD Reference Guide (literature number SPRU680 SPRU680) OMAP5910 OMAP5910 Dual-Core Processor Inter-Integrated Circuit (I2C) Controller Reference Guide (literature number SPRU681 SPRU681) OMAP5910 OMAP5910 Dual-Core Processor Timer Reference Guide (literature number SPRU682 SPRU682) OMAP5910 OMAP5910 Dual-Core Processor Inter-Processor Reference Guide (literature number SPRU683 SPRU683) Communication OMAP5910 OMAP5910 Dual-Core Processor Camera Interface Reference Guide (literature number SPRU684 SPRU684) OMAP5905 OMAP5905 Dual-Core Processor Multichannel Serial Interface (MCSI) Reference Guide (literature number SPRU685 SPRU685) OMAP5910 OMAP5910 Dual-Core Processor Micro-Wire Interface Reference Guide (literature number SPRU686 SPRU686) OMAP5910 OMAP5910 Dual-Core Processor Real-Time Clock (RTC) Reference Guide (literature number SPRU687 SPRU687) OMAP5910 OMAP5910 Dual-Core Processor HDQ/1-Wire Interface Reference Guide (literature number SPRU688 SPRU688) OMAP5910 OMAP5910 Dual-Core Processor PWL, PWT, and LED Peripheral Reference Guide (literature number SPRU689 SPRU689) OMAP5910 OMAP5910 Dual-Core Processor Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU708 SPRU708) Trademarks OMAP and the OMAP symbol are trademarks of Texas Instruments. 6 SPRU677 SPRU677 Contents Contents 1 USB Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 USB Open Host Controller Interface Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 OHCI Controller Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 OMAP5910 OMAP5910 USB Host Controller/OHCI Specification Differences . . . . . . . . . . . . . . . . . . 2.2.1 Power Switching Output Pins Not Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Overcurrent Protection Input Pins Not Supported . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 HMC_MODE and Top-Level Pin Multiplexing and OHCI Registers . . . . . . . . . . 2.2.4 No Ownership Change Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5 Valid Address Ranges for Pointers to Data Structures . . . . . . . . . . . . . . . . . . . . . 2.3 OMAP5910 OMAP5910 Implementation of OHCI Specification for USB . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Isochronous TD OFFSETX/PSWX Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 OMAP5910 OMAP5910 USB Host Controller Endpoint Descriptor (ED) List Head Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 14 14 15 15 15 15 15 15 3 USB Host Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 USB Host Controller Reserved Registers and Reserved Bit Fields . . . . . . . . . . . . . . . . . 3.2 Endianism and USB Host Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 USB Host Controller Registers, USB Reset, and USB Clocking . . . . . . . . . . . . . . . . . . . . 17 53 53 54 4 USB Host Controller Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 OHCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 OHCI Scheduling Overrun Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 OHCI HcDoneHead Writeback Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.3 OHCI Start Of Frame Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.4 OHCI Resume Detect Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.5 OHCI Unrecoverable Error Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.6 OHCI Frame Number Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.7 OHCI Root Hub Status Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.8 OHCI Ownership Change Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Local Bus MMU Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 55 55 55 55 55 55 56 56 56 56 5 USB Pin Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Host Controller Connectivity With USB Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 USB Function Controller Connectivity With USB Transceivers . . . . . . . . . . . . . . . . . . . . . 5.3 On-Board Transceiverless Connection Using OMAP5910 OMAP5910 Transceiverless Link Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 57 58 SPRU677 SPRU677 16 60 7 Contents 5.4 5.5 5.6 USB Signal Multiplexing Mode Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Ports Shown as Unconnected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Conflicts Between USB Signal Multiplexing and Top-Level Multiplexing . . . . . . . . . . . . . 92 6 USB Host Controller Access to System Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.1 Local Bus Virtual Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.2 Cache Coherency in OHCI Data Structures and Data Buffers . . . . . . . . . . . . . . . . . . . . . 96 6.3 Local Bus Addressing and OHCI Data Structure Pointers . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.3.1 MPUVAtoLBVA()-MPU Virtual Address to Local Bus Virtual Address Conversion Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.3.2 LBVAtoMPUVA()-Local Bus Virtual Address to MPU Virtual Address Conversion Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.3 MPUVAtoPA()-MPU Virtual Address to Physical Address Conversion Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.4 LBVAtoPA()-Local Bus Virtual Address to Physical Address Conversion Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.5 PAtoLBVA()-Physical Address to Local Bus Virtual Address Conversion Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.6 PAtoMPUVA()-Physical Address to MPU Virtual Address Conversion Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.7 Physical, MPU Virtual, and Local Bus Virtual Addresses-an Example . . . . . . 100 6.4 NULL Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.5 Endianism and USB Host Controller Access to System Memory . . . . . . . . . . . . . . . . . . 103 6.5.1 Endianism and OHCI Endpoint and Transfer Descriptors . . . . . . . . . . . . . . . . . 103 6.5.2 Endianism and OHCI Data Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7 OMAP5910 OMAP5910 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 LB Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 LB MPU Time-out Register (LB_MPU_TIMEOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 LB Hold Timer Register (LB_HOLD_TIMER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 LB Priority Register (LB_PRIORITY_REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 LB Clock Divider Register (LB_CLOCK_DIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 LB Abort Address Register (LB_ABORT_ADD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 LB Abort Data Register (LB_ ABORT_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8 LB Abort Status Register (LB_ABORT_STATUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9 LB IRQ Output Register (LB_IRQ_OUTPUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10 LB IRQ Input Register (LB_IRQ_INPUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.11 Local Bus Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.12 Local Bus Virtual Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 105 106 106 107 107 110 110 111 112 112 113 113 8 OMAP5910 OMAP5910 Local Bus MMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 OMAP5910 OMAP5910 Local Bus MMU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Local Bus MMU Programming for USB Host Controller Operation . . . . . . . . . . . . . . . . . 8.2.1 Local Bus MMU Page Size and the USB Host Controller . . . . . . . . . . . . . . . . . . 8.2.2 Local Bus MMU and Page Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.3 Local Bus MMU Page Miss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 115 127 127 127 127 8 SPRU677 SPRU677 Contents 9 USB Host Controller Reset and Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 USB Host Controller Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Initializing ULPD to Generate the 48-MHz Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 USB Host Controller Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 USB Host Controller OHCI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 USB Host Controller Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6 Local Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 129 129 130 130 130 131 10 OMAP5910 OMAP5910 USB Hardware Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 VBUS Power Switching For USB Type A Host Receptacles . . . . . . . . . . . . . . . . . . . . . . 10.2 Transient Suppression for USB Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 VBUS Monitoring for USB Function Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 USB D+ Pullup Enable for USB Function Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 Port Passthrough Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6 UART1 Connectivity when CONF_MOD_USB_HOST_HMC_MODE_R = 2, 10, 18, and 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7 MPU_BOOT Signal Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8 USB D+, D- Pulldown for USB Function Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 132 132 132 132 133 11 Overview of the OMAP5910 OMAP5910 USB Functional Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 OMAP5910 OMAP5910 Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 USB Function Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 USB Function Clocks and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 USB Function DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5 USB Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.1 Software Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.2 Hardware Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO0 Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Power Supply Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6 Software Disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 135 135 137 137 138 138 138 139 139 140 12 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 Revision Register (REV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.1 REV_NB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Endpoint Selection Register (EP_NUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1 Setup FIFO Select (Setup_Sel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.2 TX/RX FIFO Select (EP_Sel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.3 Endpoint Direction (EP_Dir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.4 Endpoint Number (EP_Num) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Data Register (DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.1 Transmit/Receive FIFO Data (DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 Control Register (CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.1 Clear Halt Endpoint (Clr_Halt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.2 Set Halt Endpoint (Set_Halt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.3 Set FIFO Enable (Set_FIFO_En) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 143 143 143 144 144 145 145 146 146 147 147 148 148 SPRU677 SPRU677 133 134 134 9 Contents 12.4.4 Clear Endpoint (Clr_EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.5 Endpoint Reset (Reset_EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 Status Register (STAT_FLG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.1 Isochronous Missed IN Token (Miss_In) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.2 Isochronous Receive Data Flush (Data_Flush) . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.3 Isochronous Receive Data Error (ISO_Err) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.4 Isochronous FIFO Empty (ISO_FIFO_Empty) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.5 Isochronous FIFO Full (ISO_FIFO_Full) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.6 Endpoint Halted Flag (EP_Halted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.7 Transaction Stall (STALL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.8 Transmit Non-Acknowledge (NAK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.9 Transaction Acknowledge (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.10 FIFO Enable (FIFO_En) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.11 Non-Isochronous FIFO Empty (Non_ISO_FIFO_Empty) . . . . . . . . . . . . . . . . . . 12.5.12 Non-Isochronous FIFO Full (Non_ISO_FIFO_Full) . . . . . . . . . . . . . . . . . . . . . . . 12.6 Receive FIFO Status Register (RXFSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6.1 Receive FIFO Byte Count (RXF_Count) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7 System Configuration Register 1 (SYSCON1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7.1 Device Configuration Locked (Cfg_lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7.2 NAK Enable (Nak_En:) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7.3 Self-Powered (Self_Pwr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7.4 Shutoff Disable (SOFF_Dis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7.5 External Pullup Enable (Pullup_En) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8 System Configuration Register 2 (SYSCON2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8.1 Remote Wakeup (Rmt_Wkp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8.2 Stall Command (Stall_Cmd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8.3 Device Cond (Dev_Cfg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8.4 Clear Cond (Clr_Cfg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.9 Device Status Register (DEVSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.9.1 Remote Wakeup Enabled (R_WK_OK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.9.2 USB Reset Signaling (USB_Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.9.3 Suspended State (SUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.9.4 Cond State (CFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.9.5 Addressed State (ADD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.9.6 Default State (DEF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.9.7 Attached State (ATT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.10 Start of Frame Register (SOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.10.1 Frame Timer Locked (FT_Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.10.2 Time Stamp OK(TS_OK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.10.3 Time Stamp Number(TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11 Interrupt Enable Register (IRQ_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.12 Interrupt Source Register (IRQ_SRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.12.1 Transmit DMA CH.n Done Interrupt Flag (TXn_Done) . . . . . . . . . . . . . . . . . . . . 12.12.2 RX DMA CH.n Transactions Count Interrupt Flag (RXn_Cnt) . . . . . . . . . . . . . . 10 149 149 150 151 151 152 152 152 153 153 153 154 154 154 155 155 155 156 156 157 157 157 158 159 159 160 160 160 161 162 162 162 163 163 163 163 164 164 165 165 166 167 168 168 SPRU677 SPRU677 Contents 12.13 12.14 12.15 12.16 12.17 12.18 12.19 12.20 12.21 12.22 SPRU677 SPRU677 12.12.3 Receive DMA CH.n EOT Interrupt Flag (RXn_EOT) . . . . . . . . . . . . . . . . . . . . . . 12.12.4 Start Of Frame Interrupt Flag (SOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.12.5 OUT Transaction Endpoint n Interrupt Flag (EPn_RX) . . . . . . . . . . . . . . . . . . . . 12.12.6 IN Transaction Endpoint n Interrupt Flag (EPn_TX) . . . . . . . . . . . . . . . . . . . . . . 12.12.7 Device State Changed Interrupt Flag (DS_Chg) . . . . . . . . . . . . . . . . . . . . . . . . . 12.12.8 Setup Transaction Interrupt Flag (Setup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.12.9 OUT Transaction Endpoint 0 Interrupt Flag (EP0_RX) . . . . . . . . . . . . . . . . . . . . 12.12.10 IRQ_SRC[0].EP0_TX: IN Transaction Endpoint 0 Interrupt Flag . . . . . . . . . . Non-Isochronous Endpoint Interrupt Status Register (EPN_STAT) . . . . . . . . . . . . . . . . 12.13.1 Receive Endpoint Interrupt Source (EPn_RX_IT_src) . . . . . . . . . . . . . . . . . . . . 12.13.2 Transmit Endpoint Interrupt Source (EPn_TX_IT_src) . . . . . . . . . . . . . . . . . . . . Non-Isochronous DMA Interrupt Status Register (DMAN_STAT) . . . . . . . . . . . . . . . . . . 12.14.1 DMA Receive Single Byte (DMAn_RX_SB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.14.2 DMA Receive Interrupt Source (DMAn_RX_IT_src) . . . . . . . . . . . . . . . . . . . . . . 12.14.3 DMA Transmit Interrupt Source (DMAn_TX_IT_src) . . . . . . . . . . . . . . . . . . . . . . Receive DMA Channels Configuration Register (RXDMA_CFG) . . . . . . . . . . . . . . . . . . 12.15.1 Receive Endpoint Number for DMA Channel 2 (RXDMA2_EP) . . . . . . . . . . . . 12.15.2 Receive Endpoint Number for DMA Channel 1 (RXDMA1_EP) . . . . . . . . . . . . 12.15.3 Receive Endpoint Number for DMA Channel 0 (RXDMA0_EP) . . . . . . . . . . . . Transmit DMA Channels Configuration Register (TXDMA_CFG) . . . . . . . . . . . . . . . . . . 12.16.1 Transmit Endpoint Number for DMA Channel 2 (TXDMA2_EP) . . . . . . . . . . . . 12.16.2 Transmit Endpoint Number for DMA Channel 1 (TXDMA1_EP) . . . . . . . . . . . . 12.16.3 Transmit Endpoint Number for DMA Channel 0 (TXDMA0_EP) . . . . . . . . . . . . DMA FIFO Data Register (DATA_DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.17.1 DMA FIFO Data(DATA_DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit DMA Control Registers (TXDMA0.TXDMA2) . . . . . . . . . . . . . . . . . . . . . . . . . . 12.18.1 Transmit DMA Ch.n End of Transfer (TXn_EOT) . . . . . . . . . . . . . . . . . . . . . . . . 12.18.2 Transmit DMA Ch.n Start (TXn_Start) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.18.3 Transmit DMA Ch.n Transfer Size Counter (TXn_TSC) . . . . . . . . . . . . . . . . . . . Receive DMA Control Registers (RXDMA.RXDMA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.19.1 Receive DMA Ch.n Transfer Stop (RXn_Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . 12.19.2 Receive DMA Ch.n Transactions Count (RXn_TC) . . . . . . . . . . . . . . . . . . . . . . . Endpoint 0 Configuration Register (EP0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.20.1 Endpoint 0 FIFO Size (EP0_Size) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.20.2 Endpoint 0 Pointer (EP0_ptr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Endpoint Configuration Registers (EP1_RX.EP15_RX) . . . . . . . . . . . . . . . . . 12.21.1 Receive Endpoint n Valid (EPn_RX_Valid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.21.2 Receive Endpoint n Double-Buffer (EPn_RX_Db) . . . . . . . . . . . . . . . . . . . . . . . . 12.21.3 Receive Endpoint n Size (EPn_RX_Size) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.21.4 Receive Isochronous Endpoint n(EPn_RX_Iso) . . . . . . . . . . . . . . . . . . . . . . . . . 12.21.5 Receive Endpoint n Pointer (EPn_RX_ptr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Endpoint Configuration Registers (EP1_TX.EP15_TX) . . . . . . . . . . . . . . . . . 12.22.1 EPn_TX[15].EPn_TX_Valid: Transmit Endpoint n Valid . . . . . . . . . . . . . . . . . . . 12.22.2 Transmit Endpoint n Double-Buffer(EPn_TX_Db) . . . . . . . . . . . . . . . . . . . . . . . . 169 169 170 170 170 170 171 171 171 172 172 173 173 174 174 175 175 176 176 177 177 178 178 179 179 180 180 181 181 182 182 182 183 183 183 184 184 185 185 186 186 187 187 187 11 Contents 12.22.3 Transmit Endpoint n Size (EPn_TX_Size) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.22.4 Transmit Isochronous Endpoint n (EPn_TX_Iso) . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.22.5 Transmit Endpoint n Pointer (EPn_TX_ptr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 13 USB Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1 Non-Isochronous, Non-Setup OUT (USB HOST -> LH) Transactions . . . . . . . . . . . . . . 13.1.1 Non-Isochronous, Non-Control OUT Endpoint Handshaking Conditions . . . . . Acknowledged Transactions (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Acknowledged Transactions (NAK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.2 Non-Isochronous, Non-Control OUT Transaction Error Conditions . . . . . . . . . STALLed Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packet Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sequence Bit Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.3 Non-Isochronous, Non-Control OUT Endpoint FIFO Error Conditions . . . . . . . 13.2 Non-Isochronous IN (LH->USB HOST) Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.1 Non-Isochronous IN Endpoint Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acknowledged Transactions (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-must Transactions (NAK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.2 Non-Isochronous IN Transaction Error Conditions . . . . . . . . . . . . . . . . . . . . . . . STALLed Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packet Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.3 Non-Isochronous IN Endpoint FIFO Error Conditions . . . . . . . . . . . . . . . . . . . . . 13.3 Isochronous OUT (USB HOST-> LH) Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.1 Isochronous OUT Endpoint Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2 Isochronous OUT Transaction Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.3 Isochronous OUT Endpoint FIFO Error Conditions . . . . . . . . . . . . . . . . . . . . . . . 13.4 Isochronous IN (LH->USB HOST) Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.1 Isochronous IN Endpoint Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2 Isochronous IN Transaction Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.3 Isochronous IN Endpoint FIFO Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 13.5 Control Transfers on Endpoint 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.1 Autodecoded Control Write Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autodecoded Control Write Transfer Handshaking . . . . . . . . . . . . . . . . . . . . . . . Autodecoded Control Write Transfer Error Conditions . . . . . . . . . . . . . . . . . . . . 13.5.2 Autodecoded Control Read Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autodecoded Control Read Transfer Handshaking . . . . . . . . . . . . . . . . . . . . . . . Autodecoded Control Read Transfer Error Conditions . . . . . . . . . . . . . . . . . . . . 13.5.3 Non-Autodecoded Control Write Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specific Local Host Required Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Autodecoded Control Write Transfer Handshaking . . . . . . . . . . . . . . . . . . . Non-Autodecoded Control Write Transfer Error Conditions . . . . . . . . . . . . . . . . 13.5.4 Non-Autodecoded Control Read Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Autodecoded Control Read Transfer Handshaking . . . . . . . . . . . . . . . . . . Non-Autodecoded Control Read Transfer Error Conditions . . . . . . . . . . . . . . . . 12 189 189 190 191 192 192 192 193 193 193 193 195 196 196 197 197 198 198 199 200 200 201 202 203 203 203 204 208 208 208 209 209 209 209 211 211 212 212 213 214 SPRU677 SPRU677 Contents 13.5.5 Autodecoded Versus Non-Autodecoded Control Requests . . . . . . . . . . . . . . . . 214 13.5.6 Note on Control Transfers Data Stage Length . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 14 Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 15 Preparing for Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 16 Interrupt Service Routine (ISR) Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.1 Important Note on USB Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2 Parsing the General USB Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3 Setup Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4 Endpoint 0 RX Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 Endpoint 0 TX Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.6 Device States Changed Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.7 Device States Attached/Unattached Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.8 USB Reset Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.9 Suspend/Resume Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.10 Parsing the Non-Isochronous Endpoint-Specific Interrupt . . . . . . . . . . . . . . . . . . . . . . . . 16.11 Non-Isochronous, Non-Control OUT Endpoint Receive Interrupt Handler . . . . . . . . . . . 16.12 Non-Isochronous, Non-Control IN Endpoint Transmit Interrupt Handler . . . . . . . . . . . . 16.13 SOF Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.14 Summary of USB-Related Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 226 227 227 232 232 237 240 241 241 241 246 246 246 254 17 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.1 Receive DMA Channels Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.2 Non-Isochronous OUT (USB HOST -> LH) DMA Transactions . . . . . . . . . . . . . . . . . . . 17.3 Isochronous OUT (USB HOST -> LH) DMA Transactions . . . . . . . . . . . . . . . . . . . . . . . 17.4 Transmit DMA Channels Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5 Non-Isochronous IN (LH -> USB HOST) DMA Transactions . . . . . . . . . . . . . . . . . . . . . 17.6 Isochronous IN (USB HOST -> LH) DMA Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . 17.7 Important Note on DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.8 Note on DMA Channel Deconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 255 255 261 262 262 266 266 267 18 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 19 Frame Adjustment Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 20 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 21 Synchronization and Counter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 22 FAC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 23 FAC Clocks and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 24 Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 SPRU677 SPRU677 13 Figures Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 14 OMAP5910 OMAP5910 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 USB Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical USB Host Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical USB Function Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 USB Host Controller Connection-With and Without the OMAP5910 OMAP5910 Transceiverless Link Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 USB Function Connection-With and Without the OMAP5910 OMAP5910 Transceiverless Link Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 0 . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 1 . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 2 . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 3 . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 4 . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 5 . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 6 . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 7 . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 9 . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 10 . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 11 . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 12 . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 13 . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 14 . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 15 . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 16 . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 17 . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 18 . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 19 . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 20 . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 21 . . . . . . . . . . . . . . . OMAP5910 OMAP5910 Cond for HMC_MODEs 22, 26-31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 23 (Transceiverless Connection Uses TXD+, TXD- Signaling) . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 24 (Transceiverless Connection Uses TXD+, TXD- Signaling) . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 25 (Transceiverless Connection Uses TXD+, TXD- Signaling) . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 USB Host Controller Data Path to System Memory . . . . . . . . . . . . . . . . . . . . . . 12 13 57 58 61 62 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 93 SPRU677 SPRU677 Figures 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 Relationships Between Processor Virtual Address, Processor Physical Address, and Local Bus Virtual Address With Local Bus MMU Disabled . . . . . . . . . . . . . . . 94 Relationships Between Processor Virtual Address, Processor Physical Address, and Local Bus Virtual Address With Local Bus MMU Enabled . . . . . . . . . . . . . . . 95 USB Function Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Non-Isochronous, Non-Control OUT Endpoint Handshaking Conditions . . . . . . . . . . . . . . 190 Non-Isochronous IN Transaction Phases and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Isochronous OUT Transaction Phases and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Isochronous IN Transaction Phases and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Stages and Transaction Phases of Autodecoded Control Transfers . . . . . . . . . . . . . . . . . . 205 Stages and Transaction Phases of Non-Autodecoded Control Transfers . . . . . . . . . . . . . . 206 Example of RAM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Device Configuration Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Endpoint Configuration Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Prepare for USB RX Transfer Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Prepare for TX Transfer on Endpoint n Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 General USB Interrupt ISR Source Parsing Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Setup Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Parse Command Routine (Setup Stage Control Transfer Request) . . . . . . . . . . . . . . . . . . 231 Endpoint 0 RX Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Prepare for Control Write Status Stage Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Endpoint 0 TX Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Prepare for Control Read Status Stage Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 USB Function Device State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Typical Operation for USB Device State Changed Interrupt Handler . . . . . . . . . . . . . . . . . 239 Attached/Unattached Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 USB Reset Handler Flowchart I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 USB Reset Handler Flowchart II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Typical Operation for USB Suspend/Resume General USB Interrupt Handler . . . . . . . . . 244 Non-Isochronous Endpoint-Specific (Except ER 0) ISR Flowchart . . . . . . . . . . . . . . . . . . . 245 Non-Isochronous Non-Control Endpoint Receive Interrupt Handler . . . . . . . . . . . . . . . . . . 247 Read Non-Isochronous RX FIFO Data Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Non-Isochronous Non-control Endpoint Transmit Interrupt Handler . . . . . . . . . . . . . . . . . . 249 Write Non-Isochronous TX FIFO Data Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 SOF Interrupt Handler Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Read Isochronous RX FIFO Data Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Write Isochronous TX FIFO Data Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Non-Isochronous RX DMA Transaction Example (RX_TC = 2) . . . . . . . . . . . . . . . . . . . . . . 257 Non-Isochronous RX DMA Start Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Non-Isochronous RX DMA EOT Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Non-Isochronous RX DMA Transaction Count Interrupt Handler . . . . . . . . . . . . . . . . . . . . . 260 Isochronous RX DMA Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Isochronous RX DMA Start Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 File Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 SPRU677 SPRU677 15 Figures 75 76 77 78 79 80 81 82 16 Non-Isochronous TX DMA DMA Start Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Isochronous TX DMA Done Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous TX DMA Start Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Signal Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FAC Top-Level Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FAC-Module Counters and Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Circuit for Frame-Synchronization and Frame-Start Signals . . . . . . . . . . Synchronization Circuit Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 265 267 270 272 274 275 275 SPRU677 SPRU677 Tables Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 USB Host Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 OHCI Revision Number Register (HcRevision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 HC Operating Mode Register (HcControl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 HC Command and Status Register (HcCommandStatus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 HC Interrupt Status Register (HcInterruptStatus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 HC Interrupt Enable Register (HcInterruptEnable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 HC Interrupt Disable Register (HcInterruptDisable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 HC HCAA Address Register (HcHCCA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 HC Current Periodic Register (HcPeriodCurrentED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 HC Head Control Register (HcControlHeadED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 HC Current Control Register (HcControlCurrentED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 HC Head Bulk Register (HcBulkHeadED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 HC Current Bulk Register (HcBulkCurrentED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 HC Head Done Register (HcDoneHead) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 HC Frame Interval Register (HcFmInterval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 HC Frame Remaining Register (HcFmRemaining) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 HC Frame Number Register (HcFmNumber) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 HC Periodic Start Register (HcPeriodicStart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 HC Low-Speed Threshold Register (HcLSThreshold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 HC Root Hub A Register (HcRhDescriptorA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 HC Root Hub B Register (HcRhDescriptorB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 HC Root Hub Status Register (HcRhStatus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 HC Port 1 Status and Control Register (HcRhPortStatus1) . . . . . . . . . . . . . . . . . . . . . . . . . 39 HC Port 2 Status and Control Register (HcRhPortStatus2) . . . . . . . . . . . . . . . . . . . . . . . . . 43 HC Port 3 Status and Control Register (HcRhPortStatus3) . . . . . . . . . . . . . . . . . . . . . . . . . 47 Host UE Address Register (HostUEAddr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Host UE Status Register (HostUEStatus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Host Time-out Control Register (HostTimeoutCtrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Host Revision Register (HostRevision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 USB Signal Multiplexing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 MPU MMU Programming for Address Conversion Example . . . . . . . . . . . . . . . . . . . . . . . . 100 MPU Memory Allocations for Address Conversion Example . . . . . . . . . . . . . . . . . . . . . . . . 100 Physical Addresses for Address Conversion Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Local Bus MMU Programming for Address Conversion Example . . . . . . . . . . . . . . . . . . . . 101 Local Bus Virtual Addresses for Address Conversion Example . . . . . . . . . . . . . . . . . . . . . . 101 Some Data Structure Initializations for Address Conversion Example . . . . . . . . . . . . . . . . 102 SPRU677 SPRU677 17 Tables 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 18 Little-Endian Data Alignment Within 32-Bit Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LB MPU Time-out Register (LB_MPU_TIMEOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LB Hold Timer Register (LB_HOLD_TIMER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LB Priority Register (LB_PRIORITY_REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LB Clock Divider Register (LB_CLOCK_DIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LB Abort Address Register (LB_ABORT_ADD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LB Abort Data Register (LB_ ABORT_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LB Abort Status Register (LB_ABORT_STATUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LB IRQ Output Register (LB_IRQ_OUTPUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LB IRQ Input Register (LB_IRQ_INPUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus MMU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LB MMU Walking Status Register (LB_MMU_WALKING_ST_REG) . . . . . . . . . . . . . . . . . LB MMU Control Register (LB_MMU_CNTL_REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LB MMU Fault Address High Register (LB_MMU_FAULT_AD_H_REG) . . . . . . . . . . . . . . LB MMU Fault Address Low Register (LB_MMU_FAULT_AD_L_REG) . . . . . . . . . . . . . . . LB MMU Fault Status Register (LB_MMU_FAULT_ST_REG) . . . . . . . . . . . . . . . . . . . . . . . LB MMU Interrupt Acknowledge Register (LB_MMU_IT_ACK_REG) . . . . . . . . . . . . . . . . . LB MMU TTB Address High Register (LB_MMU_TTB_H_REG) . . . . . . . . . . . . . . . . . . . . . LB MMU TTB Address Low Register (LB_MMU_TTB_L_REG) . . . . . . . . . . . . . . . . . . . . . . LB MMU Lock Counter Register (LB_MMU_LOCK_REG) . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus MMU TLB Read/Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus MMU CAM High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus MMU CAM Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus MMU RAM High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus MMU RAM Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus MMU Global Flush Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus MMU Entry Flush Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus MMU CAM Read High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus MMU RAM Read High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus MMU RAM Read Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CONF_MOD_USB_HOST_HMC_MODE_R=7 Internal Connectivity . . . . . . . . . . . . . . . . . CONF_MOD_USB_HOST_HMC_MODE_R = 2, 10, 18, and 24 UART Signal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Function Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision Register (REV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endpoint Selection Register (EP_NUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Register (DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Register (CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register (STAT_FLG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive FIFO Status Register (RXSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Configuration Register 1(SYSCON1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYSCON2 ­ System Configuration Register 2 (SYSCON2) . . . . . . . . . . . . . . . . . . . . . . . . . Device Status Register (DEVSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 105 106 106 107 108 110 110 111 112 112 115 116 116 117 117 118 118 119 119 119 120 121 121 123 123 124 124 124 126 126 133 134 141 143 143 146 147 150 155 156 159 161 SPRU677 SPRU677 Tables 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Start of Frame Register (SOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Enable Register (IRQ_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Source Register (IRQ_SRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Isochronous Endpoint Interrupt Status Register (EPN_STAT) . . . . . . . . . . . . . . . . . . . Non-Isochronous DMA Interrupt Status Register (DMAN_STAT) . . . . . . . . . . . . . . . . . . . . Receive DMA Channels Configuration Register (RXDMA_CFG) . . . . . . . . . . . . . . . . . . . . Transmit DMA Channels Configuration Register (TXDMA_CFG) . . . . . . . . . . . . . . . . . . . . DMA FIFO Data Register (DATA_DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit DMA Control Registers (TXDMA.TXDMA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive DMA Control Registers (RXDMA0.RXDMA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endpoint 0 Configuration Register (EP0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Endpoint n Configuration Registers (EP1_RX.EP15_RX) . . . . . . . . . . . . . . . . . Endpoint n Size Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Endpoint Configuration Registers (EP1_TX.EP15_TX) . . . . . . . . . . . . . . . . . . . . Autodecoded Versus Non-Autodecoded Control Requests . . . . . . . . . . . . . . . . . . . . . . . . USB Interrupt Type by Endpoint Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame-Adjustment-Reference-Count Register (FARC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame-Start-Count Register (FSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FAC-Control-and-Configuration Register (CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FAC-Status Register (STATUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPRU677 SPRU677 164 166 167 171 173 175 177 179 180 182 183 184 185 187 214 254 277 277 278 279 279 19 20 SPRU677 SPRU677 Universal Serial Bus This chapter describes the universal serial bus (USB) host of the OMAP5910 OMAP5910 multimedia processor. 1 USB Host Controller The OMAP5910 OMAP5910 USB host controller (HC) is a three-port controller that communicates with USB devices at the USB low-speed (1.5M bit/s maximum) and full-speed (12M bit/s maximum) data rates. It is compatible with the Universal Serial Bus Specification Revision 1.1 and the Open HCI-Open Host Controller Interface Specification for USB, Release 1.0a, available through the Compaq Computer Corporation web site, and hereafter called the OHCI Specification for USB. It is assumed that users of the OMAP5910 OMAP5910 USB host controller are already familiar with the USB Specification and OHCI Specification for USB. The OMAP5910 OMAP5910 USB host controller implements the register set and makes use of the memory data structures defined in the OHCI Specification for USB. These registers and data structures are the mechanism by which a USB host controller driver software package can control the OMAP5910 OMAP5910 USB host controller. The OHCI Specification for USB also defines how the USB host controller implementation must interact with those registers and data structures in system memory. To reduce processor software and interrupt overhead, the USB host controller generates USB traffic based on data structures and data buffers stored in system memory. The OMAP5910 OMAP5910 USB host controller accesses these data structures without direct intervention by the processor using the OMAP5910 OMAP5910 local bus. These data structures and data buffers can be located in internal or external system RAM. The local bus MMU allows the USB host controller to access the full address range of internal and external memories. The OMAP5910 OMAP5910 USB host controller is connected to the OMAP5910 OMAP5910 MPU public peripheral bus to enable MPU access to registers. The USB host controller gains access to the data structures in the OMAP5910 OMAP5910 system memory via the internal OMAP5910 OMAP5910 local bus (LB) interface. The USB host controller provides an interrupt to the MPU level 2 interrupt handler to signal certain hardware events to the host controller driver software. Flexible multiplexing of signals from the OMAP5910 OMAP5910 USB host controller, the OMAP5910 OMAP5910 USB function controller, and other OMAP5910 OMAP5910 peripherals allows SPRU677 SPRU677 Universal Serial Bus 21 USB Host Controller a wide variety of system-level USB functions. The OMAP5910 OMAP5910 top-level pin multiplexing controls each pin individually to select one of several possible internal pin signal interconnections. When these shared pins are programmed for use as USB signals, the OMAP5910 OMAP5910 USB signal multiplexing selects how the signals associated with the three OMAP5910 OMAP5910 USB host ports and the OMAP5910 OMAP5910 USB function controller can be brought out to OMAP5910 OMAP5910 pins. Figure 1 shows the OMAP5910 OMAP5910 device with the USB host controller highlighted. Figure 2 shows the OMAP5910 OMAP5910 USB host controller. See Section 1.11 for the OMAP5910 OMAP5910 USB Functional Module. Figure 1. OMAP5910 OMAP5910 Block Diagram DSP MMU 32 TMS320C55x DSP (Instruction cache, SARAM DARAM, DMA, H/W accelerators) 16 32 SDRAM memories 16 16 32 E M I F F MPU Bus 32 32 I M I F SRAM 1.5M bits JTAG/ emulation I/F MPU/DSP shared peripherals Mailbox GPIO I/F TIPB switch 32 32 Memory interface traffic controller (TC) 32 MPU core (TI925T TI925T) (instruction cache, data cache, MMU) MPU public peripherals bus MPU privatePeripherals bus 16 MPU private peripherals Timers (3) Clock and reset management LCD I/F ETM9 McBSP2 32 32 Watchdog timer Level 1/2 interrupt handlers OSC OSC UART1 UART2 UART3 IrDA MPU public peripherals MPU peripheral bridge System DMA controller 32 McBSP3 MCSI1 MCSI2 32 32 McBSP1 16 MPU Interface E M I F S DSP public peripherals DSP public (shared) pheripheral bus 16 Flash and SRAM memories DSP Private peripherals Timers (3) Watchdog timer Level 1/2 interrupt handlers DSP private peripheral bus OMAP5910 OMAP5910 USB Host I/F USB Function I/F I2C µWire Camera I/F MPUIO 32-kHz timer PWT PWL Keyboard I/F MMC/SD LPG x2 Frame adjstument counter HDQ / 1-WIRE RTC Configuration registers Device identification External clock 12 MHz 32 kHz Clock Reset request or 13 MHz 22 Universal Serial Bus SPRU677 SPRU677 USB Host Controller OMAP5910 OMAP5910 USB Host Controller Memory controller Local Bus interface LB's MMU USB connector USB connector Local bus controller USB connector MPU's MMU USB transceiver, ESD protection MPU USB signal multiplexing MPU Public peripheral bus interface ESD protection USB transceiver, ESD protection Peripheral UART 1 USB transciever INTH2 Peripheral USB function controller Top-level pin multiplexing MPU public peripheral bus Peripheral OHCI controller Figure 2. USB Host Controller Internal memory Signals to/from other peripherals GPIO USB power switching OMAP5910 OMAP5910 External memory SPRU677 SPRU677 Universal Serial Bus 23 USB Open Host Controller Interface Functionality 2 2.1 USB Open Host Controller Interface Functionality OHCI Controller Overview The Open HCI-Open Host Controller Interface Specification for USB, Release 1.0a defines a set of registers and data structures stored in system memory that define how a USB host controller interfaces to system software. This specification, in conjunction with the Universal Serial Bus Specification Version 1.1, defines most of the USB functionality that the OMAP5910 OMAP5910 USB host controller provides. The OHCI Specification for USB focuses on two main aspects of the hardware implementation of a USB host controller: its register set and the memory data structures that define the activity to appear on the USB bus. Issues such as interrupt generation, USB host controller state, USB frame management, and the methods that the hardware must use to process the lists of data structures in system memory are also described. This document does not duplicate the information presented in the OHCI Specification for USB or the USB Specification. OMAP5910 OMAP5910 USB host controller users should refer to the USB Specification and the OHCI Specification for USB for detailed discussions of USB requirements and OHCI controller operation. 2.2 OMAP5910 OMAP5910 USB Host Controller/OHCI Specification Differences The OMAP5910 OMAP5910 USB host controller does not implement every aspect of the functionality defined in the OHCI Specification for USB. The differences focus on power switching, overcurrent reporting, and the OHCI ownership change interrupt. Other restrictions are imposed by OMAP5910 OMAP5910 system memory addressing mechanisms and the effects of OMAP5910 OMAP5910 pin multiplexing options. 2.2.1 Power Switching Output Pins Not Supported The OMAP5910 OMAP5910 device does not provide pins that can be controlled directly by the USB host controller OHCI port power control features. The OHCI RhPortStatus(n) register port power control bits can be programmed by the USB host controller driver software, but this does not have any direct effect on any VBUS switching implemented on the board. Users can use other GPIO pins or implementation-specific control mechanisms to control VBUS switching. 24 Universal Serial Bus SPRU677 SPRU677 USB Open Host Controller Interface Functionality 2.2.2 Overcurrent Protection Input Pins Not Supported The OMAP5910 OMAP5910 device does not provide pins that allow the USB host controller OHCI RhPortStatus(n) overcurrent protection status bits to be directly controlled by external hardware. Users can use GPIO pins or other implementation-specific control mechanisms to report port overcurrent information to the USB host controller driver. 2.2.3 HMC_MODE and Top-Level Pin Multiplexing and OHCI Registers The USB signal multiplexing modes provide selections to allow 0, 1, 2, or 3 USB host controller ports to be brought out to OMAP5910 OMAP5910 pins. The OHCI RhDescriptorA register always reports three available USB host ports, regardless of the CONF_MOD_USB_HOST_HMC_MODE_R field of the MOD_CONF_CTRL_0 register or top-level pin multiplexing settings. When the CONF_MOD_USB_HOST_HMC_MODE_R field setting of the MOD_CONF_CTRL_0 register disables a USB host controller port, the USB host controller sees that port as unattached. When OMAP5910 OMAP5910 top-level pin multiplexing configures a pin for functionality other than the USB, the USB host controller is disconnected from that pin and that pin does not affect the USB host controller. 2.2.4 No Ownership Change Interrupt The OMAP5910 OMAP5910 USB host controller does not implement the OHCI ownership change interrupt. 2.2.5 Valid Address Ranges for Pointers to Data Structures The mechanism that allows the OMAP5910 OMAP5910 USB host controller to access the USB endpoint descriptor (ED), transfer descriptor (TD) , and HCCA data structures in system memory places certain requirements on the registers that point to data structures in system memory and on the pointers within those data structures. Details can be found in Section 6, USB Host Controller Access to System Memory. 2.3 OMAP5910 OMAP5910 Implementation of OHCI Specification for USB 2.3.1 Isochronous TD OFFSETX/PSWX Values The OMAP5910 OMAP5910 USB host controller implements the OHCI Specification for USB optional feature of checking isochronous OFFSETX/PSWX values. If SPRU677 SPRU677 Universal Serial Bus 25 USB Open Host Controller Interface Functionality either OFFSETX or OFFSET(X+1) does not have a condition code of Not Accessed, or if the OFFSET(X+1) value is not greater than or equal to OFFSETX, then an unrecoverable error is reported. Unrecoverable errors issued for these reasons do not cause an update of the HostUEAddr, HostUEStatus, or HostTimeoutCtrl registers. 2.3.2 OMAP5910 OMAP5910 USB Host Controller Endpoint Descriptor (ED) List Head Pointers The OHCI Specification for USB provides a specific sequence of operations for the host controller driver to perform when setting up the host controller. Failure to follow that sequence can result in a malfunction. As a specific example, the HcControlHeadED and HCBulkHeadED pointer registers and the 32 HccaInterruptTable pointers must all point to valid local bus addresses of valid endpoint descriptors. The OMAP5910 OMAP5910 USB host controller does not check HcControlHeadED registers, HcBulkHeadED registers, or the values in the 32 HccaInterruptTable pointers before using them to access EDs. If any of these pointers are NULL when the corresponding list enable bit is set, the OMAP5910 OMAP5910 USB host controller attempts to access using the local bus virtual address of 0, which causes an unrecoverable error. Registers HostUEAddr, HostUEStatus, and HostTimeoutCtrl are updated in this case. 26 Universal Serial Bus SPRU677 SPRU677 USB Host Controller Registers 3 USB Host Controller Registers Most of the OMAP5910 OMAP5910 host controller (HC) registers are the OHCI operational registers, which are defined by the OHCI Specification for USB. Four additional registers not specified by the OHCI Specification for USB provide additional information about the USB host controller state. USB host controller registers can be accessed in user and supervisor modes. Note: The USB host controller registers must be accessed using 32-bit data operations. Use of smaller data access sizes may result in unexpected operation of the USB host controller. The USB host controller registers and the USB host controller data structures are organized for little-endian operation mode because the MPU processor on the OMAP5910 OMAP5910 device must use little-endian mode. The OMAP5910 OMAP5910 USB host controller registers are listed in Table 1. Table 2 through Table 29 describe specific register bits. Table 1. USB Host Controller Registers R/W Size Address R 32 FFFB:A000h HC operating mode R/W 32 FFFB:A004h HcCommandStatus HC command and status R/W 32 FFFB:A008h HcInterruptStatus HC interrupt status R/W 32 FFFB:A00Ch HcInterruptEnable HC interrupt enable R/W 32 FFFB:A010h HcInterruptDisable HC interrupt disable R 32 FFFB:A014h HcHCCA Local bus virtual address of the HCCA R/W 32 FFFB:A018h HcPeriodCurrentED Local bus virtual address of the current periodic endpoint descriptor R/W 32 FFFB:A01Ch HcControlHeadED Local bus virtual address of the head of the control endpoint descriptor list R/W 32 FFFB:A020h HcControlCurrentED Local bus virtual address of the current control endpoint descriptor R/W 32 FFFB:A024h Name Description HcRevision OHCI revision number HcControl Access to these registers must be by 32-bit reads or 32-bit writes. Use of other access sizes may result in undefined operation. Restrictions apply to the local bus virtual addresses used in these registers. See Section 6.1, Local Bus Addressing. § This register provides control and status for the OMAP5910 OMAP5910 pins associated with the USB transceiver for some HMC_MODE values. ¶ This register provides control and status for the OMAP5910 OMAP5910 pins associated with USB port 1 for some HMC_MODE values. # This register provides control and status for the OMAP5910 OMAP5910 pins associated with USB port 2 for some HMC_MODE values. SPRU677 SPRU677 Universal Serial Bus 27 USB Host Controller Registers Table 1. USB Host Controller Registers (Continued) Name Description R/W Size Address HcBulkHeadED Local bus virtual address of the head of the bulk endpoint descriptor list R/W 32 FFFB:A028h HcBulkCurrentED Local bus virtual of the current bulk endpoint descriptor R/W 32 FFFB:A02Ch HcDoneHead Local bus virtual address of the head of the list of retired transfer descriptors R 32 FFFB:A030h HcFmInterval HC frame interval R/W 32 FFFB:A034h HcFmRemaining HC frame remaining R 32 FFFB:A038h HcFmNumber HC frame number R 32 FFFB:A03Ch HcPeriodicStart HC periodic start R/W 32 FFFB:A040h HcLSThreshold HC low speed threshold R/W 32 FFFB:A044h HcRhDescriptorA HC root hub A R, R/W 32 FFFB:A048h HcRhDescriptorB HC root hub B R/W 32 FFFB:A04Ch HcRhStatus HC root hub status R, R/W 32 FFFB:A050h HcRhPortStatus1 HC port 1 control and status§ R, R/W 32 FFFB:A054h HcRhPortStatus2 HC port 2 control and status¶ R, R/W 32 FFFB:A058h HcRhPortStatus3 HC port 3 control and status# R, R/W 32 FFFBA05Ch Reserved Reserved HostUEAddr Host UE address R 32 FFFB:A0E0h HostUEStatus Host UE status R 32 FFFB:A0E4h HostTimeoutCtrl Host timeout control R/W 32 FFFB:A0E8h HostRevision Host revision R 32 FFFB:A0ECh Reserved Reserved None None FFFB:A060h to FFFB:A0DFh FFFB:A0F0h to FFFB:AFFFh Access to these registers must be by 32-bit reads or 32-bit writes. Use of other access sizes may result in undefined operation. Restrictions apply to the local bus virtual addresses used in these registers. See Section 6.1, Local Bus Addressing. § This register provides control and status for the OMAP5910 OMAP5910 pins associated with the USB transceiver for some HMC_MODE values. ¶ This register provides control and status for the OMAP5910 OMAP5910 pins associated with USB port 1 for some HMC_MODE values. # This register provides control and status for the OMAP5910 OMAP5910 pins associated with USB port 2 for some HMC_MODE values. 28 Universal Serial Bus SPRU677 SPRU677 USB Host Controller Registers The other revision number register reports the revision number of the OHCI Specification for USB upon which the USB host controller is based. Table 2. OHCI Revision Number Register (HcRevision) Bits Field Description Type 31-8 Reserved Reserved 7-0 REV OHCI Specification revision-the OHCI revision number upon which the USB host controller is based. Write has no effect. Reset Value 0x00 0000 R 0x10 The HC operating mode register controls the operating mode of the USB host controller. Table 3. Bits 31-11 HC Operating Mode Register (HcControl) Field Value Type Description Reset Value Reserved Reserved 10 RWE Remote wake-up enable. This bit has no effect in OMAP5910 OMAP5910. The OMAP5910 OMAP5910 USB host controller does not provide a processor wake-up mechanism. R/W 0 9 RWC Remote wake up connected. This bit has no effect in OMAP5910 OMAP5910. The OMAP5910 OMAP5910 USB host controller does not provide a processor wake-up mechanism. R/W 0 8 IR Interrupt routing. The OMAP5910 OMAP5910 USB host controller does not provide an SMI interrupt. This bit must be 0 to allow the USB host controller interrupt to propagate to the MPU level 2 interrupt controller. R/W 0 SPRU677 SPRU677 Universal Serial Bus 29 USB Host Controller Registers Table 3. HC Operating Mode Register (HcControl) (Continued) Bits Field 7-6 HCFS Description Type Reset Value Host controller functional state: Value R/W 00 R/W 0 R/W 0 00 USBReset 01 USBResume 10 USBOperational 11 USBSuspend A transition to USBOperational causes SOF generation to begin in 1 ms. The USB host controller may automatically transition from USBSuspend to USBResume if a downstream resume is received. The USB host controller enters USBSuspend after a software reset. The USB host controller enters USBReset after a hardware reset. The USBReset state resets the root hub and causes downstream signaling of USBReset. 5 BLE Bulk list enable: 0 1 4 Bulk ED list is not processed in the next 1-ms frame. The host controller driver can modify the list. If the driver removes the ED pointed to by the HcBulkCurrentED from the ED list, it must update HcBulk-CurrentED to point to an ED still on the list before it reenables the bulk list. Enables processing of bulk ED List. HcBulkHeadED must be 0 or point to a valid ED before setting this bit. HcBulkCurrentED must point to a valid ED or be 0 before setting this bit. CLE Control list enable: 0 1 30 The host control ED list is not processed in the next 1-ms frame. Host controller driver may modify the control ED list. If the driver removes the ED pointed to by the HcControlCurrentED from the ED list, it must updateHcControlCurrentED to point to an ED still on the list before it reenables the control list. Enables processing of the control ED list. HcControlHeadED must be 0 or point to a valid ED before setting this bit. HcControlCurrentED must be 0 or point to a valid ED before setting this bit Universal Serial Bus SPRU677 SPRU677 USB Host Controller Registers Table 3. Bits 3 HC Operating Mode Register (HcControl) (Continued) Field IE Description Type Reset Value Isochronous enable Value R/W 0 R/W 0 R/W 00 0 Enables processing of isochronous EDs. 1 Isochronous EDs are not processed. The USB host controller checks this bit every time it finds an isochronous ED in the periodic list. When this bit is written to 1, processing of isochronous EDs might not occur in the current frame but is enabled in the next frame. 2 PLE Periodic list enable 0 1 1-0 The periodic ED lists are not processed. When written to 0, periodic list processing is disabled beginning with the next frame. Enables processing of the periodic ED lists. When written to 1, periodic list processing begins in the next frame. CBSR Control/bulk service ratio Specifies the ratio between control and bulk EDs processed in a frame. 00 01 Two control EDs per bulk ED 10 Three control EDs per bulk ED 11 SPRU677 SPRU677 One control ED per bulk ED Four control EDs per bulk ED Universal Serial Bus 31 USB Host Controller Registers The HC command and status register shows the current state of the host controller and accepts commands from the host controller driver. Table 4. Bits HC Command and Status Register (HcCommandStatus) Field Description 31-18 Reserved SOC Scheduling overrun count Reset Value R 00 R/W 0 R/W 0 R/W 0 R/W 0 Reserved 17-16 Type Counts the number of times a scheduling overrun occurs. This count is incremented even if the host controller driver has not acknowledged any previous pending scheduling overrun interrupt. 15 -4 3 Reserved Reserved OCR Ownership change request This bit is set by the host controller driver to gain ownership of the host controller. OMAP5910 OMAP5910 does not support SMI interrupts, so no ownership change interrupt occurs. 2 BLF Bulk list filled The host controller driver must set this bit if it modifies the bulk list to include new TDs. If HcBulkCurrentED is 0, the USB host controller does not begin processing bulk list EDs unless this bit is set. When the USB host controller sees this bit set and begins processing the bulk list, it clears this bit. 1 CLF Control list filled The host controller driver must set this bit if it modifies the control list to include new TDs. If HcControlHeadED is 0, the USB host controller does not begin processing control list EDs unless this bit is set. When the USB host controller sees this bit set and begins processing the control list, it clears this bit. 0 HCR Host controller reset Write of 0 has no effect. 1: This bit initiates a software reset of the USB host controller. This transitions the USB host controller to the USBSuspend state. This resets most USB host controller OHCI registers. OHCI register accesses must not be attempted until a read of this register returns a 0. A write of 1 to this bit does not reset the root hub, and does not signal USB reset to downstream USB functions. 32 Universal Serial Bus SPRU677 SPRU677 USB Host Controller Registers The HC interrupt status register reports the status of the USB host controller internal interrupt sources. Table 5. Bits HC Interrupt Status Register (HcInterruptStatus) Field 31 Reserved OC R 0 R/W 0 R/W 0 R/W 0 R/W Ownership change Reset Value 0 Reserved 30 Type Description The OMAP5910 OMAP5910 USB host controller does not implement ownership change interrupts. 29 -7 6 Reserved Reserved RHSC Root hub status change When 1 indicates a root hub status change has occurred. Write of 0 has no effect. Write of 1 clears this bit. 5 FNO Frame number overflow When 1 indicates a frame number overflow has occurred. Write of 0 has no effect. Write of 1 clears this bit. 4 UE Unrecoverable error When 1 indicates that an unrecoverable error has occurred on the local bus or that an isochronous TD PSW field condition code was not set to Not Accessed when the USB host controller attempted to perform a transfer using that PSW/offset pair. Write of 0 has no effect. Write of 1 clears this bit. 3 RD Resume detected When 1 indicates that a downstream device has issued a resume request. Write of 0 has no effect. Write of 1 clears this bit. SPRU677 SPRU677 Universal Serial Bus 33 USB Host Controller Registers Table 5. Bits 2 HC Interrupt Status Register (HcInterruptStatus) (Continued) Field Description Type Reset Value SF Start of frame R/W 0 R/W 0 R/W 0 When 1 indicates that a SOF has been issued. Write of 0 has no effect. Write of 1 clears this bit. 1 WDH Write done head When 1 indicates that the USB host controller has updated the HcDoneHead register. Write of 0 has no effect. Write of 1 clears this bit. The host controller driver must read the value from HcDoneHead before writing 1 to this bit. 0 SO Scheduling overrun When 1 indicates that a scheduling overrun has occurred. Write of 0 has no effect. Write of 1 clears this bit. The HC interrupt enable register enables various OHCI interrupt sources to generate interrupts to the OMAP5910 OMAP5910 level 2 interrupt handler. Table 6. HC Interrupt Enable Register (HcInterruptEnable) Bits Field Description Type Reset Value 31 MIE Master interrupt enable R/W 0 R 0 When 1, allows other enabled OHCI interrupt sources to propagate to the OMAP5910 OMAP5910 level 2 interrupt controller. When 0, OHCI interrupt sources are ignored and no USB host controller interrupts are propagated to the OMAP5910 OMAP5910 level 2 interrupt controller. A write of 0 has no effect on this bit. A write of 1 sets this bit. 30 OC Ownership change This bit has no effect on OMAP5910 OMAP5910. 29-7 34 Reserved Reserved Universal Serial Bus SPRU677 SPRU677 USB Host Controller Registers Table 6. HC Interrupt Enable Register (HcInterruptEnable) (Continued) Bits Field Description Type Reset Value 6 RHSC Root hub status change R/W 0 R/W: 0 R/W 0 R/W 0 When 1 and MIE is 1, allows root hub status change interrupts to propagate to the OMAP5910 OMAP5910 level 2 interrupt controller. When 0, or when MIE is 0, root hub status change interrupts do not propagate. A write of 0 has no effect on this bit. A write of 1 sets this bit. 5 FNO Frame number overflow When 1 and MIE is 1, allows frame number overflow interrupts to propagate to the OMAP5910 OMAP5910 level 2 interrupt controller. When 0, or when MIE is 0, frame number overflow interrupts do not propagate. A write of 0 has no effect on this bit. A write of 1 sets this bit. 4 UE Unrecoverable error When 1 and MIE is 1, allows unrecoverable error interrupts to propagate to the OMAP5910 OMAP5910 level 2 interrupt controller. When 0, or when MIE is 0, unrecoverable error interrupts do not propagate. A write of 0 has no effect on this bit. A write of 1 sets this bit. 3 RD Resume detected When 1 and MIE is 1, allows resume detected interrupts to propagate to the OMAP5910 OMAP5910 level 2 interrupt controller. When 0, or when MIE is 0, resume detected interrupts do not propagate. A write of 0 has no effect on this bit. A write of 1 sets this bit. SPRU677 SPRU677 Universal Serial Bus 35 USB Host Controller Registers Table 6. Bits 2 HC Interrupt Enable Register (HcInterruptEnable) (Continued) Field Description Type Reset Value SF Start of frame R/W 0 R/W 0 R/W 0 When 1 and MIE is 1, allows start of frame interrupts to propagate to the OMAP5910 OMAP5910 level 2 interrupt controller. When 0, or when MIE is 0, start of frame interrupts do not propagate. A write of 0 has no effect on this bit. A write of 1 sets this bit. 1 WDH Write done head When 1 and MIE is 1, allows write done head interrupts to propagate to the OMAP5910 OMAP5910 level 2 interrupt controller. When 0, or when MIE is 0, write done head interrupts do not propagate. A write of 0 has no effect on this bit. A write of 1 sets this bit. 0 SO Scheduling overrun When 1 and MIE is 1, allows scheduling overrun interrupts to propagate to the OMAP5910 OMAP5910 level 2 interrupt controller. When 0, or when MIE is 0, scheduling overrun interrupts do not propagate. A write of 0 has no effect on this bit. A write of 1 sets this bit. 36 Universal Serial Bus SPRU677 SPRU677 USB Host Controller Registers The HC interrupt disable register is used to clear bits in the HcInterruptEnable register. Table 7. HC Interrupt Disable Register (HcInterruptDisable) Bits Field Description Type Reset Value 31 MIE Master interrupt enable R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Read always returns 0. Write of 0 has no effect. Write of 1 clears the HcInterruptEnable MIE bit. 30 OC Ownership change This bit has no effect on OMAP5910 OMAP5910. 29-7 6 Reserved Reserved RHSC Root hub status change Read always returns 0. Write of 0 has no effect. Write of 1 clears the HcInterruptEnable RHSC bit. 5 FNO Frame number overflow Read always returns 0. Write of 0 has no effect. Write of 1 clears the HcInterruptEnable FNO bit. 4 UE Unrecoverable error Read always returns 0. Write of 0 has no effect. Write of 1 clears the HcInterruptEnable UE bit. 3 RD Resume detected Read always returns 0. Write of 0 has no effect. Write of 1 clears the HcInterruptEnable RD bit. 2 SF Start of frame Read always returns 0. Write of 0 has no effect. Write of 1 clears the HcInterruptEnable SF bit. SPRU677 SPRU677 Universal Serial Bus 37 USB Host Controller Registers Table 7. HC Interrupt Disable Register (HcInterruptDisable) (Continued) Bits Field Description Type Reset Value 1 WDH Write done head R/W 0 R/W 0 Read always returns 0. Write of 0 has no effect. Write of 1 clears the HcInterruptEnable WDH bit. 0 SO Scheduling overrun Read always returns 0. Write of 0 has no effect. Write of 1 clears the HcInterruptEnable SO bit. The HCAA address register defines the local bus virtual address of the beginning of the HCCA. Table 8. HC HCAA Address Register (HcHCCA) Bits Field Description Type Reset Value 31-8 HCCA See Section 6.1, Local Bus Addressing, for the restrictions on local bus virtual addresses. R/W 0 7-0 Reserved Reserved R 0 The HC current periodic register defines the local bus virtual address of the next endpoint descriptor (ED) on the periodic ED List. 38 Universal Serial Bus SPRU677 SPRU677 USB Host Controller Registers Table 9. HC Current Periodic Register (HcPeriodCurrentED) Bits Field Description Type 31-4 PCED Local bus virtual address of current ED on the periodic ED list. Reset Value R/0 0x0000 000 R 0x0 This field represents bits 31:4 of the local bus virtual address of the next ED on the periodic ED List. EDs are assumed to begin at 16-byte-aligned address, so bits 3:0 of this pointer are assumed to be 0. See Section 6.1, Local Bus Addressing, for the restrictions on local bus virtual addresses. 3-0 Reserved Reserved The HC head control register defines the local bus virtual address of the head ED of the control ED list. Table 10. HC Head Control Register (HcControlHeadED) Bits Field Description Type Reset Value 31-4 CHED Local bus virtual address of head ED on the control ED list R/W 0 R 0x0 This field represents bits 31:4 of the local bus virtual address of the head ED on the control ED list. EDs are assumed to begin at 16-byte-aligned address, so bits 3:0 of this pointer are assumed to be 0. See See Section 6.1, Local Bus Addressing, for the restrictions on local bus virtual addresses. 3-0 Reserved Reserved The HC current control register defines the local bus virtual address of the next ED on the control ED list. SPRU677 SPRU677 Universal Serial Bus 39 USB Host Controller Registers Table 11. HC Current Control Register (HcControlCurrentED) Bits Field Description Type Reset Value 31-4 CCED Local bus virtual address of current ED on the control ED list R/W 0 R 0x0 This field represents bits 31:4 of the local bus virtual address of the next ED on the control ED list. EDs are assumed to begin at 16-byte-aligned address, so bits 3:0 of this pointer are assumed to be 0. See See Section 6.1, Local Bus Addressing, for the restrictions on local bus virtual addresses. A value of 0x0000000 indicates that the USB host controller has reached the end of the control ED list without finding any transfers to process. This register is automatically updated by the USB host controller. 3-0 40 Reserved Reserved Universal Serial Bus SPRU677 SPRU677 USB Host Controller Registers The HC head bulk register defines the local bus virtual address of the head ED on the bulk ED list. Table 12. HC Head Bulk Register (HcBulkHeadED) Bits Field Description Type Reset Value 31-4 BHED Local bus virtual address of head ED on the bulk ED list R/W 0 R 0x0 This field represents bits 31:4 of the local bus virtual address of the head ED on the bulk ED list. EDs are assumed to begin at 16-byte-aligned address, so bits 3:0 of this pointer are assumed to be 0. See See Section 6.1, Local Bus Addressing, for the restrictions on local bus virtual addresses. 3-0 Reserved Reserved The HC current bulk register defines the local bus virtual address of the next ED on the bulk ED list. Table 13. HC Current Bulk Register (HcBulkCurrentED) Bits Field Description Type Reset Value 31-4 BCED Local bus virtual address of current ED on the bulk ED list R/W 0 R 0x0 This field represents bits 31:4 of the local bus virtual address of the next ED on the bulk ED list. EDs are assumed to begin at 16-byte-aligned address, so bits 3:0 of this pointer are assumed to be 0. See See Section 6.1, Local Bus Addressing, for the restrictions on local bus virtual addresses. A value of 0x0000000 indicates that the USB host controller has reached the end of the bulk ED list without finding any transfers to process. This register is automatically updated by the USB host controller. 3-0 SPRU677 SPRU677 Reserved Reserved Universal Serial Bus 41 USB Host Controller Registers The HC head done register defines the local bus virtual address of the current head of the done TD queue. Table 14. HC Head Done Register (HcDoneHead) Bits Field Description 31-4 DH Local bus virtual address of the last TD that was added to the done queue. Type Reset Value R 0x0000000 R 0x0 This field represents bits 31:4 of the local bus virtual address of the top TD on the done TD queue. TDs are assumed to begin at 16-byte-aligned address, so bits 3:0 of this pointer are assumed to be 0. See See Section 6.1, Local Bus Addressing, for the restrictions on local bus virtual addresses. A value of 0x00000000 indicates that there are no TDs on the done queue. This register is automatically updated by the USB host controller. 3 -0 Reserved Reserved The HC frame interval register defines the number of 12-MHz clock pulses in each USB frame. Table 15. HC Frame Interval Register (HcFmInterval) Bits 31 Field Description Type Reset Value FIT Frame interval toggle R/W 0 R/W 0 R/W 0x2EDF The host controller driver must toggle this bit any time it changes the frame interval field. 30-16 FSMPS Largest data packet Largest data packet size allowed for full speed packets, in bit times. 15-14 Reserved Reserved 13-0 FI Frame interval The number of 12-MHz clocks in the USB frame. Nominally, this is set to 11,999, to give a 1-ms frame. The host controller driver may make minor changes to this field to attempt to manually synchronize with another clock source. 42 Universal Serial Bus SPRU677 SPRU677 USB Host Controller Registers The HC frame remaining register reports the number of full-speed bit times remaining in the current frame. Table 16. HC Frame Remaining Register (HcFmRemaining) Bits Field 31 FRT Type 0 R Frame remaining toggle Reset Value R Description 0 This bit is loaded with the frame interval toggle bit every time the USB host controller loads the frame interval field into the frame remaining field. 30-14 Reserved Reserved 13-0 FR Frame remaining The number of full-speed bit times remaining in the current frame. This field is automatically reloaded with the frame interval field value at the beginning of every frame. The HC frame number register reports the current USB frame number. Table 17. HC Frame Number Register (HcFmNumber) Bits Field 31-16 Reserved FN R Frame number Reset Value 0 Reserved 15-0 Type Description This field reports the current USB frame number. It is incremented when the frame remaining field is reloaded with the frame interval field value. Frame number automatically rolls over from 0xFFFF to 0x0000. After frame number is incremented, its new value is written to the HCCA and the USB host controller sets the SOF interrupt status bit and begins processing the ED lists. SPRU677 SPRU677 Universal Serial Bus 43 USB Host Controller Registers The HC periodic start register defines the position within the USB frame where EDs on t