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SP 320 Dots Data Bank MAR. 06, 2002 Version 1.3 SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without

 

SPLB24A SPLB24A SP 320 Dots Data Bank MAR. 06, 2002 Version 1.3 SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus. SPLB24A SPLB24A Table of Contents PAGE 1. GENERAL DESCRIPTION. 3 2. BLOCK DIAGRAM . 3 3. FEATURES. 3 4. APPLICATION FIELD . 3 5. SIGNAL DESCRIPTIONS . 4 6. FUNCTIONAL DESCRIPTIONS. 5 6.1. ROM AREA . 5 6.2. MASK OPTIONS. 5 6.3. LCD MAPPING AND SPECIFICATION . 5 7. ELECTRICAL SPECIFICATIONS . 6 7.1. ABSOLUTE MAXIMUM RATINGS . 6 7.2. DC CHARACTERISTICS (VDD = 3.0V, TA = 25) . 6 7.3. DC CHARACTERISTICS (VDD = 4.5V, TA = 25) . 6 7.4. THE RELATIONSHIP BETWEEN THE ROSC AND THE FCPU . 7 8. APPLICATION CIRCUITS. 8 8.1. APPLICATION CIRCUIT - (1). 8 8.2. APPLICATION CIRCUIT - (2). 9 9. PACKAGE/PAD LOCATIONS . 10 9.1. PAD ASSIGNMENT . 10 9.2. ORDERING INFORMATION . 10 9.3. PAD LOCATIONS .11 10. DISCLAIMER. 12 11. REVISION HISTORY . 13 © Sunplus Technology Co., Ltd. Proprietary & Confidential 2 MAR. 06, 2001 Version: 1.3 SPLB24A SPLB24A 320 DOTS DATA BANK 3. FEATURES 1. GENERAL DESCRIPTION SPLB24A SPLB24A is an 8-bit CMOS microprocessor with advanced ! 8-bit microprocessor processing technology and mechanisms by Sunplus. ! 22K bytes ROM It includes 1280-bytes working RAM, 22K-bytes ROM, 8 I/Os, an interrupt ! 40 dual port SRAM for 40 x 8 LCD display buffer controller, a timer and a LCD controller/driver. ! 128 bytes SRAM for CPU working space The 22K-byte ROM provides proper space for LCD graphic data. ! 1152 bytes SRAM for data The 1280-bytes of CPU working SRAM is available to users for ! 8 I/O ports programming and data storage. ! LCD controller/driver (1/4 bias, VOP = VDD, Type-B) The SPLB24A SPLB24A is capable of . 40 x 8 (320 dots) driving sophisticated functions and displaying remarkable LCD graphics. . 40 x 6 (240 dots) A Sleep (power-down) feature is also built-in to reduce power consumption. ! Built-in R-oscillator and 32.768KHz crystal oscillator The SPLB24A SPLB24A is a high-end micro-controller that includes, not only the latest technology, but also the full ! 8-bit reloadable timer/counter with prescaler commitment and support of Sunplus. ! NMI controller with following sources Clearly the most suitable . 2Hz for Real Time Counter (RTC) solution for your product needs. . 128Hz . Key (PA7 - 0) 2. BLOCK DIAGRAM . Counter overflow ! Halt and Standby mode ROSC , X32I , X32O ! Watchdog Timer (WDT) ! Power saving sleep mode 8-bit Micro Processor Low Voltage Power Down Prescaler Time Base Timer Interrupt Logic ! Low Voltage Power Down I/O ! Wide operating range: 2.4V - 3.6V @ 1.0MHz PA7 - 0 Ports 3.6V - 5.5V @ 1.0MHz Watch Dog Timer 4. APPLICATION FIELD ROM 24K Bytes LCD Controller SRAM 40 Bytes 128 Bytes 1152 Bytes ! Hand held games Key ! Pet games Scan BIAS Controller ! Educational games, etc. Ports 40 Segments x 8 Commons LCD Driver SEG40 SEG40 - 1 COM8 - 1 © Sunplus Technology Co., Ltd. Proprietary & Confidential 3 MAR. 06, 2001 Version: 1.3 SPLB24A SPLB24A 5. SIGNAL DESCRIPTIONS Mnemonic PIN No. Type Description VDD 9 I Power supply input VSS 22 I GND RESET 11 I System reset input (internal pull-high), low active TEST 63 I Test input (internal pull-low), high active X32I 13 I 32.768 KHz crystal input X32O 12 O 32.768 KHz crystal output R-oscillator input, connect a resistor to VDD through a resistor ROSC 10 I PA7 - 0 21 - 14 I/O Input / output port COM8 - 1 8-1 O LCD common output. COM7, COM8 can be reassigned as IOZ6, IOZ7 SEG40 SEG40 - 1 23 - 62 O LCD segment output. See note 1 below. Note1: SEG16 SEG16 - 1 can be used as keyboard scan output pins by programming register ($007E). Note2: When the ROSC mode is selected, pin X32I should be connected to VSS and X32O should be floating. Key scan options are as follows: Key scan port No. 1-8 9 - 16 © Sunplus Technology Co., Ltd. Proprietary & Confidential Key scan assignment options ($ 007E) bit 2, bit 1, bit 0 SEG1 - 8 or 1, SEG9 - 16 1, 1, 0 SEG1 - 16 1, 1, 1 4 0, 1 MAR. 06, 2001 Version: 1.3 SPLB24A SPLB24A 6. FUNCTIONAL DESCRIPTIONS 6.2.2. Watchdog enable / Watchdog disable 6.1. ROM Area $0000 There is an on-chip WDT (Watchdog Timer) available in the LCD display buffer SPLB24A SPLB24A. ( 40 bytes used ) $003F crash. $0040 Unused $006F $0070 $007F $0080 reset to restart system after 1 second. I/O Port /Registers WDT can be cleared by writing to address ($007F). ( 128 bytes ) The data SRAM address map : (1152 bytes) $0200 - $047F also map to SRAM $1200 - $147F $2000 - $247F also map to SRAM $1000 - $147F $3000 - $347F also map to SRAM $1000 - $147F Data SRAM ( 1152 bytes ) $147F $A000 Note that the 6.2.3. Low voltage power down (LVPD) enable/disable The Low Voltage Power Down circuit is enabled only when 32768 Test program ROM (2K bytes) $A7FF $A800 The WDT only works when 32768 crystal is available. Reserved $01FF $1000 If the WDT is enabled, the WDT is cleared every 0.5 seconds to avoid accidental reset. CPU working SRAM $00FF $0100 The WDT is designed for recovering from a system If the system is stalled, the WDT will generate a system signal is available. $X000 - $X47F also map to SRAM $1000 - $147F There are 1152 Bytes available in $0200 - $7FFF Program ROM system will enter the Low Voltage (standby) mode after the R-osc Note: $FFF2 - $FFF7 are reserved for testing (22K bytes) If the LVPD circuit senses VDD < 2.2V, the stops. $FFFF In the Low Voltage mode current consumption is minimized. This feature can be used to avoid possible data loss during battery replacement. 6.2. Mask Options 6.2.1. 32K from Crystal / R-osc with prescaler 6.3. LCD Mapping and Specification When the crystal mode is selected, the system time base, LCD SRAM space ($00H - $3F) is allocated for LCD display buffer. To timing, and auto-strobe signal is generated form the 32.768KHz display a pattern on the LCD, the user simply writes the crystal oscillator. corresponding bits as display buffer. The following table shows the The R-osc option is provided to support system mapping between LCD and display buffer. timebase, LCD timing, and auto-strobe signal without 32.768KHz crystal oscillator. When the R-osc mode is selected, the signals and timings will be generated from pre-scaler. By programming register ($007C), users can get a suitable clock (R-osc) to replace the 32.768 KHz clock. Bit-5 of register ($007A) can also turn off this clock. SEG8 - 1 SEG16 SEG16 - 9 SEG24 SEG24 - 17 SEG32 SEG32 - 25 SEG40 SEG40 - 33 (b7 - 0) (b7 - 0) (b7 - 0) (b7 - 0) (b7 - 0) COM1 07H 06H 05H 04H 03H COM2 0FH 0EH 0DH 0CH 0BH COM3 17H 16H 15H 14H 13H COM4 1FH 1EH 1DH 1CH 1BH COM5 27H 26H 25H 24H 23H COM6 2FH 2EH 2DH 2CH 2BH COM7 37H 36H 35H 34H 33H COM8 3FH 3EH 3DH 3CH 3BH The SPLB24A SPLB24A supports LCD's with the following characteristics: Duty: 1/6 or 1/8 Bias: 1/4; VLCD = VDD V1 = VDD * 3/4 V2 = VDD * 2/4 V3 = VDD * 1/4 VEE = GND © Sunplus Technology Co., Ltd. Proprietary & Confidential 5 MAR. 06, 2001 Version: 1.3 SPLB24A SPLB24A 7. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Characteristics Symbol Ratings VDD < 6.0V Input Voltage Range VIN -0.5V to VDD + 0.5V Operating Temperature TA 0 to +60 TSTO -50 to +150 DC Supply Voltage Storage Temperature Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics. 7.2. DC Characteristics (VDD = 3.0V, TA = 25) Characteristics Operating Voltage Symbol Limit Unit Min. Typ. Max. VDD 2.4 - 5.5 V IOP - 160 - µA Standby Current ISTBY - - 2.0 µA Input High Level VIH 2.0 - - V Operating Current Input Low Level VIL - - 0.8 V Output high I (PA5 - 0) IOH - -1.0 - mA Output sink I (PA5 - 0) IOL - 1.0 - mA Output high I (PA7 - 6) IOH - -2.5 - mA Output sink I (PA7 - 6) IOL - 2.5 - mA 7.3. DC Characteristics (VDD = 4.5V, TA = 25) Characteristics Operating Voltage Symbol Limit Unit Min. Typ. Max. VDD 2.4 - 5.5 V IOP - 400 - µA Standby Current ISTBY - - 2.0 µA Input High Level VIH 3.0 - - V Operating Current Input Low Level VIL - - 0.8 V Output high I (PA5 - 0) IOH - - 1.0 - mA Output sink I (PA5 - 0) IOL - 1.0 - mA Output high I (PA7 - 6) IOH - - 3.0 - mA Output sink I (PA7 - 6) IOL - 3.0 - mA © Sunplus Technology Co., Ltd. Proprietary & Confidential 6 MAR. 06, 2001 Version: 1.3 SPLB24A SPLB24A 7.4. The Relationship between the ROSC and the FCPU 7.4.2. VDD = 4.5V, TA = 25 1.0 ( MHz ) 1.0 0.5 CPU 0.5 F F CPU ( MHz ) 7.4.1. VDD = 3.0V, TA = 25 0.0 0 200 400 600 800 0 Rosc ( Kohms ) © Sunplus Technology Co., Ltd. Proprietary & Confidential 0.0 200 400 600 800 Rosc ( Kohms ) 7 MAR. 06, 2001 Version: 1.3 SPLB24A SPLB24A 8. APPLICATION CIRCUITS 8.1. Application Circuit - (1) VDD R1 680K C1 30p 200 µ F 20p C3 20p C2 RESET VDD 0.1 µ 32768Hz 0.1 µ F COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 VDD ROSC RESET X32O X32I PA0 PA1 PA2 SPLB24A SPLB24A PA1 PA2 PA3 PA4 SW1 SW2 SW3 SW4 SW5 SW6 PA0 PA5 SEG40 SEG40 SEG39 SEG39 SEG38 SEG38 SEG37 SEG37 SEG36 SEG36 SEG35 SEG35 SEG34 SEG34 SEG33 SEG33 SEG32 SEG32 SEG15 SEG15 SEG16 SEG16 SEG17 SEG17 SEG18 SEG18 SEG19 SEG19 SEG20 SEG20 SEG21 SEG21 SEG22 SEG22 SEG23 SEG23 SEG24 SEG24 SEG25 SEG25 SEG26 SEG26 SEG27 SEG27 SEG28 SEG28 SEG29 SEG29 SEG30 SEG30 SEG31 SEG31 PA6 PA7 L1 SEG[40.1] LCD DISPLAY 40 SEGMENTS X 8 COMMONS COM[8.1] Buzzer Version: 1.3 Proprietary & Confidential MAR. 06, 2001 8 © Sunplus Technology Co., Ltd. TEST SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG10 SEG11 SEG11 SEG12 SEG12 SEG13 SEG13 SEG14 SEG14 PA3 PA4 PA5 PA6 PA7 VSS SPLB24A SPLB24A 8.2. Application Circuit - (2) COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 VDD ROSC VDD R1 0.1 µ C2 C1 30p 20p C3 RESET X32O 32768Hz RESET X32I PA0 PA1 PA2 SPLB24A SPLB24A PA3 PA4 PA5 PA6 PA7 VSS SEG40 SEG40 SEG39 SEG39 SEG38 SEG38 SEG37 SEG37 SEG36 SEG36 SEG35 SEG35 SEG34 SEG34 SEG33 SEG33 SEG32 SEG32 680K TEST SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG10 SEG11 SEG11 SEG12 SEG12 SEG13 SEG13 SEG14 SEG14 SEG[40.1] SEG15 SEG15 SEG16 SEG16 SEG17 SEG17 SEG18 SEG18 SEG19 SEG19 SEG20 SEG20 SEG21 SEG21 SEG22 SEG22 SEG23 SEG23 SEG24 SEG24 SEG25 SEG25 SEG26 SEG26 SEG27 SEG27 SEG28 SEG28 SEG29 SEG29 SEG30 SEG30 SEG31 SEG31 LCD DISPLAY 40 SEGMENTS X 8 COMMONS COM[8.1] 20p VDD 0.1 µ F PA1 PA2 PA3 PA4 PA5 PA6 PA7 L1 ON/OFF Seg 1 Seg 2 Seg 3 Seg 15 . 200 µ F PA0 Buzzer Seg16 . PA1 . PA2 . PA3 . PA4 . PA5 Note1: In the CRYSTAL mode, the 32768Hz crystal oscillator generates an accurate time base. The Crystal mode requires the installation of a 32768Hz crystal oscillator. Note2: In the ROSC mode, a suitable time base is generated from the R-Oscillator. A 32768Hz crystal oscillator does not need to be installed. Note 3: To avoid noise interference on the PCB around R-Oscillator and crystal circuit, the following installation guidelines are suggested: 1). R1 and C1 should be placed as near as possible to the ROSC pin. 2). C2, C3 and the Crystal should be placed as near as possible to X32I and X32O. © Sunplus Technology Co., Ltd. Proprietary & Confidential 9 A shielding by ground is suggested. MAR. 06, 2001 Version: 1.3 SPLB24A SPLB24A 9. PACKAGE/PAD LOCATIONS 9.1. PAD Assignment Chip Size: 2490µm x 3050µm This IC substrate should be connected to VSS Note1: Chip size included scribe line. Note2: The 0.1µF capacitor between VDD and VSS should be placed to IC as close as possible. 9.2. Ordering Information Product Number Package Type SPLB24A-nnnnV-C Chip form Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (V = A - Z). © Sunplus Technology Co., Ltd. Proprietary & Confidential 10 MAR. 06, 2001 Version: 1.3 SPLB24A SPLB24A 9.3. PAD Locations PAD No. PAD Name X Y PAD No. PAD Name X Y 1 COM1 -1075 1301 33 SEG30 SEG30 1071 -1125 2 COM2 -1075 1166 34 SEG29 SEG29 1071 -985 3 COM3 -1075 1031 35 SEG28 SEG28 1071 -845 4 COM4 -1075 896 36 SEG27 SEG27 1071 -705 5 COM5 -1075 761 37 SEG26 SEG26 1071 -570 6 COM6 -1075 631 38 SEG25 SEG25 1071 -440 7 COM7 -1075 501 39 SEG24 SEG24 1071 -310 8 COM8 -1075 371 40 SEG23 SEG23 1071 -180 9 VDD -1075 -313 41 SEG22 SEG22 1071 244 10 ROSC -1075 -448 42 SEG21 SEG21 1071 374 11 RESET -1075 -583 43 SEG20 SEG20 1071 504 12 X32O -1075 -718 44 SEG19 SEG19 1071 634 13 X32I -1075 -853 45 SEG18 SEG18 1071 764 14 PA0 -1075 -988 46 SEG17 SEG17 1071 904 15 PA1 -1075 -1123 47 SEG16 SEG16 1071 1044 16 PA2 -1075 -1258 48 SEG15 SEG15 1071 1184 17 PA3 -954 -1357 49 SEG14 SEG14 1026 1357 18 PA4 -819 -1357 50 SEG13 SEG13 862 1357 19 PA5 -684 -1357 51 SEG12 SEG12 722 1357 20 PA6 -549 -1357 52 SEG11 SEG11 582 1357 21 PA7 -414 -1357 53 SEG10 SEG10 442 1357 22 VSS -279 -1357 54 SEG9 302 1357 23 SEG40 SEG40 -144 -1357 55 SEG8 167 1357 24 SEG39 SEG39 -9 -1357 56 SEG7 32 1357 25 SEG38 SEG38 126 -1357 57 SEG6 -103 1357 26 SEG37 SEG37 261 -1357 58 SEG5 -238 1357 27 SEG36 SEG36 396 -1357 59 SEG4 -373 1357 28 SEG35 SEG35 531 -1357 60 SEG3 -513 1357 29 SEG34 SEG34 666 -1357 61 SEG2 -653 1357 30 SEG33 SEG33 801 -1357 62 SEG1 -793 1357 31 SEG32 SEG32 936 -1357 63 TEST -933 1357 32 SEG31 SEG31 1071 -1265 © Sunplus Technology Co., Ltd. Proprietary & Confidential 11 MAR. 06, 2001 Version: 1.3 SPLB24A SPLB24A 10. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only. © Sunplus Technology Co., Ltd. Proprietary & Confidential 12 MAR. 06, 2001 Version: 1.3 SPLB24A SPLB24A 11. REVISION HISTORY Date Revision # Description JUL. 29, 1998 0.1 Original SEP. 01, 1998 0.2 Modify "LVD sensed VDD