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Part Manufacturer Description PDF Samples Ordering
UCC5672PWPTRG4 Texas Instruments 9 Line 2.7-5V Multimode Terminator for SCSI through Ultra320 with SPI-3 Mode Change Delay 28-TSSOP 0 to 70 pdf Buy
UCC5672PWPG4 Texas Instruments 9 Line 2.7-5V Multimode Terminator for SCSI through Ultra320 with SPI-3 Mode Change Delay 28-TSSOP 0 to 70 pdf Buy Buy
UCC5672PWPTR Texas Instruments 9 Line 2.7-5V Multimode Terminator for SCSI through Ultra320 with SPI-3 Mode Change Delay 28-TSSOP 0 to 70 pdf Buy

Search Stock

Part Manufacturer Description Last Check Distributor Ordering
SPI-41 Cooper Hand Tools SOLDERING IRON, 40W, 230V, EURO 10 from $62.6240 (Aug 2016) element14 Asia-Pacific Buy
SPI-41 Cooper Hand Tools SOLDERING IRON, 40W, 230V, EURO 63 from £29.9700 (Aug 2016) Farnell element14 Buy
SPI-41. Cooper Hand Tools SOLDERING IRON, 40W, 230V, EURO 10 from $62.6240 (Aug 2016) element14 Asia-Pacific Buy
SPI-41. Cooper Hand Tools SOLDERING IRON, 40W, 230V, EURO 63 from £29.9700 (Aug 2016) Farnell element14 Buy
SPI-42-E3-U3 Lattice Semiconductor Development Software System Packet Level 4, Phase 2 from $16312.50 (Sep 2016) Mouser Electronics Buy
SPI-42-E3-UT3 Lattice Semiconductor Development Software from $48937.50 (Sep 2016) Mouser Electronics Buy
SPI-42-P2-U4 Lattice Semiconductor Development Software SPI4.2 User Config from $16312.50 (Sep 2016) Mouser Electronics Buy
SPI-42-P2-UT4 Lattice Semiconductor Development Software SPI 4.2 from $48937.50 (Sep 2016) Mouser Electronics Buy
SPI-42-PM-U4 Lattice Semiconductor Development Software SPI4.2 User Config from $16312.50 (Sep 2016) Mouser Electronics Buy
SPI-42-PM-UT4 Lattice Semiconductor Development Software SPI4.2 from $48937.50 (Sep 2016) Mouser Electronics Buy
SPI-42-SC-U4 Lattice Semiconductor Development Software SPI4.2 User Config from $16312.50 (Aug 2016) Mouser Electronics Buy
SPI-42-SC-UT4 Lattice Semiconductor Development Software SPI 4.2 from $48937.50 (Aug 2016) Mouser Electronics Buy

SPI-4 Datasheet

Part Manufacturer Description PDF Type Ordering
SPI-4 Exemplar Logic Core w/ FIFOs V1.0 For Altera PLDs
ri

3 pages,
85.02 Kb

Original Buy
datasheet frame
SPI42N03S2L-13 N/A OptiMOS Power Amplifier, 30V 42A 64W, MOS-FET N-Channel enhanced
ri

8 pages,
517.02 Kb

Original Buy
datasheet frame
SPI42N03S2L-13 Infineon Technologies OptiMOS Power-Transistor
ri

8 pages,
410.79 Kb

Original Buy
datasheet frame
SPI42N03S2L-13 Infineon Technologies OptiMOS Power-Transistor
ri

10 pages,
538.12 Kb

Original Buy
datasheet frame
SPI47N10 Infineon Technologies SIPMOS Power-Transistor
ri

8 pages,
104.75 Kb

Original Buy
datasheet frame
SPI47N10 Infineon Technologies SIPMOS Power-Transistor
ri

8 pages,
508.5 Kb

Original Buy
datasheet frame
SPI47N10L Infineon Technologies SIPMOS Power-Transistor
ri

8 pages,
110.86 Kb

Original Buy
datasheet frame
SPI47N10L Infineon Technologies SIPMOS Power-Transistor
ri

8 pages,
511.17 Kb

Original Buy
datasheet frame
SPI-42-E3-U3 Lattice Semiconductor Software, Programmers, Development Systems, IP CORE SPI 4.2 REV.1 ECP3 CONF
ri

62 pages,
0 Kb

Original Buy
datasheet frame
SPI-42-E3-UT3 Lattice Semiconductor Software, Programmers, Development Systems, IP CORE SPI 4.2 ECP3
ri

4 pages,
0 Kb

Original Buy
datasheet frame

SPI-4

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: PRODUCT BRIEF IDT88P8344 IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4 To request the full IDT88P8344 IDT88P8344 , Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP configurable memory allocation , address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 256 concurrently active LPs - SPI-4 FIFO status channel options: • LVDS full-rate â , operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire frequency range - ... Integrated Device Technology
Original
datasheet

5 pages,
59.21 Kb

IDT88P8344 TEXT
datasheet frame
Abstract: SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 FEATURES · Functionality - Low speed to high speed SPI exchange device - Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP , , 19.44-133 MHz, 256 address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 256 concurrently active LPs - SPI-4 FIFO status channel options: · LVDS , mode of operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire ... Integrated Device Technology
Original
datasheet

98 pages,
644.12 Kb

IDT88P8344 TEXT
datasheet frame
Abstract: PRODUCT BRIEF IDT88P8341 IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 To request the full IDT88P8341 IDT88P8341 , Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP configurable memory allocation , range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 64 concurrently active LPs - SPI-4 FIFO status channel options: • LVDS full-rate • LVTTL , SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire frequency range - SPI-4 ... Integrated Device Technology
Original
datasheet

5 pages,
54.33 Kb

IDT88P8341 TEXT
datasheet frame
Abstract: SPI EXCHANGE 2 x SPI-3 TO SPI-4 Issue 1.0 FEATURES · Functionality - Low speed to high speed SPI exchange device - Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP , , 19.44-133 MHz, 256 address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 128 concurrently active LPs - SPI-4 FIFO status channel options: · LVDS , mode of operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire ... Integrated Device Technology
Original
datasheet

98 pages,
631.34 Kb

IDT88P8342 TSOP 48 thermal resistance type1 TEXT
datasheet frame
Abstract: LatticeSCM SPI4.2 Interoperability with PMC-Sierra PM3388 PM3388 August 2006 Technical Note TN1121 TN1121 Introduction The System Packet Interface, Level 4, Phase 2 (SPI4.2) is a system level interface, published in , and a network processor or switch fabric, the SPI4.2 interface supports the aggregate bandwidths required of ATM and packet-over-SONET/SDH (POS) applications. Moreover, SPI4.2 provides a common interface , into a single 10Gbps uplink for long haul or backbone transmission. Typically, SPI4.2 has a 16 ... Lattice Semiconductor
Original
datasheet

9 pages,
3392.06 Kb

DDR2 sodimm pcb layout PM3388 AX4000 TN1121 TEXT
datasheet frame
Abstract: PRODUCT BRIEF IDT88P8344 IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4 - Number of errors - Number of , Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP configurable memory allocation , address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 256 concurrently active LPs - SPI-4 FIFO status channel options: · LVDS full-rate · , operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire frequency range - ... Integrated Device Technology
Original
datasheet

5 pages,
55.5 Kb

IDT88P8344 DSC-6370 spi FIFO TEXT
datasheet frame
Abstract: SPI4.2 Interoperability Between ORSPI4 and LatticeSC Devices June 2006 Technical Note TN1116 TN1116 Introduction The System Packet Interface, Level 4, Phase 2 (SPI4.2) is a system level interface, published in , between a MAC device and a network processor or switch fabric, the SPI4.2 interface supports the aggregate bandwidths required of ATM and packet-over-Sonet/SDH (POS) applications. Moreover, SPI4.2 , , SPI4.2 has a 16-bit LVDS interface that operates at rates from 622Mbps to 900Mbps. These high data ... Lattice Semiconductor
Original
datasheet

9 pages,
1361.46 Kb

POWR1208 pDS4102-DL2A ORSPI4-2FE1036C IXF18101 TN1116 TEXT
datasheet frame
Abstract: instantiation of OIF-compliant System Packet Interface Level 4 Phase 2 Revision 1 (SPI4.2.1) cores in Lattice , core is fully compliant with the OIF System Packet Interface Level 4 Phase 2 Revision 1 (SPI4.2.1 , 'TxBLEN[5:0]', where a value of one results in standard SPI4.2 behavior (16 byte minimum burst), a value , Soft SPI4 IP Core User’s Guide September 2010 IPUG59 IPUG59_01.7 Table of Contents Chapter 1 , . 6 SPI4 Transmitter - S4TX ... Lattice Semiconductor
Original
datasheet

62 pages,
1829.44 Kb

IPUG59 TEXT
datasheet frame
Abstract: PRODUCT BRIEF IDT88P8341 IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 - Number of errors - Number of bytes , (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP configurable memory allocation - , concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 64 concurrently active LPs - SPI-4 FIFO status channel options: • LVDS full-rate • LVTTL quarter-rate - Compatible with Network Processor Streaming Interface (NPSI) NPE-Framer mode of operation - SPI-4 ingress ... Integrated Device Technology
Original
datasheet

5 pages,
49.76 Kb

IDT88P8341 TEXT
datasheet frame
Abstract: SPI EXCHANGE SPI-3 TO SPI-4 Issue 1.0 FEATURES · Functionality - Low speed to high speed SPI exchange device - Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP configurable , address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 64 concurrently active LPs - SPI-4 FIFO status channel options: · LVDS full-rate · , operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire frequency range - ... Integrated Device Technology
Original
datasheet

96 pages,
532.14 Kb

TSOP 28 SPI memory Package flash spi flash parallel port JTAG MODULE SPI TEXT
datasheet frame
Abstract: SPI EXCHANGE 2 x SPI-3 TO SPI-4 Issue 1.0 FEATURES · Functionality - Low speed to high speed SPI exchange device - Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP , , 19.44-133 MHz, 256 address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 128 concurrently active LPs - SPI-4 FIFO status channel options: · LVDS , mode of operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire ... Silicon Laboratories
Original
datasheet

16 pages,
557.07 Kb

TQFP64 C8051F705-GQ C8051F714-GM 8051 interfacing to EEProm qfn48 QFP48 QFP48 package TQFP48 EEPROM Silabs 8051 spi eeprom C8051F700 high level block diagram for eeprom TEXT
datasheet frame
Abstract: , SPI4.2, SFI-4, UTOPIA, XGMII and CSIX. The LatticeSCM devices feature clock multiply, divide and , property (IP) designed to handle chip-to-chip communications standards. For instance, SPI4.2 is a popular , gates. Other FPGA vendors offer SPI4.2 solutions as soft IP that consume FPGA resources and make user , SPI4.2 interface is an Ethernet-to-SONET bridge. In Figure 5 the FPGA is used to manage the bridge , SPI4.2 interfaces in this example have to be implemented in soft IP using FPGA gates, the design ... Fulcrum Microsystems
Original
datasheet

2 pages,
44.72 Kb

FULCRUM FM1020 1232B FM1010 TEXT
datasheet frame

Archived Files

Abstract Saved from Date Saved File Size Type Download
No abstract text available
/download/91401815-995983ZC/xapp525.zip ()
Xilinx 31/03/2004 399.48 Kb ZIP xapp525.zip
BTJT SPI_MI,spi_4 ; Copy data bit from line to carry flag. .spi_4 BRES SPI_CLK DEC X ; One more bit
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/5700-v3.htm
STMicroelectronics 16/01/2001 12.64 Kb HTM 5700-v3.htm
No abstract text available
/download/30716330-845108ZC/an972-v1.zip ()
STMicroelectronics 08/04/1998 3.89 Kb ZIP an972-v1.zip
SPI_CLK BTJT SPI_MI,spi_4 ; Copy data bit from line to carry flag. .spi_4 BRES SPI_CLK DEC X ; One more
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/5700-v4.htm
STMicroelectronics 25/05/2000 12.43 Kb HTM 5700-v4.htm
BTJT SPI_MI,spi_4 ; Copy data bit from line to carry flag. .spi_4 BRES SPI_CLK DEC X ; One more bit
/datasheets/files/stmicroelectronics/stonline/books/ascii/an/5700.htm
STMicroelectronics 17/09/1999 12.47 Kb HTM 5700.htm
BTJT SPI_MI,spi_4 ; Copy data bit from line to carry flag. .spi_4 BRES SPI_CLK DEC X ; One more bit
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/5700.htm
STMicroelectronics 02/04/1999 10.63 Kb HTM 5700.htm
BTJT SPI_MI,spi_4 ; Copy data bit from line to carry flag. .spi_4 BRES SPI_CLK DEC X ; One more bit
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/5700-v2.htm
STMicroelectronics 14/06/1999 10.59 Kb HTM 5700-v2.htm
No abstract text available
/download/33694577-844041ZC/an972.zip ()
STMicroelectronics 04/01/2001 3.89 Kb ZIP an972.zip
BTJT SPI_MI,spi_4 ; Copy data bit from line to carry flag. .spi_4 BRES SPI_CLK DEC X ; One more bit
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/5700-v1.htm
STMicroelectronics 20/10/2000 12.75 Kb HTM 5700-v1.htm
a fully integrated single-chip mesh fabric controller implementing a 10 Gb SPI4.2 interface to the support package (BSP) is also available. Programmable I/O suitable for SPI4.2, CSIX, or other
/datasheets/files/xilinx/files/xcell journal articles/xcell_49/xc_mesh49.htm
Xilinx 26/04/2004 22.44 Kb HTM xc_mesh49.htm

Shortform Datasheet Search

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SPI4 Silicon Sensors, Inc. Transistor-Stage-Output Optocoupler - Photo Interrupter

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