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SPI-4 Datasheet

Part Manufacturer Description PDF Type
SPI-4 Exemplar Logic Core w/ FIFOs V1.0 For Altera PLDs Original
SPI-42-E3-U3 Lattice Semiconductor Software, Programmers, Development Systems, IP CORE SPI 4.2 REV.1 ECP3 CONF Original
SPI-42-E3-UT3 Lattice Semiconductor Software, Programmers, Development Systems, IP CORE SPI 4.2 ECP3 Original
SPI42N03S2L-13 Infineon Technologies OptiMOS Power-Transistor Original
SPI42N03S2L-13 Infineon Technologies OptiMOS Power-Transistor Original
SPI42N03S2L-13 N/A OptiMOS Power Amplifier, 30V 42A 64W, MOS-FET N-Channel enhanced Original
SPI-42-P2-U4 Lattice Semiconductor Software, Programmers, Development Systems, IP CORE SPI 4.2 ECP2 USER CONFIG Original
SPI-42-P2-UT4 Lattice Semiconductor Software, Programmers, Development Systems, SITE LICENSE SPI 4.2 ECP2 CONF Original
SPI-42-PM-U4 Lattice Semiconductor Software, Programmers, Development Systems, IP CORE SPI 4.2 ECP2M USER CONF Original
SPI-42-PM-UT4 Lattice Semiconductor Software, Programmers, Development Systems, SITE LICENSE SPI 4.2 ECP2M CONF Original
SPI-42-SC-U4 Lattice Semiconductor Software, Programmers, Development Systems, IP CORE SPI 4.2 SC/SCM USER CONF Original
SPI-42-SC-UT4 Lattice Semiconductor Software, Programmers, Development Systems, SITE LICENSE SPI 4.2 SC/SCM CONF Original
SPI47N10 Infineon Technologies SIPMOS Power-Transistor Original
SPI47N10 Infineon Technologies SIPMOS Power-Transistor Original
SPI47N10L Infineon Technologies SIPMOS Power-Transistor Original
SPI47N10L Infineon Technologies SIPMOS Power-Transistor Original

SPI-4

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: PRODUCT BRIEF IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4 To request the full IDT88P8344 , Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP configurable memory allocation , address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 256 concurrently active LPs - SPI-4 FIFO status channel options: â'¢ LVDS full-rate â , operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire frequency range - Integrated Device Technology
Original
OIF-SPI4-02 800MH BH820-1 88P8344
Abstract: SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 FEATURES · Functionality - Low speed to high speed SPI exchange device - Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP , , 19.44-133 MHz, 256 address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 256 concurrently active LPs - SPI-4 FIFO status channel options: · LVDS , mode of operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire Integrated Device Technology
Original
Abstract: PRODUCT BRIEF IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 To request the full IDT88P8341 , Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP configurable memory allocation , range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 64 concurrently active LPs - SPI-4 FIFO status channel options: â'¢ LVDS full-rate â'¢ LVTTL , SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire frequency range - SPI-4 Integrated Device Technology
Original
lps 256 88P8341
Abstract: SPI EXCHANGE 2 x SPI-3 TO SPI-4 Issue 1.0 FEATURES · Functionality - Low speed to high speed SPI exchange device - Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP , , 19.44-133 MHz, 256 address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 128 concurrently active LPs - SPI-4 FIFO status channel options: · LVDS , mode of operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire Integrated Device Technology
Original
IDT88P8342 TSOP 48 thermal resistance type1 drw22 88P8342
Abstract: LatticeSCM SPI4.2 Interoperability with PMC-Sierra PM3388 August 2006 Technical Note TN1121 Introduction The System Packet Interface, Level 4, Phase 2 (SPI4.2) is a system level interface, published in , and a network processor or switch fabric, the SPI4.2 interface supports the aggregate bandwidths required of ATM and packet-over-SONET/SDH (POS) applications. Moreover, SPI4.2 provides a common interface , into a single 10Gbps uplink for long haul or backbone transmission. Typically, SPI4.2 has a 16 Lattice Semiconductor
Original
AX4000 DDR2 sodimm pcb layout OC-192 PM-3388 AX-4000 1-800-LATTICE
Abstract: PRODUCT BRIEF IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4 - Number of errors - Number of , Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP configurable memory allocation , address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 256 concurrently active LPs - SPI-4 FIFO status channel options: · LVDS full-rate · , operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire frequency range - Integrated Device Technology
Original
spi FIFO DSC-6370
Abstract: SPI4.2 Interoperability Between ORSPI4 and LatticeSC Devices June 2006 Technical Note TN1116 Introduction The System Packet Interface, Level 4, Phase 2 (SPI4.2) is a system level interface, published in , between a MAC device and a network processor or switch fabric, the SPI4.2 interface supports the aggregate bandwidths required of ATM and packet-over-Sonet/SDH (POS) applications. Moreover, SPI4.2 , , SPI4.2 has a 16-bit LVDS interface that operates at rates from 622Mbps to 900Mbps. These high data Lattice Semiconductor
Original
IXF18101 ORSPI4-2FE1036C pDS4102-DL2A POWR1208 TN1059 IXF1810
Abstract: instantiation of OIF-compliant System Packet Interface Level 4 Phase 2 Revision 1 (SPI4.2.1) cores in Lattice , core is fully compliant with the OIF System Packet Interface Level 4 Phase 2 Revision 1 (SPI4.2.1 , 'TxBLEN[5:0]', where a value of one results in standard SPI4.2 behavior (16 byte minimum burst), a value , Soft SPI4 IP Core Userâ'™s Guide September 2010 IPUG59_01.7 Table of Contents Chapter 1 , . 6 SPI4 Transmitter - S4TX Lattice Semiconductor
Original
LFE3-70EA-8FN672CES D2009 12L-1 LFSC3GA25E-6FF1020C SPI-42-SC-U3
Abstract: PRODUCT BRIEF IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 - Number of errors - Number of bytes , (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP configurable memory allocation - , concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 64 concurrently active LPs - SPI-4 FIFO status channel options: â'¢ LVDS full-rate â'¢ LVTTL quarter-rate - Compatible with Network Processor Streaming Interface (NPSI) NPE-Framer mode of operation - SPI-4 ingress Integrated Device Technology
Original
Abstract: SPI EXCHANGE SPI-3 TO SPI-4 Issue 1.0 FEATURES · Functionality - Low speed to high speed SPI exchange device - Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP configurable , address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 64 concurrently active LPs - SPI-4 FIFO status channel options: · LVDS full-rate · , operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire frequency range - Integrated Device Technology
Original
JTAG MODULE SPI spi flash parallel port TSOP 28 SPI memory Package flash
Abstract: ESC SPI4_Tx_STATUS UP_PAUSE_REQ TX Egress Direction EQ _R ME IBC SPI4_RX PCS , SATISFIED XAUI_TX ISC SPI4_RX_STATUS UP_PAUSE_REQ SMI SPI4_REGS X2S4_REGS & STATS MAC_REGS SPI4_TX_PLL SPI4_RX_PLL SDCK_PLL USI UMI Bus SYSTEM BUS (comp interupt) PCSA , LatticeSCM XAUI to SPI4.2 July 2008 Reference Design RD1033 Introduction The XAUI to SPI4.2 (X2S4) Bridge reference design is a cost-effective system solution for bridging SPI4.2 based network Lattice Semiconductor
Original
higig2 frame format EZchip higig2 higig specification verilog code for spi4.2 to fifo 10G/10G
Abstract: Data Tx FIFO(s) Spi4Tx PHY Layer Processor SPI-4 I/F PluriBus Interface Link Layer Line Rx Data Spi4Rx Control Rx FIFO(s) Status Figure 1: SPI-4 Phase 1 PHY Layer , Spi4Rx PHY Layer Sink FIFO(s) SPI-4 I/F Link Atlantic Interface Line Tx Data , Spi4Tx Detailed documentation: Figure 2: SPI-4 Phase 1 Link Layer Application On the system side , initiates a data transfer from the Source FIFO towards the SPI-4 interface. The Spi4Rx block transmits the Modelware
Original
spi demux
Abstract: PRODUCT BRIEF IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 To request the full IDT88P8342 , Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP configurable memory allocation , address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 128 concurrently active LPs - SPI-4 FIFO status channel options: â'¢ LVDS full-rate â , operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire frequency range - Integrated Device Technology
Original
Abstract: PRODUCT BRIEF IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 - Number of errors - Number of , Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP configurable memory allocation , address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 128 concurrently active LPs - SPI-4 FIFO status channel options: · LVDS full-rate · , operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire frequency range - Integrated Device Technology
Original
spi on parallel port
Abstract: -192 in less than a decade. System-Packet Interface (SPI4.2) Resource-strapped equipment vendors must , . SPI4.2 (System-Packet Interface, Level 4, Phase 2) is a recent system-level interface standard that , infrastructure. Published in 2001 by the Optical Internetworking Forum (OIF), the SPI4.2 standard allows the , SAN. SPI4.2 relieves designers from wasting valuable resources on proprietary ASIC-based or , packet transfer between a MAC device and a network processor or switch fabric, the SPI4.2 interface Lattice Semiconductor
Original
QDR pcb layout 10G serdes 2.5 quad ORT42G5 ORT82G5 P802
Abstract: SPI4.2 Core, 3.7Gbps SERDES, High-Speed Memory Controller + FPGA Introducing the ORCA® ORSPI4, the , ) architecture, the ORSPI4 device contains two OIFcompliant System Packet Interface, Level 4, Phase 2 (SPI4.2 , other devices on a board. Embedded SPI4.2 blocks provide dual 10 Gbits/s Physicalto-Link Layer interfaces in conformance to the OIF-SPI402.0 specification. Each SPI4.2 block provides a bi-directional , DIP-2 parity generation and checking are supported. Embedded Dual-Port RAM in each SPI4.2 core Lattice Semiconductor
Original
I0165A
Abstract: lower-density applications is the FM1020 three-interface SPI-4.2 interconnect.) Features · Six SPI-4 Phase 2 , PivotPointTM FM1010 Product Brief Six-Interface SPI-4.2 Interconnect The PivotPoint FM1010 , multiple chips with SPI-4.2 interfaces, enabling designers to deliver sophisticated systems while , modes. The PivotPoint FM1010 converts a fixedconfiguration half-duplex daisy-chain of devices with SPI-4 , greater flexibility · 16-bit processor interface - SPI-4.2 interface Fulcrum delay-insensitive Fulcrum Microsystems
Original
1232B FULCRUM FM1010-PB-05-0217
Abstract: SPI4-02.0 System Packet Interface Level 4(SPI-4) Phase 2 standard · Supports aggregate bandwidth for , System Packet Interface Level-4P2 OIF Compliant SPI-4P2 IO macro and core logic IP for SPI-4PS and NPSI Link Device Rx-Link Tx-Link SPI-4 Core Logic (data receive) SPI-4 IO data receiver LVDS receiver deskew 1:4 Parallel-Serial SPI-4 Core Logic (data transmit) SPI-4 IO status driver SPI-4 IO data driver SPI-4 IO status receiver LVTTL or LVDS driver (4:1 PS for LVDS Fujitsu
Original
OC192 fujitsu lvds standard DDR PHY ASIC SPI-4PS SPI4 ASIC-FS-20922-4/2003
Abstract: packets are received within 6-7 idles on the TX SPI4-2. Implication: Consecutive SPI4-2 EOP abort , # Description 11 Removed old Item 1 (SPI4-2 Interface Signal Descriptions Table)from , â'Specification Clarificationsâ'. 22 Removed old Item 1 under â'Documentation Changesâ' (SPI4-2 Interface , Reading SPI4-2 Registersâ' from PlanFix to Fixed. 14 Changed Erratum 12, â'TSCLK Not Output At a , EOP on the SPI4-2 Interfaceâ' from PlanFix to Fixed. 15 Changed Erratum 16, â'RX FIFO Intel
Original
IXF1010 HFIXF1010CC B3534-02
Abstract: -3 links and a SPI-4 link. The SPI-4.2 interface block provides a 10Gbps physical to link layer , Quad SPI-3 to SPI-4 PHY Layer Bridge Core April 2004 IP Data Sheet Features ­ , -3 bus Complete Quad SPI-3 to SPI-4 PHY Layer Bridge Solution Based on the ORCA® ORSPI4 FPSC IP , -01.0, Including: ­ ­ ­ ­ SPI-4 Functionality Supported by the Embedded Section of the ORSPI4, Including , at the receive interface ­ Single-link and multi-link operation ­ SPI-4.2 transmit data protocol Lattice Semiconductor
Original
SPI-324P-O4-N1 TSX 07 software DPRAM Quad SPI MPC860 OIF-SPI3-01 TN1017 104MH
Abstract: SPI EXCHANGE 2 x SPI-3 TO SPI-4 Issue 1.0 FEATURES · Functionality - Low speed to high speed SPI exchange device - Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP , , 19.44-133 MHz, 256 address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 128 concurrently active LPs - SPI-4 FIFO status channel options: · LVDS , mode of operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire Silicon Laboratories
Original
C8051F700 TQFP64 TQFP48 high level block diagram for eeprom 8051 spi eeprom Silabs EEPROM QFN48
Abstract: PRODUCT BRIEF IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 To request the full IDT88P8341 , Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP configurable memory allocation , range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 64 concurrently active LPs - SPI-4 FIFO status channel options: â'¢ LVDS full-rate â'¢ LVTTL , SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire frequency range - SPI-4 Lattice Semiconductor
Original
verilog code for spi4.2 interface LFSC25 DDR2 routing Tree LFSC115 qdr2 sram R28C9A 700MH
Abstract: applications. The device supports a System Packet Interface Level 4 Phase 2 (SPI4-2) system interface to the , physical connectivity System Packet Interface Level 4 Phase 2 (SPI4-2) - Capable of data transfers from , 6.2.1.2 TXFIFO relation to SPI4-2 Transmit FIFO Status (TSTAT).91 6.2.1.3 TX FIFO Drain , . 93 6.3.1 SPI4-2 Initialization. 93 6.3.1.1 RX SPI4 Vitesse Semiconductor
Original
leaky ASIC, FCBGA VSC7350 VPPD-02129
Abstract: PRODUCT BRIEF IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 - Number of errors - Number of , Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP configurable memory allocation , address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 128 concurrently active LPs - SPI-4 FIFO status channel options: · LVDS full-rate · , operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire frequency range - Intel
Original
RGMII version 1.2a specification B2584-02 SFF-8053 IXF1110 B2510 AD10 552-C B2577-01
Abstract: -192 in less than a decade. System-Packet Interface (SPI4.2) Resource-strapped equipment vendors must , . SPI4.2 (System-Packet Interface, Level 4, Phase 2) is a recent system-level interface standard that , infrastructure. Published in 2001 by the Optical Internetworking Forum (OIF), the SPI4.2 standard allows the , SAN. SPI4.2 relieves designers from wasting valuable resources on proprietary ASIC-based or , packet transfer between a MAC device and a network processor or switch fabric, the SPI4.2 interface Lattice Semiconductor
Original
L211C 3100B L17c l71c R68T FE1036 F1156 ORSPI4-2FE1036CES ORSPI4-1FE1036CES ORSPI4-2F1156CES ORSPI4-1F1156CES
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