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Part Manufacturer Description PDF Samples Ordering
DS2114Z/T&R Maxim Integrated Products SCSI Terminator ri Buy
DS21T07E/T&R/C01 Maxim Integrated Products SCSI Terminator ri Buy
DS21T07S/T&R/C02 Maxim Integrated Products SCSI Terminator ri Buy

SPI-4 Datasheet

Part Manufacturer Description PDF Type Ordering
SPI-4 Exemplar Logic, Inc. Core w/ FIFOs V1.0 For Altera PLDs
ri

3 pages,
85.02 Kb

Original Buy
datasheet frame
SPI42N03S2L-13 N/A OptiMOS Power Amplifier, 30V 42A 64W, MOS-FET N-Channel enhanced
ri

8 pages,
517.02 Kb

Original Buy
datasheet frame
SPI42N03S2L-13 Infineon Technologies OptiMOS Power-Transistor
ri

8 pages,
410.79 Kb

Original Buy
datasheet frame
SPI42N03S2L-13 Infineon Technologies OptiMOS Power-Transistor
ri

10 pages,
538.12 Kb

Original Buy
datasheet frame
SPI47N10 Infineon Technologies SIPMOS Power-Transistor
ri

8 pages,
104.75 Kb

Original Buy
datasheet frame
SPI47N10 Infineon Technologies SIPMOS Power-Transistor
ri

8 pages,
508.5 Kb

Original Buy
datasheet frame
SPI47N10L Infineon Technologies SIPMOS Power-Transistor
ri

8 pages,
110.86 Kb

Original Buy
datasheet frame
SPI47N10L Infineon Technologies SIPMOS Power-Transistor
ri

8 pages,
511.17 Kb

Original Buy
datasheet frame

SPI-4

Catalog Datasheet Results Type PDF Document Tags
Abstract: SPI4-02.0 System Packet Interface Level 4(SPI-4) Phase 2 standard · Supports aggregate bandwidth for OC192 OC192 , System Packet Interface Level-4P2 OIF Compliant SPI-4P2 IO macro and core logic IP for SPI-4PS and NPSI Link Device Rx-Link Tx-Link SPI-4 Core Logic (data receive) SPI-4 IO data receiver LVDS receiver deskew 1:4 Parallel-Serial SPI-4 Core Logic (data transmit) SPI-4 IO status driver SPI-4 IO data driver SPI-4 IO status receiver LVTTL or LVDS driver (4:1 PS for LVDS ... Original
datasheet

2 pages,
28.23 Kb

SPI4 SPI-4PS OC192 DDR PHY ASIC fujitsu lvds standard spi demux datasheet abstract
datasheet frame
Abstract: Data Tx FIFO(s) Spi4Tx PHY Layer Processor SPI-4 I/F PluriBus Interface Link Layer Line Rx Data Spi4Rx Control Rx FIFO(s) Status Figure 1: SPI-4 Phase 1 PHY Layer , Spi4Rx PHY Layer Sink FIFO(s) SPI-4 I/F Link Atlantic Interface Line Tx Data , Spi4Tx Detailed documentation: Figure 2: SPI-4 Phase 1 Link Layer Application On the system side , initiates a data transfer from the Source FIFO towards the SPI-4 interface. The Spi4Rx block transmits the ... Original
datasheet

3 pages,
85.04 Kb

spi demux datasheet abstract
datasheet frame
Abstract: OIF -4 (SPI-4, System Packet Interface-4) Phase 2 OptiPHY-F10G SPI-4 Phase 2 SDH/SONET Virtex®-II FPGA PL4 SPI-4 Phase 4 Xilinx FPGA SDH/SONET Xilinx Virtex®-II FPGA OC-192 OC-192 (10Gbps , /SONET OIF SPI-4 Phase 2 POS Ail Mesri SPI-4 Phase 2 Xilinx Virtex®-II FPGA OC-192 OC-192 , , Packet-over-SONET 10 Gigabit Ethernet SPI-4 Phase 2 SATURN PL4 PL4 LogiCORETM Vertex®-II FPGA $18,000 , 2.5Gbps OptiPHY-F10G OC-192 OC-192 10 Gbps SPI-4 Phase 2 50% OptiPHY-F10G SONET SDH 10 Gbps OC-192 OC-192 ... Original
datasheet

3 pages,
168.62 Kb

STM-64 M29730 OC-192 10 Gbps ethernet phy OC-48 OC-192 abstract
datasheet frame
Abstract: Xilinx PL4 (OIF, Optical Internetworking Forum)-4(SPI-4, System Packet Interface-4) Phase 2 OptiPHYF10G(M29730 M29730) SPI-4 Phase 2 SONET Virtex®-II FPGA PL4 SPI-4 Phase 2 Xilinx FPGA SONET , OC-192/4xOC-48 SONET/SDH (M29730 M29730) OIF SPI-4 Phase 2 Packet-over-SONET Ail Mesri Xilinx Virtex®-II FPGA, SPI-4 Phase 2 OC-192 OC-192 iScaleTM IC Xilinx Virtex®-II FPGA PL4 terabit Xilinx IP , FPGA SystemIO PL4 PL4-based 10 Gigabit ATM, Packet-over-SONET 10 Gigabit Ethernet SPI-4 Phase ... Original
datasheet

3 pages,
145.45 Kb

xilinx STM-64 M29730 FPGA Virtex 6 Ethernet OC-192 OC192 OC-48 OC-192/ OC-48/STM-16 OC-192 abstract
datasheet frame
Abstract: PRODUCT BRIEF IDT88P8344 IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4 - Number of errors - Number of , Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP configurable memory allocation , address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 256 concurrently active LPs - SPI-4 FIFO status channel options: · LVDS full-rate · , operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire frequency range - ... Original
datasheet

5 pages,
55.5 Kb

IDT88P8344 DSC-6370 spi FIFO IDT88P8344 abstract
datasheet frame
Abstract: NETWORK PRODUCTS VSC874 VSC874 GigaStream® 10 Gbps Queue Manager with Integrated SPI4.2 Interface VSC874 VSC874 Ingress Queues . . . HSSL HSSL MANAGER MANAGER SPI4.2 Interface SPI4.2 Interface Static Load Balancer Packet Segmentation SPI4.2 PHY LOGIC DATA PROCESSING DATA PROCESSING , : SPI4.2 Interface A standard 10 Gbps Interface 16 High-speed Serial Links Provides 40 Gbps of , Media Gateways PB-VSC0874-001 PB-VSC0874-001 VSC874 VSC874 GigaStream® 10 Gbps Queue Manager with Integrated SPI4.2 ... Original
datasheet

2 pages,
498.49 Kb

VSC882 VSC872 Vitesse BGA 672 Speed VSC874 VSC874 abstract
datasheet frame
Abstract: PRODUCT BRIEF IDT88P8342 IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 - Number of errors - Number of , Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP configurable memory allocation , address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 128 concurrently active LPs - SPI-4 FIFO status channel options: · LVDS full-rate · , operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire frequency range - ... Original
datasheet

5 pages,
52.77 Kb

IDT88P8342 spi on parallel port IDT88P8342 abstract
datasheet frame
Abstract: Internetworking Forum (OIF)-compliant System Packet Interface Level-4 Phase 2 (SPI4.2) interface core promise , DRAM and SPI4.2 interface core 1 To implement efficient IP processing, the larger memory size and , NEC Electronics successfully combined embedded DRAM and the SPI4.2 core on the same silicon chip (code-named "ATOLL"), which consists of two 10 Mb embedded DRAM instances and two full-duplex SPI4.2 ports. ATOLL FEATURES - - - SPI4.2 - The total data throughput: 40 Gbps - Receiving performance ... Original
datasheet

6 pages,
2736.95 Kb

SP14 embedded dram "embedded dram" nec OC-192/STM-64 OC-192/STM-64 abstract
datasheet frame
Abstract: LatticeSCM SPI4.2 Interoperability with PMC-Sierra PM3388 PM3388 August 2006 Technical Note TN1121 TN1121 Introduction The System Packet Interface, Level 4, Phase 2 (SPI4.2) is a system level interface, published in , and a network processor or switch fabric, the SPI4.2 interface supports the aggregate bandwidths required of ATM and packet-over-SONET/SDH (POS) applications. Moreover, SPI4.2 provides a common interface , into a single 10Gbps uplink for long haul or backbone transmission. Typically, SPI4.2 has a 16-bit ... Original
datasheet

9 pages,
3392.06 Kb

DDR2 sodimm pcb layout PM3388 AX4000 TN1121 OC-192 PM-3388 PM3388 abstract
datasheet frame
Abstract: SPI4.2 Interoperability Between ORSPI4 and LatticeSC Devices June 2006 Technical Note TN1116 TN1116 Introduction The System Packet Interface, Level 4, Phase 2 (SPI4.2) is a system level interface, published in , between a MAC device and a network processor or switch fabric, the SPI4.2 interface supports the aggregate bandwidths required of ATM and packet-over-Sonet/SDH (POS) applications. Moreover, SPI4.2 , , SPI4.2 has a 16-bit LVDS interface that operates at rates from 622Mbps to 900Mbps. These high data rates ... Original
datasheet

9 pages,
1361.46 Kb

POWR1208 pDS4102-DL2A ORSPI4-2FE1036C IXF18101 TN1116 OC-192 TN1116 abstract
datasheet frame
Abstract: SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 FEATURES · Functionality - Low speed to high speed SPI exchange device - Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP , , 19.44-133 MHz, 256 address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 256 concurrently active LPs - SPI-4 FIFO status channel options: · LVDS , mode of operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire ... Original
datasheet

98 pages,
644.12 Kb

IDT88P8344 IDT88P8344 abstract
datasheet frame
Abstract: SPI EXCHANGE 2 x SPI-3 TO SPI-4 Issue 1.0 FEATURES · Functionality - Low speed to high speed SPI exchange device - Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP , , 19.44-133 MHz, 256 address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 128 concurrently active LPs - SPI-4 FIFO status channel options: · LVDS , mode of operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire ... Original
datasheet

98 pages,
631.34 Kb

IDT88P8342 IDT88P8342 abstract
datasheet frame
Abstract: SPI EXCHANGE SPI-3 TO SPI-4 Issue 1.0 FEATURES · Functionality - Low speed to high speed SPI exchange device - Logical port (LP) mapping (SPI-3 SPI-4) tables per direction - Per LP configurable , address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 64 concurrently active LPs - SPI-4 FIFO status channel options: · LVDS full-rate · , operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire frequency range - ... Original
datasheet

96 pages,
532.14 Kb

TSOP 28 SPI memory Package flash spi flash parallel port JTAG MODULE SPI IDT88P8341 IDT88P8341 abstract
datasheet frame
Abstract: GbE line cards · SPI-4 extension over XAUI backplanes · Ethernet over SONET line cards 2 - 10 GbE , interface · Up to 48 1 GbE ports from two VSC7344 VSC7344 Barrington-II MAC devices can be mapped to 48 SPI-4 channels; or up to 48 SPI-4 channels can be mapped to two XAUI ports including per-channel QoS and flow , VSC7350 VSC7350, and between VSC7350 VSC7350 and the SPI-4 host interface · SPI-4 scheduler with weighted scheduling across 48 SPI-4 channels · XAUI scheduler with weighted scheduling across 24 logical ports on each XAUI ... Original
datasheet

2 pages,
250.78 Kb

leaky VSC7350 VSC7350 abstract
datasheet frame

Datasheet Content (non pdf)

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Xilinx 31/03/2004 399.48 Kb ZIP xapp525.zip
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Xilinx 31/03/2004 399.48 Kb ZIP xapp525.zip
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Xilinx 31/03/2004 399.48 Kb ZIP xapp525.zip
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Xilinx 31/03/2004 399.48 Kb ZIP xapp525.zip
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Xilinx 31/03/2004 399.48 Kb ZIP xapp525.zip
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Xilinx 31/03/2004 399.48 Kb ZIP xapp525.zip
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Xilinx 31/03/2004 399.48 Kb ZIP xapp525.zip
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Xilinx 31/03/2004 399.48 Kb ZIP xapp525.zip
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Xilinx 31/03/2004 399.48 Kb ZIP xapp525.zip
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Xilinx 31/03/2004 399.48 Kb ZIP xapp525.zip

Shortform Datasheet Search Results

Part Manufacturer Description Shortform Datasheet Ordering
SPI4 Silicon Sensors, Inc. Transistor-Stage-Output Optocoupler - Photo Interrupter

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Fairchild Cross Reference Results

Fairchild Part Orderable Industry Part Manufacturer Type Family Description
FDI3632 FDI3632 Buy SPI47N10 Buy Infineon (Siemens) Close Power MOSFET 100V N-Channel Trench MOSFET

Misc. Cross Reference Results

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SPI42N03S2L-13 Buy STB70NF03L-1 Buy